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  • This comparison shows the changes necessary to convert path 
    /raytrac/branches/fp_sgdma
    from Rev 198 to Rev 199
    ↔ Reverse comparison
  •

Rev 198 → Rev 199

/memblock.vhd
27,7 → 27,6
entity memblock is
generic (
blocksize : integer := 512;
external_readable_widthad : integer := 3;
external_writeable_widthad : integer := 4
34,22 → 33,21
);
port (
qempty : out std_logic_vector (4 downto 0); --! Res0:0 Res1:1 Res2:2 Res3:3 Prm:4
clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
instrfifo_rd : in std_logic;
resultfifo_wr: in std_logic_vector(8-1 downto 0);
instrfifo_empty: out std_logic;
resultfifo_wr: in std_logic_vector(3 downto 0);
ext_rd,ext_wr: in std_logic;
ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
ext_rd_add : in std_logic_vector(3 downto 0);
ext_d: in std_logic_vector(floatwidth-1 downto 0);
resultfifo_full : out std_logic_vector(3 downto 0);
int_d : in vectorblock08;
ext_d: in xfloat32;
int_d : in vectorblock04;
status_register : in std_logic_vector(3 downto 0);
ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
int_q : out vectorblock12;
int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
ext_q: out xfloat32;
int_q : out vectorblock06;
address : in std_logic_vector(1 downto 0);
dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
62,10 → 60,20
 
--!TBXSTART:LOAD_CHAIN
signal sparams_chain : std_logic_vector (5 downto 0);
signal sparams_load : std_logic_vector (5 downto 0);
signal scomb : std_logic;
signal sgo : std_logic;
signal sqparams_q : xfloat32;
signal s1int_q : vectorblock06;
signal sload_params_cfg : std_logic;
signal sqparams_not_empty : std_logic;
signal sqparams_empty : std_logic;
--!TBXEND
--!TXBXSTART:MEMBLOCK_EXTERNAL_WRITE
signal s0ext_wr_add_one_hot : std_logic_vector(12-1+1 downto 0); --! La señal extra es para la escritura de la cola de instrucciones.
signal s0ext_wr_add : std_logic_vector(4+widthadmemblock-1 downto 0);
signal s0ext_wr : std_logic;
signal s0ext_d : std_logic_vector(floatwidth-1 downto 0);
--!TBXEND
81,10 → 89,6
--!TBXEND
--!TBXSTART:MEMBLOCK_INTERNAL_READ
signal sint_rd_add : vectorblockadd02;
signal s1int_q : vectorblock12;
--!TBXEND
--!TXBXSTART:MEMBLOCK_INTERNAL_WRITE
signal sint_d : vectorblock08;
94,137 → 98,96
begin
load_chain_proc: process (clk,rst,sparams_chain,sparams_load,sload_params_cfg,scomb,sgo,sparams_unload)
begin
if rst=rstMasterValue then
--!LD Section
sparams_chain <= (others => '0');
for i in 5 downto 0 loop
s1int_q <= (others => '0');
end loop;
elsif clk'event and clk='1' then
--LOAD SECTION COMBINATORIAL CIRCUIT
--! Ax enabler.
if sload_params_cfg='1' then
sparams_chain(0) <= sparams_load(0);
elsif sgo='1' then
sparams_chain(0) <= sparams_chain(5) and not(scomb);
else
sparams_chain(0) <= sparams_chain(0);
end if;
--! Ay Az By Bz Enabler.
for i in 2 downto 1 loop
if sload_params_cfg='1' then
sparams_chain(i) <= sparams_load(i);
sparams_chain(i+3) <= sparams_load(i+3);
elsif sgo='1' tjem
sparams_chain(i) <= sparams_chain(i-1);
sparams_chain(i+3) <= sparams_chain(i-2);
else
sparams_chain(i) <= sparams_chain(i);
sparams_chain(i+3) <= sparams_chain(i+3);
end if;
end loop;
--! Bx enabler.
if sload_params_cfg='1' then
sparams_chain(3) <= sparams_load(3);
elsif sgo='1' then
if scomb='1' then
sparams_chain(3) <= sparams_chain(5);
else
sparams_chain(3) <= sparams_chain(2);
end if;
else
sparams_chain(3) <= sparams_chain(3);
end if;
for i in 5 downto 0 loop
if sparams_chain(i)='1' then
s1int_q(i) <= sqparams_q;
end if;
end loop;
end if
end process;
 
 
--! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.
q0q1 : scfifo --! Debe ir registrada la salida.
generic map (
add_ram_output_register => "OFF",
allow_rwcycle_when_full => "OFF",
intended_device_family => "CycloneIII",
lpm_hint => "MAXIMUM_DEPTH=8",
almost_full_value => 8,
lpm_numwords => 8,
lpm_showahead => "ON",
lpm_type => "SCIFIFO",
lpm_width => 64,
lpm_widthu => 3,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "OFF"
)
port map (
rdreq => dpfifo_rd,
aclr => '0',
empty => open,
clock => clk,
q => dpfifo_q,
wrreq => dpfifo_wr,
data => dpfifo_d
);
--! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute;tico
qxqyqz : scfifo
generic map (
--! Instanciaci&oacute;n de la cola de resultados de salida.
int_q <= s1int_q;
qempty(4) <= sqparams_empty;
sgo <= not(sqparams_empty);
qparams : scififo
generic map(
add_ram_output_register => "OFF",
allow_rwcycle_when_full => "OFF",
intended_device_family => "Cyclone III",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
almost_full_value => 32,
lpm_numwords => 32,
lpm_showahead => "OFF",
lpm_type => "SCFIFO",
lpm_width => 96,
lpm_widthu => 5,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
rdreq => normfifo_rd,
aclr => '0',
empty => open,
clock => clk,
q => normfifo_q,
wrreq => normfifo_wr,
data => normfifo_d,
almost_full => open,
full => open
);
--! Cola de instrucciones
qi : scfifo
generic map (
add_ram_output_register => "OFF",
allow_rwcycle_when_full => "OFF",
intended_device_family => "Cyclone III",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
almost_full_value => 16,
lpm_numwords => 16,
lpm_numwords => 256,
lpm_showahead => "ON",
lpm_type => "SCIFIFO",
lpm_width => 32,
lpm_widthu => 4,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "OFF"
use_eab => "ON"
)
port map (
rdreq => instrfifo_rd,
aclr => '0',
empty => instrfifo_empty,
clock => clk,
q => instrfifo_q,
wrreq => s0ext_wr_add_one_hot(12),
data => s0ext_d,
almost_full => open
);
--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de c&oacute;digo, no influye en la sintesis del circuito.
sint_rd_add (0)<= int_rd_add(widthadmemblock-1-memoryreduction downto 0);
sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1-memoryreduction downto widthadmemblock);
--! Instanciaci&oacute;n de la cola de resultados de salida.
int_q <= s1int_q;
operands_blocks:
for i in 11 downto 0 generate
--!int_q((i+1)*floatwidth-1 downto floatwidth*i) <= s1int_q(i);
operandsblock : altsyncram
generic map (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**(widthadmemblock-memoryreduction),
numwords_b => 2**(widthadmemblock-memoryreduction),
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
rdcontrol_reg_b => "CLOCK0",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => widthadmemblock-memoryreduction,
widthad_b => widthadmemblock-memoryreduction,
width_a => floatwidth,
width_b => floatwidth,
width_byteena_a => 1
)
port map (
wren_a => s0ext_wr_add_one_hot(i),
clock0 => clk,
address_a => s0ext_wr_add(widthadmemblock-1-memoryreduction downto 0),
address_b => sint_rd_add((i/3) mod 2),
rden_b => '1',
q_b => s1int_q(i),
data_a => s0ext_d
);
end generate operands_blocks;
port map (
rdreq =>
aclr => '0',
empty => qparams_empty,
clock => clk,
q => sqparams_q,
wrreq => ext_wr,
data => ext_d
)
--! Instanciaci&oacute;n de la cola de resultados.
resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
232,11 → 195,10
resultfifo_full(0) <= sresultfifo_full(0);
sint_d <= int_d;
results_blocks:
for i in 7 downto 0 generate
for i in 3 downto 0 generate
resultsfifo : scfifo
generic map (
add_ram_output_register => "OFF",
almost_full_value => 224,
allow_rwcycle_when_full => "OFF",
intended_device_family => "Cyclone III",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
244,7 → 206,6
lpm_showahead => "ON",
lpm_type => "SCIFIFO",
lpm_width => 32,
lpm_widthu => 8,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
277,44 → 238,8
end if;
end process;
--! Decodificaci&oacute;n de se&ntilde;al escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la direcci&oacute;n de entrada.
s0ext_wr_add_choice <= s0ext_wr_add(4+widthadmemblock-1 downto widthadmemblock);
operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)
begin
--! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como est&aacute; el pool de direcciones por bloques de vectores.
--! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
case s0ext_wr_add_choice is
when "0000" =>
s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
when x"1" =>
s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
when x"2" =>
s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
when x"4" =>
s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
when x"5" =>
s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
when x"6" =>
s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
when x"8" =>
s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
when x"9" =>
s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
when x"A" =>
s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
when x"C" =>
s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
when x"D" =>
s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
when x"E" =>
s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
when others =>
s0ext_wr_add_one_hot <= s0ext_wr&x"000";
end case;
end process;
--! Decodificaci&oacute;n para seleccionar que cola de resultados se conectar&acute; a la salida del RayTrac.
results_block_proc: process(clk,rst)
390,6 → 315,60
end if;
end process;
--! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.
q0q1 : scfifo --! Debe ir registrada la salida.
generic map (
add_ram_output_register => "OFF",
allow_rwcycle_when_full => "OFF",
intended_device_family => "CycloneIII",
lpm_hint => "MAXIMUM_DEPTH=8",
almost_full_value => 8,
lpm_numwords => 8,
lpm_showahead => "ON",
lpm_type => "SCIFIFO",
lpm_width => 64,
lpm_widthu => 3,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "OFF"
)
port map (
rdreq => dpfifo_rd,
aclr => '0',
empty => open,
clock => clk,
q => dpfifo_q,
wrreq => dpfifo_wr,
data => dpfifo_d
);
--! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute;tico
qxqyqz : scfifo
generic map (
add_ram_output_register => "OFF",
allow_rwcycle_when_full => "OFF",
intended_device_family => "Cyclone III",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
almost_full_value => 32,
lpm_numwords => 32,
lpm_showahead => "OFF",
lpm_type => "SCFIFO",
lpm_width => 96,
lpm_widthu => 5,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
rdreq => normfifo_rd,
aclr => '0',
empty => open,
clock => clk,
q => normfifo_q,
wrreq => normfifo_wr,
data => normfifo_d,
almost_full => open,
full => open
);
end architecture;
 

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