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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /raytrac/branches
    from Rev 231 to Rev 232
    ↔ Reverse comparison
  •

Rev 231 → Rev 232

/fp_sgdma/raytrac_hw.tcl
1,5 → 1,5
# TCL File Generated by Component Editor 11.0
# Sun Aug 12 22:31:43 COT 2012
# Thu Aug 30 11:19:35 COT 2012
# DO NOT MODIFY
 
 
6,10 → 6,10
# +-----------------------------------
# |
# | raytrac "raytrac" v1.0
# | null 2012.08.12.22:31:43
# | null 2012.08.30.11:19:35
# |
# |
# | J:/code/RtEngineHw/SlaveInterfaceDrive/fp_sgdma/raytrac.vhd
# | J:/code/hworkspace/raytrac/fp_sgdma/raytrac.vhd
# |
# | ./raytrac.vhd syn
# | ./arithpack.vhd syn
57,7 → 57,6
set_parameter_property wd DISPLAY_NAME wd
set_parameter_property wd TYPE INTEGER
set_parameter_property wd UNITS None
set_parameter_property wd ALLOWED_RANGES -2147483648:2147483647
set_parameter_property wd AFFECTS_GENERATION false
set_parameter_property wd HDL_PARAMETER true
add_parameter fd INTEGER 8
65,15 → 64,13
set_parameter_property fd DISPLAY_NAME fd
set_parameter_property fd TYPE INTEGER
set_parameter_property fd UNITS None
set_parameter_property fd ALLOWED_RANGES -2147483648:2147483647
set_parameter_property fd AFFECTS_GENERATION false
set_parameter_property fd HDL_PARAMETER true
add_parameter mb INTEGER 3
set_parameter_property mb DEFAULT_VALUE 3
add_parameter mb INTEGER 4
set_parameter_property mb DEFAULT_VALUE 4
set_parameter_property mb DISPLAY_NAME mb
set_parameter_property mb TYPE INTEGER
set_parameter_property mb UNITS None
set_parameter_property mb ALLOWED_RANGES -2147483648:2147483647
set_parameter_property mb AFFECTS_GENERATION false
set_parameter_property mb HDL_PARAMETER true
# |
86,14 → 83,14
# +-----------------------------------
 
# +-----------------------------------
# | connection point rtClock
# | connection point clock
# |
add_interface rtClock clock end
set_interface_property rtClock clockRate 0
add_interface clock clock end
set_interface_property clock clockRate 0
 
set_interface_property rtClock ENABLED true
set_interface_property clock ENABLED true
 
add_interface_port rtClock clk clk Input 1
add_interface_port clock clk clk Input 1
# |
# +-----------------------------------
 
103,8 → 100,8
add_interface rtSlave avalon end
set_interface_property rtSlave addressAlignment DYNAMIC
set_interface_property rtSlave addressUnits WORDS
set_interface_property rtSlave associatedClock rtClock
set_interface_property rtSlave associatedReset rtReset
set_interface_property rtSlave associatedClock clock
set_interface_property rtSlave associatedReset reset_sink
set_interface_property rtSlave burstOnBurstBoundariesOnly false
set_interface_property rtSlave explicitAddressSpan 0
set_interface_property rtSlave holdTime 0
131,25 → 128,12
# +-----------------------------------
 
# +-----------------------------------
# | connection point rtReset
# |
add_interface rtReset reset end
set_interface_property rtReset associatedClock rtClock
set_interface_property rtReset synchronousEdges BOTH
 
set_interface_property rtReset ENABLED true
 
add_interface_port rtReset rst reset_n Input 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point rtMaster
# |
add_interface rtMaster avalon start
set_interface_property rtMaster addressUnits SYMBOLS
set_interface_property rtMaster associatedClock rtClock
set_interface_property rtMaster associatedReset rtReset
set_interface_property rtMaster associatedClock clock
set_interface_property rtMaster associatedReset reset_sink
set_interface_property rtMaster burstOnBurstBoundariesOnly false
set_interface_property rtMaster doStreamReads false
set_interface_property rtMaster doStreamWrites false
158,14 → 142,14
 
set_interface_property rtMaster ENABLED true
 
add_interface_port rtMaster master_address address Output 32
add_interface_port rtMaster master_waitrequest waitrequest Input 1
add_interface_port rtMaster master_burstcount burstcount Output 5
add_interface_port rtMaster master_waitrequest waitrequest Input 1
add_interface_port rtMaster master_read read Output 1
add_interface_port rtMaster master_readdata readdata Input 32
add_interface_port rtMaster master_readdatavalid readdatavalid Input 1
add_interface_port rtMaster master_write write Output 1
add_interface_port rtMaster master_writedata writedata Output 32
add_interface_port rtMaster master_address address Output 32
# |
# +-----------------------------------
 
174,8 → 158,8
# |
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint rtSlave
set_interface_property interrupt_sender associatedClock rtClock
set_interface_property interrupt_sender associatedReset rtReset
set_interface_property interrupt_sender associatedClock clock
set_interface_property interrupt_sender associatedReset reset_sink
 
set_interface_property interrupt_sender ENABLED true
 
182,3 → 166,16
add_interface_port interrupt_sender irq irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point reset_sink
# |
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges BOTH
 
set_interface_property reset_sink ENABLED true
 
add_interface_port reset_sink rst reset_n Input 1
# |
# +-----------------------------------

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