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  • This comparison shows the changes necessary to convert path 
    /raytrac/trunk/sqrtdiv
    from Rev 80 to Rev 81
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Rev 80 → Rev 81

/func.vhd File deleted
/RLshifter.vhd
56,11 → 56,7
process (mantis,exp)
variable expi : integer ;
begin
if shiftFunction="INVERSION" then
expi:= conv_integer(exp);
else
expi:= conv_integer(exp(exp'high downto 1)); --! Por qu'e hasta 1 y no hasta 0!? Porque el corrimiento de la raiz cuadrada es 2^(N/2)
end if;
expi:= conv_integer(exp(exp'high downto 1)); --! Por qu'e hasta 1 y no hasta 0!? Porque el corrimiento de la raiz cuadrada es 2^(N/2)
for i in owidth-1 downto 0 loop
 
/funcsqrt.vhd
0,0 → 1,142
------------------------------------------------
--! @file func.vhd
--! @brief Functions for calculating x**-1, x**0.5, 2x**0.5
--! @author Julián Andrés Guarín Reyes
--------------------------------------------------
 
 
-- RAYTRAC
-- Author Julian Andres Guarin
-- func.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
 
 
 
library ieee;
use ieee.std_logic_1164.all;
 
 
library altera_mf;
use altera_mf.all;
 
entity func is
generic (
memoryfilepath : string :="X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif";
awidth : integer := 9;
qwidth : integer := 18
);
port (
ad0,ad1 : in std_logic_vector (awidth-1 downto 0) := (others => '0');
clk : in std_logic;
q0,q1 : out std_logic_vector(qwidth-1 downto 0)
);
end func;
 
architecture func_arch of func is
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
END COMPONENT;
 
begin
 
altsyncram_component : altsyncram
generic map (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
--init_file => "X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif",
init_file => memoryfilepath,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 512,
numwords_b => 512,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
widthad_a => 9,
widthad_b => 9,
width_a => 18,
width_b => 18,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
port map (
clock0 => clk,
wren_a => '0',
address_b => ad1,
data_b => (others=>'0'),
wren_b => '0',
address_a => ad0,
data_a => (others=>'0'),
q_b => q1,
q_a => q0
);
 
 
end func_arch;
 
 
 
 
/sqrtdiv.vhd
34,8 → 34,7
reginput: string := "YES";
c3width : integer := 18;
functype: string := "INVERSION";
iwidth : integer := 18;
owidth : integer := 18;
iwidth : integer := 32;
awidth : integer := 9
);
port (
42,7 → 41,9
clk,rst : in std_logic;
value : in std_logic_vector (iwidth-1 downto 0);
zero : out std_logic;
result : out std_logic_vector (owidth-1 downto 0)
sqr : out std_logic_vector (15 downto 0);
inv : out std_logic_vector (16 downto 0)
);
end sqrtdiv;
 
60,24 → 61,28
signal funkyexp : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal funkyzero : std_logic;
signal funkyq : std_logic_vector (2*c3width+3 downto 0);
signal funkyq : std_logic_vector (2*c3width-1 downto 0);
signal funkyselector : std_logic;
--! cumpa::Tercera etapa: Selecci'on de valores de acuerdo al exp escogido.
signal cumpaexp : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal cumpaq : std_logic_vector (2*c3width+3 downto 0);
signal cumpaq : std_logic_vector (2*c3width-1 downto 0);
signal cumpaselector : std_logic;
signal cumpazero : std_logic;
signal cumpaN : std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal cumpaF : std_logic_vector (c3width+1 downto 0);
signal cumpaF : std_logic_vector (c3width-1 downto 0);
--! chief::Cuarta etapa: Corrimiento a la izquierda o derecha, para el caso de la ra'iz cuadrada o la inversi'on respectivamente.
signal chiefN : std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal chiefF : std_logic_vector (c3width+1 downto 0);
signal chiefF : std_logic_vector (c3width-1 downto 0);
signal chiefQ : std_logic_vector (c3width-1 downto 0);
--! inverseDistance::Quinta etapa
signal iDistN : std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal iDistF : std_logic_vector (c3width-1 downto 0);
--! Constantes para manejar el tama&ntilde;o de los vectores
constant exp1H : integer := 2*integer(ceil(log(real(iwidth),2.0)))-1;
constant exp1L : integer := integer(ceil(log(real(iwidth),2.0)));
89,9 → 94,9
constant add0L : integer := 0;
constant c3qHH : integer := 2*c3width+3;
constant c3qHL : integer := c3width+2;
constant c3qLH : integer := c3width+1;
constant c3qHH : integer := 2*c3width-1;
constant c3qHL : integer := c3width;
constant c3qLH : integer := c3width-1;
constant c3qLL : integer := 0;
begin
147,39 → 152,22
end if;
end process funkyget;
funkyinversion:
if functype="INVERSION" generate
meminvr:func
generic map (memoryPath&"meminvr.mif")
port map(
expomantisadd(awidth-1 downto 0),
expomantisadd(2*awidth-1 downto awidth),
clk,
funkyq(c3qLH-2 downto c3qLL),
funkyq(c3qHH-2 downto c3qHL));
end generate funkyinversion;
funkysquare_root:
if functype="SQUARE_ROOT" generate
sqrt: func
generic map (memoryPath&"memsqrt.mif")
port map(
expomantisadd(awidth-1 downto 0),
(others => '0'),
clk,
funkyq(c3qLH-2 downto c3qLL),
open);
 
sqrt2x: func
generic map (memoryPath&"memsqrt2f.mif")
port map(
(others => '0'),
expomantisadd(2*awidth-1 downto awidth),
clk,
open,
funkyq(c3qHH-2 downto c3qHL));
sqrt: funcinvr
generic map (memoryPath&"memsqrt.mif")
port map(
funkyadd(awidth-1 downto 0),
clk,
funkyq(c3qLH downto c3qLL));
sqrt2x: funcinvr
generic map (memoryPath&"memsqrt2f.mif")
port map(
funkyadd(2*awidth-1 downto awidth),
clk,
funkyq(c3qHH downto c3qHL));
end generate funkysquare_root;
--! cumpa.
cumpaProc:
209,7 → 197,9
end if;
end process cumpaMux;
--! chief.
--! Branching.
-- exp <= chiefN;
-- fadd <= chiefF(c3width-2 downto c3width-1-awidth);
chiefProc:
process (clk,rst)
begin
223,12 → 213,63
end if;
end process chiefProc;
chiefShifter: RLshifter
generic map(functype,c3width+2,iwidth,owidth)
generic map("SQUARE_ROOT",c3width,iwidth,16)
port map(
chiefN,
chiefF,
result);
sqr);
branching_invfunc:
if functype="INVERSION" generate
sqrt: funcinvr
generic map (memoryPath&"meminvr.mif")
port map(
chiefF(c3width-2 downto c3width-1-awidth),
clk,
chiefQ(c3width-1 downto 0));
end generate branching_invfunc;
branchingHighLander:
if functype="SQUARE_ROOT" generate
chiefQ <= (others => '0');
end generate branchingHighLander;
--! Inverse
inverseDistanceOK:
if functype="INVERSION" generate
inverseDistance:
process (clk,rst)
begin
if rst=rstMasterValue then
iDistN <= (others => '0');
iDistF <= (others => '0');
elsif clk'event and clk='1' then
iDistN <= chiefN;
iDistF <= chiefQ;
end if;
end process inverseDistance;
inverseShifter: RLshifter
generic map("INVERSION",c3width,iwidth,17)
port map(
iDistN,
iDistF,
inv);
end generate inverseDistanceOK;
inverseDistanceNOTOK:
if functype = "SQUARE_ROOT" generate
iDistN <= (others => '0');
iDistF <= (others => '0');
inv <= (others => '0');
end generate inverseDistanceNOTOK;
end sqrtdiv_arch;

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