Subversion Repositories raytrac

/adder.vhd

adder.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: arithpack.vhd =================================================================== --- arithpack.vhd (nonexistent) +++ arithpack.vhd (revision 2) @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; + +package arithpack is + component fastmux + generic ( w : integer := 32 ); + port ( + s : in std_logic; + mux0,mux1 : in std_logic_vector (w-1 downto 0); + muxS : out std_logic_vector (w-1 downto 0) + ); + + component r_a18_b18_smul_c32_r + port ( + aclr,clock:in std_logic; + dataa,datab:in std_logic_vector (17 downto 0); + result: out std_logic_vector(31 downto 0) + ); + end component; + component cla_logic_block + generic ( w: integer:=4); + port ( + p,g:in std_logic_vector(w-1 downto 0); + cin:in std_logic; + c:out std_logic_vector(w downto 1) + ); + end component; + component rca_logic_block + generic ( w : integer := 4); + port ( + p,g: in std_logic_vector(w-1 downto 0); + cin: in std_logic; + c: out std_logic_vector(w downto 1) + ); + end component; + component adder + generic ( + w : ingeter := 4; + carry_logic := "CLA"; + subtractor_selector := "YES"; + ); + port ( + a,b : in std_logic_vector (w-1 downto 0); + s,ci : in std_logic; + result : out std_logic_vector (w-1 downto 0); + cout : out std_logic + ); + end component; + +end package;

arithpack.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: cla_logic_block.vhd =================================================================== --- cla_logic_block.vhd (nonexistent) +++ cla_logic_block.vhd (revision 2) @@ -0,0 +1,62 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cla_logic_block is + generic ( + w : integer := 4 + ); + + port ( + p,g : in std_logic_vector(w-1 downto 0); + cin : in std_logic; + + c : out std_logic_vector(w downto 1) + ); +end cla_logic_block; + + +architecture cla_logic_block_arch of cla_logic_block is + + + +begin + + claProc: -- claProc instancia funciones combinatorias en las variables iCarry, + -- pero notese que los valores de iCarry(i) no dependen jamas de iCarry(i-1) a diferencia de rcaProc + process(p,g,cin) + + variable i,j,k : integer range 0 to w; -- Variables de control de loop + variable iCarry: std_logic_vector(w downto 1); -- Carry Interno + variable iResults: std_logic_vector(((w+w**2)/2)-1 downto 0); -- Resultados intermedios + variable index: integer; + begin + + iCarry(w downto 1) := g(w-1 downto 0); + index := 0; + for j in 0 to w-1 loop + for i in 1 to j+1 loop + iResults(index) := '1'; + for k in j-i+1 to j loop + iResults(index) := iResults(index) and p(k); + end loop; + if j>=i then + iResults(index) := iResults(index) and g(j-i); + else + iResults(index) := iResults(index) and cin; + end if; + iCarry(j+1) := iCarry(j+1) or iResults(index); + index := index + 1; + end loop; + + c(j+1) <= iCarry(j+1); + + end loop; + + + + end process claProc; + + + +end cla_logic_block_arch; +

cla_logic_block.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fastmux.vhd =================================================================== --- fastmux.vhd (nonexistent) +++ fastmux.vhd (revision 2) @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.arithpack.all; + +entity fastmux is + generic ( w : integer := 32 ); + port ( + s : in std_logic; + mux0,mux1 : in std_logic_vector(w-1 downto 0); + muxS : out std_logic_vector(w-1 downto 0) + ); +end fastmux; + +architecture fastmux_arch of fastmux is +begin + + muxS <= (mux0 and s) or (mux1 and s); + +end fastmux_arch; + + + \ No newline at end of file

fastmux.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: uf.vhd =================================================================== --- uf.vhd (nonexistent) +++ uf.vhd (revision 2) @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.arithpack.all; + +-- + + +entity uf is + port ( + opcode : in std_logic; + vectors : in std_logic_vector (12*18-1 downto 0); + clk,rst, ena : in std_logic + ); +end uf; + +architecture uf_arch of uf is + + s0_opcode : signal std_logic; + + s1_opcode: signal std_logic; + + s2_opcode : signal std_logic; + s2_prod0,s2_prod1,s2_prod2,s2_prod3,s2_prod4,s2_prod5,s2_sum0,s2_sum1,s2_sum2 : signal std_logic_vector (31 downto 0); + + s3_sum04,s3_sum25,s3_prod2,s3_prod3,s3_sum4,s3_sum5 : signal std_logic_vector ( 31 downto 0); + + +begin + + + + + +end uf_arch;

uf.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rca_logic_block.vhd =================================================================== --- rca_logic_block.vhd (nonexistent) +++ rca_logic_block.vhd (revision 2) @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity rca_logic_block is + generic ( + w : integer := 8 + ); + port ( + p,g: in std_logic_vector(w-1 downto 0); + cin : in std_logic; + + c : out std_logic_vector(w downto 1) + ); +end rca_logic_block; + + +architecture rca_logic_block_arch of rca_logic_block is + + + +begin + + rcaProc: -- rcaProc instancia funciones combinatorias en sCarry(i) haciendo uso de los resultados intermedios obtenidos + -- en sCarry(i-1), por lo que se crea un delay path en el calculo del Cout del circuito + process (p,g,cin) + variable i: integer range 0 to 2*w; + variable sCarry: std_logic_vector(w downto 1); + begin + + sCarry(w downto 1) := g(w-1 downto 0); + sCarry(1) := sCarry(1) or (p(0) and cin); + + for i in 1 to w-1 loop + sCarry(i+1) := sCarry(i+1) or (p(i) and sCarry(i)); + end loop; + + c <= sCarry; + + + end process rcaProc; +end rca_logic_block_arch;

rca_logic_block.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property