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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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  • This comparison shows the changes necessary to convert path 
    /raytrac/trunk
    from Rev 14 to Rev 15
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Rev 14 → Rev 15

/raytrac.vhd
24,7 → 24,7
 
entity raytrac is
generic (
registered : string := "NO"
registered : string := "YES"
);
port (
A,B,C,D : in std_logic_vector(18*3-1 downto 0);
/arithpack.vhd
6,7 → 6,7
 
package arithpack is
constant rstMasterValue : std_logic := '0';
constant rstMasterValue : std_logic := '1';
 
component uf
port (
/uf.vhd
33,23 → 33,23
 
-- Stage 0 signals
signal s0mf00,s0mf01,s0mf10,s0mf11,s0mf20,s0mf21,s0mf30,s0mf31,s0mf40,s0mf41,s0mf50,s0mf51 : std_logic_vector(17 downto 0);
signal s0p0,s0p1, s0p2, s0p3, s0p4, s0p5 : std_logic_vector(31 downto 0);
signal s0opcode : std_logic;
signal stage0mf00,stage0mf01,stage0mf10,stage0mf11,stage0mf20,stage0mf21,stage0mf30,stage0mf31,stage0mf40,stage0mf41,stage0mf50,stage0mf51 : std_logic_vector(17 downto 0);
signal stage0p0,stage0p1, stage0p2, stage0p3, stage0p4, stage0p5 : std_logic_vector(31 downto 0);
signal stage0opcode : std_logic;
--Stage 1 signals
signal s1p0, s1p1, s1p2, s1p3, s1p4, s1p5 : std_logic_vector (31 downto 0);
signal s1a0, s1a1, s1a2 : std_logic_vector (31 downto 0);
signal s1opcode : std_logic;
signal stage1p0, stage1p1, stage1p2, stage1p3, stage1p4, stage1p5 : std_logic_vector (31 downto 0);
signal stage1a0, stage1a1, stage1a2 : std_logic_vector (31 downto 0);
signal stage1opcode : std_logic;
-- Some support signals
signal s1_internalCarry : std_logic_vector(2 downto 0);
signal s2_internalCarry : std_logic_vector(1 downto 0);
signal stage1_internalCarry : std_logic_vector(2 downto 0);
signal stage2_internalCarry : std_logic_vector(1 downto 0);
--Stage 2 signals
signal s2a0, s2a2, s2a3, s2a4, s2p2, s2p3 : std_logic_vector (31 downto 0);
signal stage2a0, stage2a2, stage2a3, stage2a4, stage2p2, stage2p3 : std_logic_vector (31 downto 0);
61,49 → 61,49
port map (
aclr => rst,
clock => clk,
dataa => s0mf00,
datab => s0mf01,
result => s0p0
dataa => stage0mf00,
datab => stage0mf01,
result => stage0p0
);
m1 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
clock => clk,
dataa => s0mf10,
datab => s0mf11,
result => s0p1
dataa => stage0mf10,
datab => stage0mf11,
result => stage0p1
);
m2 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
clock => clk,
dataa => s0mf20,
datab => s0mf21,
result => s0p2
dataa => stage0mf20,
datab => stage0mf21,
result => stage0p2
);
m3 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
clock => clk,
dataa => s0mf30,
datab => s0mf31,
result => s0p3
dataa => stage0mf30,
datab => stage0mf31,
result => stage0p3
);
m4 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
clock => clk,
dataa => s0mf40,
datab => s0mf41,
result => s0p4
dataa => stage0mf40,
datab => stage0mf41,
result => stage0p4
);
m5 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
clock => clk,
dataa => s0mf50,
datab => s0mf51,
result => s0p5
dataa => stage0mf50,
datab => stage0mf51,
result => stage0p5
);
-- Adder Instantiation (sTaGe 1)
115,12 → 115,12
--Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => s1p0(15 downto 0),
b => s1p1(15 downto 0),
s => s1opcode,
a => stage1p0(15 downto 0),
b => stage1p1(15 downto 0),
s => stage1opcode,
ci => '0',
result => s1a0(15 downto 0),
cout => s1_internalCarry(0)
result => stage1a0(15 downto 0),
cout => stage1_internalCarry(0)
);
--Adder 0, high adder
a0high : adder
130,11 → 130,11
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => s1p0(31 downto 16),
b => s1p1(31 downto 16),
s => s1opcode,
ci => s1_internalCarry(0),
result => s1a0(31 downto 16),
a => stage1p0(31 downto 16),
b => stage1p1(31 downto 16),
s => stage1opcode,
ci => stage1_internalCarry(0),
result => stage1a0(31 downto 16),
cout => open
);
--Adder 1, low adder
145,12 → 145,12
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => s1p2(15 downto 0),
b => s1p3(15 downto 0),
s => s1opcode,
a => stage1p2(15 downto 0),
b => stage1p3(15 downto 0),
s => stage1opcode,
ci => '0',
result => s1a1(15 downto 0),
cout => s1_internalCarry(1)
result => stage1a1(15 downto 0),
cout => stage1_internalCarry(1)
);
--Adder 1, high adder
a1high : adder
160,11 → 160,11
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => s1p2(31 downto 16),
b => s1p3(31 downto 16),
s => s1opcode,
ci => s1_internalCarry(1),
result => s1a1(31 downto 16),
a => stage1p2(31 downto 16),
b => stage1p3(31 downto 16),
s => stage1opcode,
ci => stage1_internalCarry(1),
result => stage1a1(31 downto 16),
cout => open
);
--Adder 2, low adder
175,12 → 175,12
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => s1p4(15 downto 0),
b => s1p5(15 downto 0),
s => s1opcode,
a => stage1p4(15 downto 0),
b => stage1p5(15 downto 0),
s => stage1opcode,
ci => '0',
result => s1a2(15 downto 0),
cout => s1_internalCarry(2)
result => stage1a2(15 downto 0),
cout => stage1_internalCarry(2)
);
--Adder 2, high adder
a2high : adder
190,11 → 190,11
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => s1p4(31 downto 16),
b => s1p5(31 downto 16),
s => s1opcode,
ci => s1_internalCarry(2),
result => s1a2(31 downto 16),
a => stage1p4(31 downto 16),
b => stage1p5(31 downto 16),
s => stage1opcode,
ci => stage1_internalCarry(2),
result => stage1a2(31 downto 16),
cout => open
);
208,12 → 208,12
substractor_selector => "NO" --No Just Add.
)
port map (
a => s2a0(15 downto 0),
b => s2p2(15 downto 0),
a => stage2a0(15 downto 0),
b => stage2p2(15 downto 0),
s => '0',
ci => '0',
result => s2a3(15 downto 0),
cout => s2_internalCarry(0)
result => stage2a3(15 downto 0),
cout => stage2_internalCarry(0)
);
--Adder 3, high adder
a3high : adder
223,11 → 223,11
substractor_selector => "NO" --No Just Add.
)
port map (
a => s2a0(31 downto 16),
b => s2p2(31 downto 16),
a => stage2a0(31 downto 16),
b => stage2p2(31 downto 16),
s => '0',
ci => s2_internalCarry(0),
result => s2a3(31 downto 16),
ci => stage2_internalCarry(0),
result => stage2a3(31 downto 16),
cout => open
);
--Adder 4, low adder
238,12 → 238,12
substractor_selector => "NO" --No Just Add.
)
port map (
a => s2p3(15 downto 0),
b => s2a2(15 downto 0),
a => stage2p3(15 downto 0),
b => stage2a2(15 downto 0),
s => '0',
ci => '0',
result => s2a4(15 downto 0),
cout => s2_internalCarry(1)
result => stage2a4(15 downto 0),
cout => stage2_internalCarry(1)
);
--Adder 4, high adder
a4high : adder
253,69 → 253,84
substractor_selector => "NO" --No Just Add.
)
port map (
a => s2p3(31 downto 16),
b => s2a2(31 downto 16),
a => stage2p3(31 downto 16),
b => stage2a2(31 downto 16),
s => '0',
ci => s2_internalCarry(1),
result => s2a4(31 downto 16),
ci => stage2_internalCarry(1),
result => stage2a4(31 downto 16),
cout => open
);
-- Incoming from opcoder.vhd signals into pipeline's stage 0.
s0mf00 <= m0f0;
s0mf01 <= m0f1;
s0mf10 <= m1f0;
s0mf11 <= m1f1;
s0mf20 <= m2f0;
s0mf21 <= m2f1;
s0mf30 <= m3f0;
s0mf31 <= m3f1;
s0mf40 <= m4f0;
s0mf41 <= m4f1;
s0mf50 <= m5f0;
s0mf51 <= m5f1;
stage0mf00 <= m0f0;
stage0mf01 <= m0f1;
stage0mf10 <= m1f0;
stage0mf11 <= m1f1;
stage0mf20 <= m2f0;
stage0mf21 <= m2f1;
stage0mf30 <= m3f0;
stage0mf31 <= m3f1;
stage0mf40 <= m4f0;
stage0mf41 <= m4f1;
stage0mf50 <= m5f0;
stage0mf51 <= m5f1;
-- Signal sequencing: as the multipliers use registered output and registered input is not necessary to write the sequence of stage 0 signals to stage 1 signals.
-- so the simplistic path is taken: simply connect stage 0 to stage 1 lines. However this would not apply for the opcode signal
s1p0 <= s0p0;
s1p1 <= s0p1;
s1p2 <= s0p2;
s1p3 <= s0p3;
s1p4 <= s0p4;
s1p5 <= s0p5;
stage1p0 <= stage0p0;
stage1p1 <= stage0p1;
stage1p2 <= stage0p2;
stage1p3 <= stage0p3;
stage1p4 <= stage0p4;
stage1p5 <= stage0p5;
--Outcoming to the rest of the system (by the time i wrote this i dont know where this leads to... jeje)
cpx <= s1a0;
cpy <= s1a1;
cpz <= s1a2;
dp0 <= s2a3;
dp1 <= s2a4;
cpx <= stage1a0;
cpy <= stage1a1;
cpz <= stage1a2;
dp0 <= stage2a3;
dp1 <= stage2a4;
-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
uf_seq: process (clk,rst)
uf_seq: process (clk,rst,opcode)
begin
if rst=rstMasterValue then
s0opcode <= '0';
s1opcode <= '0';
stage0opcode <= '0';
stage1opcode <= '0';
s2a2 <= (others => '0');
s2p3 <= (others => '0');
s2p2 <= (others => '0');
s2a0 <= (others => '0');
stage2a2 <= (others => '0');
stage2p3 <= (others => '0');
stage2p2 <= (others => '0');
stage2a0 <= (others => '0');
elsif clk'event and clk = '1' then
s2a2 <= s1a2;
s2p3 <= s1p3;
s2p2 <= s1p2;
s2a0 <= s1a0;
stage2a2 <= stage1a2;
stage2p3 <= stage1p3;
stage2p2 <= stage1p2;
stage2a0 <= stage1a0;
-- Opcode control sequence
s0opcode <= opcode;
s1opcode <= s0opcode;
stage0opcode <= opcode;
stage1opcode <= stage0opcode;
end if;
end process uf_seq;
uf_seq2: process (clk,rst,stage0opcode)
begin
if rst=rstMasterValue then
elsif clk'event and clk='1' then
end if;
end process uf_seq2;
end uf_arch;

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