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Rev 21 → Rev 22

/adder.vhd
1,21 → 1,41
--! @file adder.vhd
--! @brief Sumador parametrizable.
 
 
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
library ieee;
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
use work.arithpack.all;
 
--! Sumador parametrizable.
 
 
 
--! \n\n
--! <table>
 
 
 
entity adder is
generic (
w : integer := 9;
carry_logic : string := "CLA";
substractor_selector : string := "YES"
w : integer := 9; --! Ancho de los sumandos
 
 
);
 
port (
a,b : in std_logic_vector(w-1 downto 0);
s,ci : in std_logic;
result : out std_logic_vector(w-1 downto 0);
cout : out std_logic
a,b : in std_logic_vector(w-1 downto 0); --! Sumandos
s : in std_logic; --! Selector Suma / Resta
ci : in std_logic; --! Datos Carry In.
result : out std_logic_vector(w-1 downto 0);--! Resultado de la suma.
cout : out std_logic --! Carry out (Overflow).
);
end adder;
--! Arquitectura del sumador parametrizable.
 
 
 
architecture adder_arch of adder is
 
58,7 → 78,8
 
-- Conditional Instantiation / RCA/CLA Logical Blocks Generation --
rca_logic_block_instancing: -- Ripple Carry Adder
if carry_logic="RCA" generate
if carry_logic="RCA" generate
 
rca_x: rca_logic_block
generic map (w=>w)
port map (
71,6 → 92,7
cla_logic_block_instancing: -- Carry Lookahead Adder
if carry_logic="CLA" generate
 
cla_x: cla_logic_block
generic map (w=>w)
port map (
80,18 → 102,7
c=>sCarry
);
end generate cla_logic_block_instancing;
 
 
 
 
 
end adder_arch;
 
/raytrac.vhd
1,6 → 1,7
------------------------------------------------
--! @file
--! @brief Entidad top del Rt Engine \n Rt Engine's top hierarchy.
 
--------------------------------------------------
 
 
/arithpack.vhd
18,7 → 18,9
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.library ieee;
 
 
 
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
library ieee;
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
 
 
/cla_logic_block.vhd
1,5 → 1,8
 
-- RAYTRAC
-- Author Julian Andres Guarin
--! @file cla_logic_block.vhd
--! @author Julian Andres Guarin
 
-- cla_logic_block.vhd
-- This file is part of raytrac.
--
18,30 → 21,43
 
-- Check out arithpack.vhd to understand in general terms what this file describes,
-- or checkout this file to check in detailed way what this file intends to.
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
library ieee;
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
 
 
 
entity cla_logic_block is
generic (
w : integer := 4 -- Carry Look Ahead Block Default Size
 
);
 
port (
p,g : in std_logic_vector(w-1 downto 0); -- Propagation and Generation Inputs
cin : in std_logic; -- Carry In input
 
 
c : out std_logic_vector(w downto 1) -- Generated Carry Out outputs
c : out std_logic_vector(w downto 1) --! Carry Out.
);
end cla_logic_block;
 
 
--! Arquitectura del bloque Carry Look Ahead.
 
 
 
--! La siguiente tabla describe el funcionamiento de este circuito.
 
architecture cla_logic_block_arch of cla_logic_block is
 
 
begin
 
 
 
claProc: -- claProc instancia funciones combinatorias en las variables iCarry,
-- pero notese que los valores de iCarry(i) no dependen jamas de iCarry(i-1) a diferencia de rcaProc
-- pero notese que los valores de iCarry(i) no dependen jamas de iCarry(i-1) a diferencia de rcaProc.
process(p,g,cin)
 
variable i,j,k : integer range 0 to w; -- Variables de control de loop
/uf.vhd
1,3 → 1,6
--! @file raytrac.vhd
 
 
-- RAYTRAC
-- Author Julian Andres Guarin
-- uf.vhd
16,16 → 19,28
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
 
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
library ieee;
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
use work.arithpack.all;
 
 
 
 
 
 
 
--! \n\n
 
 
entity uf is
port (
opcode : in std_logic;
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);
cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0);
clk,rst : in std_logic
 
 
 
clk,rst : in std_logic --! Las entradas de control usuales.
);
end uf;
 
33,30 → 48,29
 
-- Stage 0 signals
signal stage0mf00,stage0mf01,stage0mf10,stage0mf11,stage0mf20,stage0mf21,stage0mf30,stage0mf31,stage0mf40,stage0mf41,stage0mf50,stage0mf51 : std_logic_vector(17 downto 0);
signal stage0p0,stage0p1, stage0p2, stage0p3, stage0p4, stage0p5 : std_logic_vector(31 downto 0);
signal stage0opcode : std_logic;
 
 
 
--Stage 1 signals
signal stage1p0, stage1p1, stage1p2, stage1p3, stage1p4, stage1p5 : std_logic_vector (31 downto 0);
signal stage1a0, stage1a1, stage1a2 : std_logic_vector (31 downto 0);
signal stage1opcode : std_logic;
 
 
 
-- Some support signals
signal stage1_internalCarry : std_logic_vector(2 downto 0);
signal stage2_internalCarry : std_logic_vector(1 downto 0);
 
 
--Stage 2 signals
--Stage 2 signals
 
signal stage2a0, stage2a2, stage2a3, stage2a4, stage2p2, stage2p3 : std_logic_vector (31 downto 0);
begin
 
-- Multiplicator Instantiation (StAgE 0)
--! Multiplicador 0
m0 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
65,6 → 79,8
datab => stage0mf01,
result => stage0p0
);
--! Multiplicador 1
m1 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
73,6 → 89,8
datab => stage0mf11,
result => stage0p1
);
--! Multiplicador 2
m2 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
81,6 → 99,8
datab => stage0mf21,
result => stage0p2
);
--! Multiplicador 3
m3 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
89,6 → 109,8
datab => stage0mf31,
result => stage0p3
);
--! Multiplicador 4
m4 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
97,6 → 119,8
datab => stage0mf41,
result => stage0p4
);
--! Multiplicador 5
m5 : r_a18_b18_smul_c32_r
port map (
aclr => rst,
108,11 → 132,11
-- Adder Instantiation (sTaGe 1)
--Adder 0, low adder
--! Adder 0, 16 bit carry lookahead low adder.
a0low : adder
generic map (
16,"CLA","YES" --Carry Look Ahead Logic (More Gates Used, But Less Time)
--Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
16,"CLA","YES" -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p0(15 downto 0),
122,12 → 146,12
result => stage1a0(15 downto 0),
cout => stage1_internalCarry(0)
);
--Adder 0, high adder
--Adder 0, 16 bit carry lookahead high adder.
a0high : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p0(31 downto 16),
137,12 → 161,12
result => stage1a0(31 downto 16),
cout => open
);
--Adder 1, low adder
--! Adder 1, 16 bit carry lookahead low adder.
a1low : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p2(15 downto 0),
152,12 → 176,12
result => stage1a1(15 downto 0),
cout => stage1_internalCarry(1)
);
--Adder 1, high adder
--! Adder 1, 16 bit carry lookahead high adder.
a1high : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p2(31 downto 16),
167,12 → 191,12
result => stage1a1(31 downto 16),
cout => open
);
--Adder 2, low adder
--! Adder 2, 16 bit carry lookahead low adder.
a2low : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p4(15 downto 0),
182,12 → 206,12
result => stage1a2(15 downto 0),
cout => stage1_internalCarry(2)
);
--Adder 2, high adder
--! Adder 2, 16 bit carry lookahead high adder.
a2high : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p4(31 downto 16),
200,12 → 224,12
-- Adder Instantiation (Stage 2)
--Adder 3, low adder
--! Adder 3, 16 bit carry lookahead low adder.
a3low : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" --No Just Add.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" -- No Just Add.
)
port map (
a => stage2a0(15 downto 0),
215,12 → 239,12
result => stage2a3(15 downto 0),
cout => stage2_internalCarry(0)
);
--Adder 3, high adder
--Adder 3, 16 bit carry lookahead high adder.
a3high : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" --No Just Add.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" -- No Just Add.
)
port map (
a => stage2a0(31 downto 16),
230,12 → 254,12
result => stage2a3(31 downto 16),
cout => open
);
--Adder 4, low adder
--! Adder 4, 16 bit carry lookahead low adder.
a4low : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" --No Just Add.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" -- No Just Add.
)
port map (
a => stage2p3(15 downto 0),
245,12 → 269,12
result => stage2a4(15 downto 0),
cout => stage2_internalCarry(1)
);
--Adder 4, high adder
--! Adder 4, 16 bit carry lookahead high adder.
a4high : adder
generic map (
w => 16,
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" --No Just Add.
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" -- No Just Add.
)
port map (
a => stage2p3(31 downto 16),
293,7 → 317,10
dp1 <= stage2a4;
-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
uf_seq: process (clk,rst,opcode)
--! Este proceso describe la manera en que se organizan las etapas de pipe.
 
uf_seq: process (clk,rst)
begin
if rst=rstMasterValue then
318,18 → 345,6
end if;
end process uf_seq;
uf_seq2: process (clk,rst,stage0opcode)
begin
if rst=rstMasterValue then
elsif clk'event and clk='1' then
end if;
end process uf_seq2;
/opcoder.vhd
1,5 → 1,6
--! @file opcoder.vhd
--! @brief Operation decoder. \n Decodificador de operacion.
--! @brief Decodificador de operacion.
 
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
18,10 → 19,11
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
--! Libreria ieee. 'n Good oldie IEEE.
 
 
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
library ieee;
 
--! Paquete de manejo de logica estandard. \n Standard logic managment package.
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
 
--! La entidad opcoder es la etapa combinatoria que decodifica la operacion que se va a realizar.
37,19 → 39,23
);
end entity;
 
--! Arquitectura del decodificador de operaci&oacute;n.
 
--! El bloque de arquitectura del decodificador es simplemente una cascada de multiplexores. La selecci&oacute;n se hace en funci&oacute;n de las se&ntilde;ales appcode y addcode\n
--! La siguiente tabla describe el comportamiento de los multiplexores:\n
--! \n\n
 
--!
--! <table>
--! <tr><th></th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th>&nbsp;</th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th>&nbsp;</th></tr> <tr><td>m0</td><td>0</td><td>0</td><td>Ax</td><td>Bx</td><td>&nbsp;</td><td>0</td><td>0</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>0</td><td>1</td><td>Ax</td><td>Bx</td><td>&nbsp;</td><td>0</td><td>1</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>0</td><td>Ay</td><td>Bz</td><td>&nbsp;</td><td>1</td><td>0</td><td>Ax</td><td>Bz</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>1</td><td>Cy</td><td>Dz</td><td>&nbsp;</td><td>1</td><td>1</td><td>Cx</td><td>Dz</td><td>m3</td></tr> <tr><td>m1</td><td>0</td><td>0</td><td>Ay</td><td>By</td><td>&nbsp;</td><td>0</td><td>0</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>0</td><td>1</td><td>Ay</td><td>By</td><td>&nbsp;</td><td>0</td><td>1</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>0</td><td>Az</td><td>By</td><td>&nbsp;</td><td>1</td><td>0</td><td>Ax</td><td>By</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>1</td><td>Cz</td><td>Dy</td><td>&nbsp;</td><td>1</td><td>1</td><td>Cx</td><td>Dy</td><td>m4</td></tr> <tr><td>m2</td><td>0</td><td>0</td><td>Az</td><td>Bz</td><td>&nbsp;</td><td>0</td><td>0</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>0</td><td>1</td><td>Az</td><td>Bz</td><td>&nbsp;</td><td>0</td><td>1</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>0</td><td>Az</td><td>Bx</td><td>&nbsp;</td><td>1</td><td>0</td><td>Ay</td><td>Bx</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>1</td><td>Cz</td><td>Dx</td><td>&nbsp;</td><td>1</td><td>1</td><td>Cy</td><td>Dx</td><td>m5</td></tr></table>
--! \n\n
 
 
 
architecture opcoder_arch of opcoder is
begin
--! Proceso que describe las 2 etapas de multiplexores.
 
 
procOpcoder:
process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,opcode,addcode)
variable scoder : std_logic_vector (1 downto 0);
/rca_logic_block.vhd
1,25 → 1,62
--! @file rca_logic_block.vhd
--! @author Julian Andres Guarin
 
-- rca_logic_block.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.library ieee;
 
-- Check out arithpack.vhd to understand in general terms what this file describes,
-- or checkout this file to check in detailed way what this file intends to.
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
library ieee;
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
 
 
--! Entidad generadora del Bloque de Ripple Carry Adder.
 
 
 
entity rca_logic_block is
generic (
w : integer := 8
 
);
port (
p,g: in std_logic_vector(w-1 downto 0);
cin : in std_logic;
 
 
c : out std_logic_vector(w downto 1)
 
);
end rca_logic_block;
 
 
--! Arquitectura del bloque Ripple Carry Adder.
 
 
 
 
 
architecture rca_logic_block_arch of rca_logic_block is
 
 
begin
--! El siguiente proceso instancia funciones combinatorias para CADA UNO de los valores de Couti a calcular. En TODO momemnto se utiliza el resultado de los Cout antrerioes a Couti, optimizando en uso de recursos.
 
 
rcaProc: -- rcaProc instancia funciones combinatorias en sCarry(i) haciendo uso de los resultados intermedios obtenidos
-- en sCarry(i-1), por lo que se crea un delay path en el calculo del Cout del circuito
process (p,g,cin)

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