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Rev 26 → Rev 27

/adder.vhd
1,60 → 1,62
--! @file adder.vhd
--! @brief Sumador parametrizable.
 
 
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
-- RAYTRAC
-- Author Julian Andres Guarin
-- adder.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
library ieee;
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
 
use work.arithpack.all;
 
--! Sumador parametrizable.
 
 
 
--! \n\n
--! <table>
 
 
 
entity adder is
generic (
w : integer := 9; --! Ancho de los sumandos
 
 
width : integer := 4;
carry_logic : string := "CLA";
substractor_selector : string := "YES"
);
 
port (
a,b : in std_logic_vector(w-1 downto 0); --! Sumandos
s : in std_logic; --! Selector Suma / Resta
ci : in std_logic; --! Datos Carry In.
result : out std_logic_vector(w-1 downto 0);--! Resultado de la suma.
cout : out std_logic --! Carry out (Overflow).
a,b : in std_logic_vector(width-1 downto 0);
s,ci : in std_logic;
result : out std_logic_vector(width-1 downto 0);
cout : out std_logic
);
end adder;
--! Arquitectura del sumador parametrizable.
 
 
 
architecture adder_arch of adder is
 
signal sa,p,g: std_logic_vector(w-1 downto 0);
signal sCarry: std_logic_vector(w downto 1);
signal sa,p,g: std_logic_vector(width-1 downto 0);
signal sCarry: std_logic_vector(width downto 1);
 
begin
begin
 
 
-- Usual Structural Model / wether or not CLA/RCA is used and wether or not add/sub selector is used, this port is always instanced --
result(0)<= a(0) xor b(0) xor ci;
wide_adder:
if (w>1) generate
if (width>1) generate
wide_adder_generate_loop:
for i in 1 to w-1 generate
for i in 1 to width-1 generate
result(i) <= a(i) xor b(i) xor sCarry(i);
end generate wide_adder_generate_loop;
end generate wide_adder;
cout <= sCarry(w);
cout <= sCarry(width);
g<= sa and b;
p<= sa or b;
64,7 → 66,7
adder_sub_logic : -- adder substractor logic
if substractor_selector = "YES" generate
a_xor_s:
for i in 0 to w-1 generate
for i in 0 to width-1 generate
sa(i) <= a(i) xor s;
end generate a_xor_s;
end generate adder_sub_Logic;
78,10 → 80,9
 
-- Conditional Instantiation / RCA/CLA Logical Blocks Generation --
rca_logic_block_instancing: -- Ripple Carry Adder
if carry_logic="RCA" generate
 
if carry_logic="RCA" generate
rca_x: rca_logic_block
generic map (w=>w)
generic map (width=>width)
port map (
p=>p,
g=>g,
92,9 → 93,8
cla_logic_block_instancing: -- Carry Lookahead Adder
if carry_logic="CLA" generate
 
cla_x: cla_logic_block
generic map (w=>w)
generic map (width=>width)
port map (
p=>p,
g=>g,
102,7 → 102,18
c=>sCarry
);
end generate cla_logic_block_instancing;
 
 
 
 
 
end adder_arch;
 
/raytrac.vhd
28,6 → 28,8
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
 
 
 
--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
use work.arithpack.all;
 
83,6 → 85,7
 
entity raytrac is
generic (
registered : string := "YES" --! Este parametro, por defecto "YES", indica si se registran o cargan en registros los vectores A,B,C,D y los codigos de operacion opcode y addcode en vez de ser conectados directamente al circuito combinatorio. \n This parameter, by default "YES", indicates if vectors A,B,C,D and operation code inputs opcode are to be loaded into a register at the beginning of the pipe rather than just connecting them to the operations decoder (opcoder).
);
port (
/arithpack.vhd
37,6 → 37,9
 
 
component uf
generic (
use_std_logic_signed : string := "NO"
);
port (
opcode : in std_logic;
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);
80,21 → 83,21
 
component cla_logic_block
generic ( w: integer:=4);
generic ( width: integer:=4);
port (
p,g:in std_logic_vector(w-1 downto 0);
p,g:in std_logic_vector(width-1 downto 0);
cin:in std_logic;
c:out std_logic_vector(w downto 1)
c:out std_logic_vector(width downto 1)
);
end component;
 
component rca_logic_block
generic ( w : integer := 4);
generic ( width : integer := 4);
port (
p,g: in std_logic_vector(w-1 downto 0);
p,g: in std_logic_vector(width-1 downto 0);
cin: in std_logic;
c: out std_logic_vector(w downto 1)
c: out std_logic_vector(width downto 1)
);
end component;
101,14 → 104,14
 
component adder
generic (
w : integer := 4;
width : integer := 4;
carry_logic : string := "CLA";
substractor_selector : string := "YES"
);
port (
a,b : in std_logic_vector (w-1 downto 0);
a,b : in std_logic_vector (width-1 downto 0);
s,ci : in std_logic;
result : out std_logic_vector (w-1 downto 0);
result : out std_logic_vector (width-1 downto 0);
cout : out std_logic
);
end component;
/cla_logic_block.vhd
32,14 → 32,14
 
entity cla_logic_block is
generic (
 
 
);
 
port (
 
 
 
c : out std_logic_vector(w downto 1) --! Carry Out.
c : out std_logic_vector(width downto 1) --! Carry Out.
);
end cla_logic_block;
 
60,15 → 60,15
-- pero notese que los valores de iCarry(i) no dependen jamas de iCarry(i-1) a diferencia de rcaProc.
process(p,g,cin)
 
variable i,j,k : integer range 0 to w; -- Variables de control de loop
variable iCarry: std_logic_vector(w downto 1); -- Carry Interno
variable iResults: std_logic_vector(((w+w**2)/2)-1 downto 0); -- Resultados intermedios
variable i,j,k : integer range 0 to width; -- Variables de control de loop
variable iCarry: std_logic_vector(width downto 1); -- Carry Interno
variable iResults: std_logic_vector(((width+width**2)/2)-1 downto 0); -- Resultados intermedios
variable index: integer;
begin
 
iCarry(w downto 1) := g(w-1 downto 0);
iCarry(width downto 1) := g(width-1 downto 0);
index := 0;
for j in 0 to w-1 loop
for j in 0 to width-1 loop
for i in 1 to j+1 loop
iResults(index) := '1';
for k in j-i+1 to j loop
/uf.vhd
23,6 → 23,10
library ieee;
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
 
 
use ieee.std_logic_signed.all;
 
--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
use work.arithpack.all;
 
35,7 → 39,10
--! \n\n
 
 
entity uf is
entity uf is
generic (
use_std_logic_signed : string := "YES"
);
port (
 
 
130,161 → 137,84
result => stage0p5
);
-- Adder Instantiation (sTaGe 1)
--! Adder 0, 16 bit carry lookahead low adder.
a0low : adder
generic map (
16,"CLA","YES" -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p0(15 downto 0),
b => stage1p1(15 downto 0),
s => stage1opcode,
ci => '0',
result => stage1a0(15 downto 0),
cout => stage1_internalCarry(0)
);
--Adder 0, 16 bit carry lookahead high adder.
a0high : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p0(31 downto 16),
b => stage1p1(31 downto 16),
s => stage1opcode,
ci => stage1_internalCarry(0),
result => stage1a0(31 downto 16),
cout => open
);
--! Adder 1, 16 bit carry lookahead low adder.
a1low : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p2(15 downto 0),
b => stage1p3(15 downto 0),
s => stage1opcode,
ci => '0',
result => stage1a1(15 downto 0),
cout => stage1_internalCarry(1)
);
--! Adder 1, 16 bit carry lookahead high adder.
a1high : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p2(31 downto 16),
b => stage1p3(31 downto 16),
s => stage1opcode,
ci => stage1_internalCarry(1),
result => stage1a1(31 downto 16),
cout => open
);
--! Adder 2, 16 bit carry lookahead low adder.
a2low : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p4(15 downto 0),
b => stage1p5(15 downto 0),
s => stage1opcode,
ci => '0',
result => stage1a2(15 downto 0),
cout => stage1_internalCarry(2)
);
--! Adder 2, 16 bit carry lookahead high adder.
a2high : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
)
port map (
a => stage1p4(31 downto 16),
b => stage1p5(31 downto 16),
s => stage1opcode,
ci => stage1_internalCarry(2),
result => stage1a2(31 downto 16),
cout => open
);
-- Adder Instantiation (Stage 2)
--! Adder 3, 16 bit carry lookahead low adder.
a3low : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" -- No Just Add.
)
port map (
a => stage2a0(15 downto 0),
b => stage2p2(15 downto 0),
s => '0',
ci => '0',
result => stage2a3(15 downto 0),
cout => stage2_internalCarry(0)
);
--Adder 3, 16 bit carry lookahead high adder.
a3high : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" -- No Just Add.
)
port map (
a => stage2a0(31 downto 16),
b => stage2p2(31 downto 16),
s => '0',
ci => stage2_internalCarry(0),
result => stage2a3(31 downto 16),
cout => open
);
--! Adder 4, 16 bit carry lookahead low adder.
a4low : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" -- No Just Add.
)
port map (
a => stage2p3(15 downto 0),
b => stage2a2(15 downto 0),
s => '0',
ci => '0',
result => stage2a4(15 downto 0),
cout => stage2_internalCarry(1)
);
--! Adder 4, 16 bit carry lookahead high adder.
a4high : adder
generic map (
w => 16,
carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
substractor_selector => "NO" -- No Just Add.
)
port map (
a => stage2p3(31 downto 16),
b => stage2a2(31 downto 16),
s => '0',
ci => stage2_internalCarry(1),
result => stage2a4(31 downto 16),
cout => open
);
useIeee:
if use_std_logic_signed="YES" generate
-- Adder Instantiation (sTaGe 1)
stage1adderProc:
process (stage1p0,stage1p1,stage1p2,stage1p3,stage1p4,stage1p5,stage1opcode)
begin
case (stage1opcode) is
when '1' => -- Cross Product
stage1a0 <= stage1p0-stage1p1;
stage1a2 <= stage1p4-stage1p5;
when others => -- Dot Product
stage1a0 <= stage1p0+stage1p1;
stage1a2 <= stage1p4+stage1p5;
end case;
end process stage1adderProc;
stage1a1 <= stage1p2-stage1p3; -- This is always going to be a substraction
-- Adder Instantiation (Stage 2)
stage2a3 <= stage2a0+stage2p2;
stage2a4 <= stage2p3+stage2a2;
end generate useIeee;
dontUseIeee:
if use_std_logic_signed="NO" generate
--! Adder 0, 16 bit carry lookahead low adder.
a0low : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stage1opcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
--Adder 0, 16 bit carry lookahead high adder.
a0high : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stage1opcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
--! Adder 1, 16 bit carry lookahead low adder.
a1low : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p2(15 downto 0),stage1p3(15 downto 0),'1','0',stage1a1(15 downto 0),stage1_internalCarry(1));
--! Adder 1, 16 bit carry lookahead high adder.
a1high : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p2(31 downto 16),stage1p3(31 downto 16),'1',stage1_internalCarry(1),stage1a1(31 downto 16),open);
--! Adder 2, 16 bit carry lookahead low adder.
a2low : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stage1opcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
--! Adder 2, 16 bit carry lookahead high adder.
a2high : adder
generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stage1opcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
-- Adder Instantiation (Stage 2)
--! Adder 3, 16 bit carry lookahead low adder.
a3low : adder
generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2a0(15 downto 0),stage2p2(15 downto 0),'0','0',stage2a3(15 downto 0),stage2_internalCarry(0));
--Adder 3, 16 bit carry lookahead high adder.
a3high : adder
generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2a0(31 downto 16),stage2p2(31 downto 16),'0',stage2_internalCarry(0),stage2a3(31 downto 16),open);
--! Adder 4, 16 bit carry lookahead low adder.
a4low : adder
generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2p3(15 downto 0),stage2a2(15 downto 0),'0','0',stage2a4(15 downto 0),stage2_internalCarry(1));
--! Adder 4, 16 bit carry lookahead high adder.
a4high : adder
generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2p3(31 downto 16),stage2a2(31 downto 16),'0',stage2_internalCarry(1),stage2a4(31 downto 16),open);
end generate dontUseIeee;
-- Incoming from opcoder.vhd signals into pipeline's stage 0.
stage0mf00 <= m0f0;
stage0mf01 <= m0f1;
/opcoder.vhd
35,7 → 35,7
entity opcoder is
generic (
width : integer := 18;
structuralDescription : string:= "NO"
structuralDescription : string:= "YES"
);
port (
Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (width-1 downto 0);
58,7 → 58,7
 
architecture opcoder_arch of opcoder is
variable aycy,bzdz,azcz,bydy,bxdx,axcx: std_logic_vector(width-1 downto 0);
signal aycy,bzdz,azcz,bydy,bxdx,axcx: std_logic_vector(width-1 downto 0);
begin
--! Proceso que describe las 2 etapas de multiplexores.
122,26 → 122,26
end generate originalMuxGen;
fastMuxGen:
if structuralDescription="YES" generate
mux0 : fastmux port map (ay,cy,addcode,aycy);
mux1 : fastmux port map (bz,dz,addcode,bzdz);
mux2 : fastmux port map (az,cz,addcode,azcz);
mux3 : fastmux port map (by,dy,addcode,bydy);
mux4 : fastmux port map (bx,dx,addcode,bxdx);
mux5 : fastmux port map (ax,cx,addcode,axcx);
mux0 : fastmux generic map (width) port map (ay,cy,addcode,aycy);
mux1 : fastmux generic map (width) port map (bz,dz,addcode,bzdz);
mux2 : fastmux generic map (width) port map (az,cz,addcode,azcz);
mux3 : fastmux generic map (width) port map (by,dy,addcode,bydy);
mux4 : fastmux generic map (width) port map (bx,dx,addcode,bxdx);
mux5 : fastmux generic map (width) port map (ax,cx,addcode,axcx);
-- Segunda etapa de multiplexores
muxa : fastmux port map (ax,aycy,opcode,m0f0);
muxb : fastmux port map (bx,bzdz,opcode,m0f1);
muxc : fastmux port map (ay,azcz,opcode,m1f0);
muxd : fastmux port map (by,bydy,opcode,m1f1);
muxe : fastmux port map (az,azcz,opcode,m2f0);
muxf : fastmux port map (bz,bxdx,opcode,m2f1);
muxg : fastmux port map (cx,axcx,opcode,m3f0);
muxh : fastmux port map (dx,bzdz,opcode,m3f1);
muxi : fastmux port map (cy,axcx,opcode,m4f0);
muxj : fastmux port map (dy,bydy,opcode,m4f1);
muxk : fastmux port map (cz,aycy,opcode,m5f0);
muxl : fastmux port map (dz,bxdx,opcode,m5f1);
muxa : fastmux generic map (width) port map (ax,aycy,opcode,m0f0);
muxb : fastmux generic map (width) port map (bx,bzdz,opcode,m0f1);
muxc : fastmux generic map (width) port map (ay,azcz,opcode,m1f0);
muxd : fastmux generic map (width) port map (by,bydy,opcode,m1f1);
muxe : fastmux generic map (width) port map (az,azcz,opcode,m2f0);
muxf : fastmux generic map (width) port map (bz,bxdx,opcode,m2f1);
muxg : fastmux generic map (width) port map (cx,axcx,opcode,m3f0);
muxh : fastmux generic map (width) port map (dx,bzdz,opcode,m3f1);
muxi : fastmux generic map (width) port map (cy,axcx,opcode,m4f0);
muxj : fastmux generic map (width) port map (dy,bydy,opcode,m4f1);
muxk : fastmux generic map (width) port map (cz,aycy,opcode,m5f0);
muxl : fastmux generic map (width) port map (dz,bxdx,opcode,m5f1);
end generate fastMuxGen;
/rca_logic_block.vhd
31,13 → 31,13
 
entity rca_logic_block is
generic (
 
 
);
port (
 
 
 
 
 
);
end rca_logic_block;
 
60,14 → 60,14
rcaProc: -- rcaProc instancia funciones combinatorias en sCarry(i) haciendo uso de los resultados intermedios obtenidos
-- en sCarry(i-1), por lo que se crea un delay path en el calculo del Cout del circuito
process (p,g,cin)
variable i: integer range 0 to 2*w;
variable sCarry: std_logic_vector(w downto 1);
variable i: integer range 0 to 2*width;
variable sCarry: std_logic_vector(width downto 1);
begin
sCarry(w downto 1) := g(w-1 downto 0);
sCarry(width downto 1) := g(width-1 downto 0);
sCarry(1) := sCarry(1) or (p(0) and cin);
for i in 1 to w-1 loop
for i in 1 to width-1 loop
sCarry(i+1) := sCarry(i+1) or (p(i) and sCarry(i));
end loop;
 

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