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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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  • This comparison shows the changes necessary to convert path 
    /raytrac/trunk
    from Rev 41 to Rev 42
    ↔ Reverse comparison
  •

Rev 41 → Rev 42

/arithpack.vhd
35,6 → 35,13
 
constant rstMasterValue : std_logic := '1';
--! Generacion de Clock y de Reset.
component clock_gen
generic (tclk : time := 20 ns);
port (clk,rst : out std_logic);
end component;
--! Memoria Rom Para Realizar TestBench
component tbRom
generic (
/clock_gen.vhd
29,7 → 29,6
 
architecture clock_gen_arch of clock_gen is
 
constant
 
begin
resetproc: process
38,9 → 37,22
wait for 50 ns;
rst<= '0';
wait;
end process;
end process resetproc;
clockproc: process
begin
clk<='1';
clock_loop:
loop
wait for tclk/2;
clk<='0';
wait for tclk/2;
clk <= '1';
end loop clock_loop;
end process clockproc;
end clock_gen_arch;
 
 
/rtRam.vhd
9,16 → 9,16
entity rtRam is
port
(
aclr : in STD_LOGIC := '0';
address_a : in STD_LOGIC_VECTOR (4 downto 0);
address_b : in STD_LOGIC_VECTOR (4 downto 0);
clock : in STD_LOGIC := '1';
data_a : in STD_LOGIC_VECTOR (17 downto 0);
data_b : in STD_LOGIC_VECTOR (17 downto 0);
wren_a : in STD_LOGIC := '0';
wren_b : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR (17 downto 0);
q_b : out STD_LOGIC_VECTOR (17 downto 0)
aclr : in std_logic := '0';
address_a : in std_logic_vector (6 downto 0);
address_b : in std_logic_vector (6 downto 0);
clock : in std_logic := '1';
data_a : in std_logic_vector (17 downto 0);
data_b : in std_logic_vector (17 downto 0);
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector (17 downto 0);
q_b : out std_logic_vector (17 downto 0)
);
end rtRam;
 
25,8 → 25,8
 
architecture rtRam_arch of rtRam is
 
signal sub_wire0 : STD_LOGIC_VECTOR (17 downto 0);
signal sub_wire1 : STD_LOGIC_VECTOR (17 downto 0);
signal sub_wire0 : std_logic_vector (17 downto 0);
signal sub_wire1 : std_logic_vector (17 downto 0);
 
 
 
61,16 → 61,16
wrcontrol_wraddress_reg_b : STRING
);
port (
clock0 : in STD_LOGIC ;
wren_a : in STD_LOGIC ;
address_b : in STD_LOGIC_VECTOR (4 downto 0);
data_b : in STD_LOGIC_VECTOR (17 downto 0);
q_a : out STD_LOGIC_VECTOR (17 downto 0);
wren_b : in STD_LOGIC ;
aclr0 : in STD_LOGIC ;
address_a : in STD_LOGIC_VECTOR (4 downto 0);
data_a : in STD_LOGIC_VECTOR (17 downto 0);
q_b : out STD_LOGIC_VECTOR (17 downto 0)
clock0 : in std_logic ;
wren_a : in std_logic ;
address_b : in std_logic_vector (4 downto 0);
data_b : in std_logic_vector (17 downto 0);
q_a : out std_logic_vector (17 downto 0);
wren_b : in std_logic ;
aclr0 : in std_logic ;
address_a : in std_logic_vector (4 downto 0);
data_a : in std_logic_vector (17 downto 0);
q_b : out std_logic_vector (17 downto 0)
);
end component;
 
88,8 → 88,8
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 32,
numwords_b => 32,
numwords_a => 128,
numwords_b => 128,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
109,16 → 109,24
wrcontrol_wraddress_reg_b => "CLOCK0"
)
port map (
 
clock0 => clock,
aclr0 => aclr,
wren_a => wren_a,
wren_b => '0',
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
wren_b => wren_b,
aclr0 => aclr,
address_a => address_a,
data_a => data_a,
 
q_a => sub_wire0,
q_b => sub_wire1
);
 
 

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