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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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  • This comparison shows the changes necessary to convert path 
    /raytrac/trunk
    from Rev 42 to Rev 43
    ↔ Reverse comparison
  •

Rev 42 → Rev 43

/memMaker.c
105,7 → 105,7
ffactor=(factor&(1<<memparam.width))?(factor^(int)(pow(2,memparam.width+1)-1))+1:factor;
ffactor/=pow(2,memparam.dec);
memset(buff,0,1024);
sprintf(buff,"%c0%dx : %c0%dx -- FIXED => %x . %x (%d . %d) FLOAT %c%f\n",
sprintf(buff,"%c0%dx : %c0%dx; -- FIXED => %x . %x (%d . %d) FLOAT %c%f\n",
'%',
depthpfw,
'%',
121,7 → 121,7
 
}
void printmem(void){
fprintf (stdout,memparam.initialheader,memparam.depth,memparam.width);
fprintf (stdout,memparam.initialheader,memparam.depth,memparam.width+1);
generatenums();
fprintf (stdout,memparam.end);
 
/tb.vhd
1,70 → 1,186
------------------------------------------------
--! @file
--! @brief RayTrac TestBench
 
--------------------------------------------------
 
 
-- RAYTRAC
-- Author Julian Andres Guarin
-- tb.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
 
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
library altera_mf;
use altera_mf.all;
 
entity tb is
port
(
address : in STD_LOGIC_VECTOR (3 downto 0);
clock : in STD_LOGIC := '1';
q : out STD_LOGIC_VECTOR (17 downto 0)
);
end mema;
end tb;
 
 
ARCHITECTURE SYN OF mema IS
ARCHITECTURE tb_arch OF tb IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal qa : std_logic_vector (53 downto 0);
signal qb : std_logic_vector (53 downto 0);
signal qc : std_logic_vector (53 downto 0);
signal qd : std_logic_vector (53 downto 0);
signal clock: std_logic;
signal address: std_logic_vector (8 downto 0);
BEGIN
 
AX : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memax.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qa (17 downto 0)
);
 
AY : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memay.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qa (35 downto 18)
);
 
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
AZ : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memaz.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qa (53 downto 36)
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
BX : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\membx.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qb (17 downto 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(17 DOWNTO 0);
BY : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memby.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qb (35 downto 18)
);
 
altsyncram_component : altsyncram
BZ : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../../MinGW/msys/1.0/home/julian/code/memoryMaker/trunk/mema.mif",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\membz.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 16,
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 4,
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
71,10 → 187,152
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
q_a => qb (53 downto 36)
);
 
CX : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memcx.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qc (17 downto 0)
);
 
CY : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memcy.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qc (35 downto 18)
);
 
CZ : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memcz.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qc (53 downto 36)
);
DX : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memdx.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qd (17 downto 0)
);
 
END SYN;
DY : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memdy.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qd (35 downto 18)
);
 
DZ : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "c:\Mingw\msys\1.0\home\julian\code\testbench\binm\memdz.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => qd (53 downto 36)
);
 
END tb_arch;
 
/arithpack.vhd
1,6 → 1,6
--! @file arithpack.vhd
 
 
--! @author Julian Andres Guarin Reyes
--! @brief Este package contiene la descripcion de los parametros y los puertos de las entidades: uf, opcoder, multiplicador, sumador, cla_logic_block y rca_logic_block.
-- RAYTRAC
-- Author Julian Andres Guarin
-- arithpack.vhd
25,9 → 25,12
--! Paquete de definicion estandard de logica.
use ieee.std_logic_1164.all;
 
--! Biblioteca de definicion de memorias de altera
library altera_mf;
 
--! Paquete para manejar memorias internas tipo M9K
 
 
--! Package con las definiciones de constantes y entidades, que conformaran el Rt Engine. Tambien con algunas descripciones para realizar test bench.
 
--! En general el package cuenta con entidades para instanciar, multiplicadores, sumadores/restadores y un decodificador de operaciones.
package arithpack is
42,20 → 45,31
end component;
--! Memoria Rom Para Realizar TestBench
component tbRom
component altsyncram
generic (
tbRom_init_file : string := "X:/Tesis/Workspace/hw/rt_lib/arith/bin/mema.mif"
);
port
(
address : in std_logic_vector (3 downto 0);
addressstall_a : in std_logic;
clock : in std_logic;
q : out std_logic_vector (17 downto 0)
address_aclr_a : string;
clock_enable_input_a : string;
clock_enable_output_a : string;
init_file : string;
intended_device_family : string;
lpm_hint : string;
lpm_type : string;
numwords_a : natural;
operation_mode : string;
outdata_aclr_a : string;
outdata_reg_a : string;
ram_block_type : string;
widthad_a : natural;
width_a : natural;
width_byteena_a : natural
);
end component;
 
port (
clock0 : in std_logic ;
address_a : in std_logic_vector (8 downto 0);
q_a : out std_logic_vector (17 downto 0)
);
 
component uf
generic (
use_std_logic_signed : string := "NO";

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