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------------------------------------------------ |
--! @file tb.vhd |
--! @brief RayTrac TestBench |
|
-------------------------------------------------- |
|
|
-- RAYTRAC |
-- Author Julian Andres Guarin |
-- tb.vhd |
-- This file is part of raytrac. |
-- |
-- raytrac is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- raytrac is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with raytrac. If not, see <http://www.gnu.org/licenses/> |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use std.textio.all; |
use work.arithpack.all; |
|
|
entity tb is |
|
end tb; |
|
|
architecture tb_arch of tb is |
|
signal qa : std_logic_vector (53 downto 0); |
signal qb : std_logic_vector (53 downto 0); |
signal qc : std_logic_vector (53 downto 0); |
signal qd : std_logic_vector (53 downto 0); |
signal clock,rst,ena: std_logic; |
signal opcode,addcode:std_logic; |
signal dp0,dp1,cpx,cpy,cpz : std_logic_vector(31 downto 0); |
signal address: std_logic_vector (8 downto 0); |
|
begin |
--! Generador de clock. |
clk_inst: clock_gen |
port map (clock,rst); -- Instanciacion simple. |
|
--! Device Under Test |
dude: raytrac |
generic map ("YES") -- Entrada registrada, pues la ROM no tiene salida registrada. |
port map(qa,qb,qc,qd,opcode,addcode,clock,rst,ena,cpx,cpy,cpz,dp0,dp1); |
|
--! Descripcion del test: 512 x (2/clock) productos punto y 1024 x (1/clock) productos cruz. |
thetest: |
process (clock,rst) |
variable addressCounter : integer := 0; |
variable tbs : tbState; |
variable tline : line; |
file log : text open write_mode is "TRACE_proc_thetest"; |
begin |
|
if rst=rstMasterValue then |
addressCounter := 0; |
opcode <= '0'; |
addcode <= '1'; |
tbs := abcd; |
ena <= '1'; |
address <= (others => '0'); |
elsif clock'event and clock = '1' then |
-- Register States when clock went up ... |
write (tline,now); |
write (tline,string'(" ")); |
write (tline,to_bitvector(address)); |
write (tline,string'(" ")); |
writeline(log,tline); |
case tbs is |
when abcd => |
|
|
if address = X"000" then |
write(tline,now); |
write(tline,string'(" : Se fue esta vaina")); |
writeline(log,tline); |
tbs := axb; |
opcode <= '1'; |
addcode <= not(addcode); |
end if; |
address <= address + 1; |
|
when axb => |
tbs := cxd; |
addcode <= not(addcode); |
when cxd => |
address <= address + 1; |
addcode <= not(addcode); |
if address=X"000" then |
null; |
end if; |
when others => |
null; |
end case; |
|
end if; |
end process thetest; |
|
--! 512x18 rom con los componentes ax. |
AX : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memax.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qa (17 downto 0) |
); |
|
--! 512x18 rom con los componentes ay. |
AY : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memay.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qa (35 downto 18) |
); |
|
--! 512x18 rom con los componentes az. |
AZ : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memaz.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qa (53 downto 36) |
); |
|
--! 512x18 rom con los componentes bx. |
BX : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\membx.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qb (17 downto 0) |
); |
|
--! 512x18 rom con los componentes by. |
BY : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memby.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qb (35 downto 18) |
); |
|
--! 512x18 rom con los componentes bz. |
BZ : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\membz.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qb (53 downto 36) |
); |
|
--! 512x18 rom con los componentes cx. |
CX : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memcx.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qc (17 downto 0) |
); |
|
--! 512x18 rom con los componentes cy. |
CY : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memcy.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qc (35 downto 18) |
); |
|
--! 512x18 rom con los componentes cz. |
CZ : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memcz.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qc (53 downto 36) |
); |
|
--! 512x18 rom con los componentes dx. |
DX : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memdx.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qd (17 downto 0) |
); |
|
--! 512x18 rom con los componentes dy. |
DY : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memdy.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qd (35 downto 18) |
); |
|
--! 512x18 rom con los componentes dz. |
DZ : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memdz.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qd (53 downto 36) |
); |
|
end tb_arch; |
|
------------------------------------------------ |
--! @file tb.vhd |
--! @brief RayTrac TestBench |
|
-------------------------------------------------- |
|
|
-- RAYTRAC |
-- Author Julian Andres Guarin |
-- tb.vhd |
-- This file is part of raytrac. |
-- |
-- raytrac is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- raytrac is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with raytrac. If not, see <http://www.gnu.org/licenses/> |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
use std.textio.all; |
use work.arithpack.all; |
|
|
entity tb is |
|
end tb; |
|
|
architecture tb_arch of tb is |
|
signal qa : std_logic_vector (53 downto 0); |
signal qb : std_logic_vector (53 downto 0); |
signal qc : std_logic_vector (53 downto 0); |
signal qd : std_logic_vector (53 downto 0); |
signal clock,rst,ena: std_logic; |
signal opcode,addcode:std_logic; |
signal dp0,dp1,cpx,cpy,cpz : std_logic_vector(31 downto 0); |
signal address: std_logic_vector (8 downto 0); |
|
begin |
--! Generador de clock. |
clk_inst: clock_gen |
port map (clock,rst); -- Instanciacion simple. |
|
--! Device Under Test |
dude: raytrac |
generic map ("YES") -- Entrada registrada, pues la ROM no tiene salida registrada. |
port map(qa,qb,qc,qd,opcode,addcode,clock,rst,ena,cpx,cpy,cpz,dp0,dp1); |
|
--! Procedimiento para escribir los resultados del testbench |
sampleproc: process |
variable buff : line; |
file rombuff : text open write_mode is "TRACE_rom_content"; |
|
begin |
write(buff,string'("ROM memories test benching")); |
writeline(rombuff, buff); |
wait for 5 ns; |
wait until rst=not(rstMasterValue); |
wait until clock='1'; |
wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida. |
displayRom: |
loop |
write (buff,now,unit =>ns); |
write (buff,string'(" ")); |
hexwrite_0 (buff,address(7 downto 0)); |
write (buff,string'(" ")); |
hexwrite_0 (buff,qa(17 downto 0)); |
writeline(rombuff,buff); |
wait for tclk; |
end loop displayRom; |
|
end process sampleproc; |
|
|
--! Descripcion del test: 512 x (2/clock) productos punto y 1024 x (1/clock) productos cruz. |
thetest: |
process (clock,rst) |
variable addressCounter : integer := 0; |
variable tbs : tbState; |
begin |
|
if rst=rstMasterValue then |
addressCounter := 0; |
opcode <= '0'; |
addcode <= '1'; |
tbs := abcd; |
ena <= '1'; |
address <= (others => '0'); |
elsif clock'event and clock = '1' then |
|
case tbs is |
when abcd => |
if address = X"1FF" then |
tbs := axb; |
opcode <= '1'; |
addcode <= not(addcode); |
end if; |
address <= address + 1; |
|
when axb => |
tbs := cxd; |
addcode <= not(addcode); |
when cxd => |
address <= address + 1; |
addcode <= not(addcode); |
if address=X"000" then |
null; |
end if; |
when others => |
null; |
end case; |
|
end if; |
end process thetest; |
|
--! 512x18 rom con los componentes ax. |
AX : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => "memax.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "UNREGISTERED", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qa (17 downto 0) |
); |
|
--! 512x18 rom con los componentes ay. |
AY : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memay.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qa (35 downto 18) |
); |
|
--! 512x18 rom con los componentes az. |
AZ : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memaz.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qa (53 downto 36) |
); |
|
--! 512x18 rom con los componentes bx. |
BX : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\membx.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qb (17 downto 0) |
); |
|
--! 512x18 rom con los componentes by. |
BY : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memby.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qb (35 downto 18) |
); |
|
--! 512x18 rom con los componentes bz. |
BZ : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\membz.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qb (53 downto 36) |
); |
|
--! 512x18 rom con los componentes cx. |
CX : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memcx.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "UNREGISTERED", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qc (17 downto 0) |
); |
|
--! 512x18 rom con los componentes cy. |
CY : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memcy.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qc (35 downto 18) |
); |
|
--! 512x18 rom con los componentes cz. |
CZ : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memcz.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qc (53 downto 36) |
); |
|
--! 512x18 rom con los componentes dx. |
DX : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memdx.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qd (17 downto 0) |
); |
|
--! 512x18 rom con los componentes dy. |
DY : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memdy.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qd (35 downto 18) |
); |
|
--! 512x18 rom con los componentes dz. |
DZ : altsyncram |
generic map ( |
address_aclr_a => "NONE", |
clock_enable_input_a => "BYPASS", |
clock_enable_output_a => "BYPASS", |
init_file => ".\memdz.mif", |
intended_device_family => "Cyclone III", |
lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
lpm_type => "altsyncram", |
numwords_a => 512, |
operation_mode => "ROM", |
outdata_aclr_a => "NONE", |
outdata_reg_a => "CLOCK0", |
ram_block_type => "M9K", |
widthad_a => 9, |
width_a => 18, |
width_byteena_a => 1 |
) |
port map ( |
clock0 => clock, |
address_a => address, |
q_a => qd (53 downto 36) |
); |
|
end tb_arch; |
|
/arithpack.vhd
25,6 → 25,9
--! Paquete de definicion estandard de logica. |
use ieee.std_logic_1164.all; |
|
--use ieee.std_logic_unsigned.conv_integer; |
|
|
--! Biblioteca de definicion de memorias de altera |
library altera_mf; |
--! Paquete para manejar memorias internas tipo M9K |
33,6 → 36,12
--! Biblioteca de modulos parametrizados. |
library lpm; |
use lpm.all; |
|
--! Package de entrada y salida de texto. |
use std.textio.all; |
|
|
|
--! Package con las definiciones de constantes y entidades, que conformaran el Rt Engine. Tambien con algunas descripciones para realizar test bench. |
|
--! En general el package cuenta con entidades para instanciar, multiplicadores, sumadores/restadores y un decodificador de operaciones. |
44,9 → 53,15
|
constant rstMasterValue : std_logic := '1'; |
|
--! Constante: periodo del reloj; |
constant tclk : time := 20 ns; |
constant tclk2: time := tclk/2; |
constant tclk4: time := tclk/4; |
|
|
--! Generacion de Clock y de Reset. |
component clock_gen |
generic (tclk : time := 20 ns); |
generic (tclk : time := tclk); |
port (clk,rst : out std_logic); |
end component; |
|
181,5 → 196,27
cout : out std_logic |
); |
end component; |
|
|
|
procedure hexwrite_0(l:inout line; h: in std_logic_vector); |
|
end package; |
|
package body arithpack is |
--! Funciones utilitarias, relacionadas sobre todo con el testbench |
constant hexchars : string (1 to 16) := "0123456789ABCDEF"; |
|
procedure hexwrite_0(l:inout line;h:in std_logic_vector) is |
variable index_high,index_low,acc : integer; |
begin |
for i in (h'high)/4 downto 0 loop |
index_low:=i*4; |
if (index_low+3)>h'high then |
index_high := h'high; |
else |
index_high := i*4+3; |
end if; |
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high downto index_low)))); |
end loop; |
end procedure; |
end package body arithpack; |
/clock_gen.vhd
23,7 → 23,7
use work.arithpack.all; |
|
entity clock_gen is |
generic (tclk : time := 20 ns); |
generic (tclk : time := tclk); |
port (clk,rst : out std_logic); |
end entity clock_gen; |
|
33,9 → 33,11
begin |
resetproc: process |
begin |
rst<= '1'; |
wait for 50 ns; |
rst<= '0'; |
rst<= not(rstMasterValue); |
wait for 1 ns; |
rst<= rstMasterValue; |
wait for 52 ns; |
rst<= not(rstMasterValue); |
wait; |
end process resetproc; |
clockproc: process |
44,12 → 46,13
clk<='1'; |
clock_loop: |
loop |
wait for tclk/2; |
wait for tclk2; |
clk<='0'; |
wait for tclk/2; |
wait for tclk2; |
clk <= '1'; |
end loop clock_loop; |
end process clockproc; |
|
end clock_gen_arch; |
|
|