OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /raytrac/trunk
    from Rev 72 to Rev 73
    ↔ Reverse comparison
  •

Rev 72 → Rev 73

/arithpack.vhd
225,9 → 225,9
--! Procedimiento para escribir std_logic_vectors en formato hexadecimal.
procedure hexwrite_0(l:inout line; h: in std_logic_vector);
component shifter is
 
--! SqrtDiv Unit::shifter, esta unidad transforma el número entero A, en terminos de 2^N * m = A. El literal m corresponde al valor de la mantissa. En terminos de representaci'on binaria, la mantissa es el valor de la direcci'on de memoria que contiene el valor f(mantissa). El literal N corresponde al valor entero mayor m'as cercano del logaritmo en base 2 del n'umero entero A.
component shifter
generic (
address_width : integer := 9;
width : integer := 32;
241,7 → 241,32
);
end component;
 
--! SqrtDiv Unit::func, func, es una memoria que almacena alguna funci'on en el rango de [1,2). Los valores de la funci'on evaluada en este rango se encuentran almacenados en una memoria ROM que seleccione el desarrollador.
component func
generic (
memoryfilepath : string :="X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif"
);
port (
ad0,ad1 : in std_logic_vector (8 downto 0);
clk : in std_logic;
q0,q1 ; : out std_logic_vector(17 downto 0)
);
end component;
--! SqrtDiv Unit::shifter2xstage, esta unidad funciona tal cual la unidad shifter, pero al doble de la velocidad. El problema es que la entidad entrega dos valores de N: exp es un std_logic_vector la primera mitad entregar'a exp0 y la mitad mas significativa ser'a exp1.
--! De estos dos valores no signados, el valor que representa a N es el mayor de los 2. As'i mismo ocurre con las mantissas. Si el exp0 es mayor que exp1 se escoge add0 en vez de add1 y viceversa.
component shifter2xstage is
generic (
address_width : integer := 9;
width : integer := 32
);
port (
data : in std_logic_vector (width-1 downto 0);
exp : out std_logic_vector (2*integer(ceil(log(real(width),2.0)))-1 downto 0);
add : out std_logic_vector (2*address_width-1 downto 0);
zero : out std_logic
);
end shifter2xstage;
end package;
 
264,5 → 289,7
end if;
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high+h'low downto index_low+h'low))));
end loop;
end procedure;
end procedure;
end package body arithpack;
/sqrtdiv/RLshifter.vhd
29,10 → 29,10
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
--use work.arithpack.all;
 
 
 
 
entity RLshifter is
generic (
shiftFunction : string := "SQUARE_ROOT";
/sqrtdiv/memsqrt.mif
1,7 → 1,7
--RAND MAX: 0x7fff
--MINGW32 VERSION
DEPTH = 512;
WIDTH = 19;
WIDTH = 18;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT
/sqrtdiv/shifter2xstage.vhd
31,7 → 31,7
entity shifter2xstage is
generic (
address_width : integer := 9;
width : integer := 16
width : integer := 32
);
port (
data : in std_logic_vector (width-1 downto 0);
48,14 → 48,33
signal add0 : std_logic_vector (address_width-1 downto 0);
signal add1 : std_logic_vector (address_width-1 downto 0);
signal szero: std_logic_vector (1 downto 0);
function exp0StringParam()return string is
begin
if width rem 2 = 0 then
return "NO";
else
return "YES";
end if;
end exp0StringParam;
function exp1StringParam()return string is
begin
if width rem 2 = 0 then
return "YES";
else
return "NO";
end if;
end exp1StringParam;
 
begin
zero <= szero(1) and szero(0);
evenS:shifter
generic map (address_width,width,"YES")
generic map (address_width,width,exp0StringParam())
port map (data,exp0,add0,szero(0));
oddS:shifter
generic map (address_width,width,"NO")
generic map (address_width,width,exp1StringParam())
port map (data,exp1,add1,szero(1));
exp(integer(ceil(log(real(width),2.0)))-1 downto 0)<=exp0;
exp(2*integer(ceil(log(real(width),2.0)))-1 downto integer(ceil(log(real(width),2.0))))<=exp1;
/sqrtdiv/meminvr.mif
1,7 → 1,7
--RAND MAX: 0x7fff
--MINGW32 VERSION
DEPTH = 512;
WIDTH = 19;
WIDTH = 18;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT
/sqrtdiv/memsqrt2f.mif
1,7 → 1,7
--RAND MAX: 0x7fffffff
--UNIX BASED VERSION
DEPTH = 512;
WIDTH = 19;
WIDTH = 18;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT
/sqrtdiv/func.vhd
0,0 → 1,138
------------------------------------------------
--! @file func.vhd
--! @brief Functions for calculating x**-1, x**0.5, 2x**0.5
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------
 
 
-- RAYTRAC
-- Author Julian Andres Guarin
-- func.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
 
 
 
library ieee;
use ieee.std_logic_1164.all;
 
 
library altera_mf;
use altera_mf.all;
 
entity func is
generic (
memoryfilepath : string :="X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif";
);
port (
ad0,ad1 : in std_logic_vector (8 downto 0);
clk : in std_logic;
q0,q1 ; : out std_logic_vector(17 downto 0)
);
end func;
 
architecture func_arch of func is
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
END COMPONENT;
 
begin
 
altsyncram_component : altsyncram
generic map (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
--init_file => "X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif",
init_file => memoryfilepath,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 512,
numwords_b => 512,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
widthad_a => 9,
widthad_b => 9,
width_a => 18,
width_b => 18,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
port map (
clock0 => clock,
wren_a => '0',
address_b => ad1,
data_b => (others=>'0'),
wren_b => '0',
address_a => ad0,
data_a => (others=>'0'),
q_b => q1,
q_a => q0
);
 
 
end func_arch;
 
 
 
 
/sqrtdiv/sqrtdiv.vhd
0,0 → 1,212
--! @file sqrtdiv.vhd
--! @brief Unidad aritm'etica para calcular la potencia de un n'umero entero elevado a la -1 (INVERSION) o a la 0.5 (SQUARE_ROOT).
--! @author Juli&acute;n Andr&eacute;s Guar&iacute;n Reyes.
-- RAYTRAC
-- Author Julian Andres Guarin
-- sqrtdiv.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
 
 
library ieee
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
 
use work.arithpack.all;
 
 
entity sqrtdiv is
generic (
reginput: string := "YES";
c3width : integer := 18;
functype: string := "SQUARE_ROOT";
iwidth : integer := 32;
owidth : integer := 16;
awidth : integer := 9
);
port (
clk,rst : in std_logic;
value : in std_logic_vector (iwidth-1 downto 0);
zero : out std_logic;
result : out std_logic_vector (owidth-1 downto 0)
);
end sqrtdiv;
 
architecture sqrtdiv_arch of sqrtdiv is
 
--! expomantis::Primera etapa: Calculo parcial de la mantissa y el exponente.
signal expomantisvalue : std_logic_vector (iwidth-1 downto 0);
signal expomantisexp : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal expomantisadd : std_logic_vector (2*awidth-1 downto 0);
signal expomantiszero : std_logic;
--! funky::Segunda etapa: Calculo del valor de la funcion evaluada en f.
signal funkyadd : std_logic_vector (2*awidth-1 downto 0);
signal funkyexp : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal funkyzero : std_logic;
signal funkyq : std_logic_vector (2*c3width-1 downto 0);
signal funkyselector : std_logic;
--! cumpa::Tercera etapa: Selecci'on de valores de acuerdo al exp escogido.
signal cumpaexp : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal cumpaq : std_logic_vector (2*c3width-1 downto 0);
signal cumpaselector : std_logic;
signal cumpazero : std_logic;
signal cumpaN : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal cumpaF : std_logic_vector (c3width-1 downto 0);
--! chief::Cuarta etapa: Corrimiento a la izquierda o derecha, para el caso de la ra'iz cuadrada o la inversi'on respectivamente.
signal chiefN : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal chiefF : std_logic_vector (c3width-1 downto 0);
begin
!-- expomantis.
expomantisreg:
if reginput="YES" generate
expomantisProc:
process (clk,rst)
begin
if rst=rstMasterValue then
expomantisvalue <= (others =>'0');
elsif clk'event and clk='1' then
expomantisvalue <= vale;
end if;
end process expomantisProc;
end generate expomantisreg;
expomantisnoreg;
if reginput ="NO" generate
expomantisvalue<=value;
end generate expomantisnoreg;
expomantisshifter2x:shifter2xstage
generic map(awidth,iwidth)
port map(expomantisvalue,expomantisexp,expomantisadd,expomantiszero);
--! funky.
funkyProc:
process (clk,rst)
begin
if rst=rstMasterValue then
funkyexp <= (others => '0');
funkyzero <= '0';
else
funkyexp <= expomantisexp;
funkyzero <= expomantiszero;
end if;
end process funkyProc;
funkyadd <= expomantisadd;
funkyget:
process (funkyexp)
begin
if (funkyexp(integer(ceil(log(real(iwidth),2.0)))-1 downto 0)>funkyexp(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0))))) then
funkyselector<='0';
else
funkyselector<='1';
end if;
end process funkyget;
funkyinversion:
if functype="INVERSION" generate
meminvr:func
generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/meminvr.mif")
port map(
funkyadd(integer(ceil(log(real(iwidth),2.0)))-1 downto 0),
funkyadd(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0)))),
clk,
funkyq(c3width-1 downto 0),
funkyq(2*c3width-1 downto c3width));
end generate funkyinversion;
funkysquare_root:
if functype="SQUARE_ROOT" generate
sqrt: func
generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif")
port map(
funkyadd(integer(ceil(log(real(iwidth),2.0)))-1 downto 0),
ad1 => (others => '0'),
clk,
funkyq(c3width-1 downto 0),
open);
sqrt2x: func
generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt2f.mif")
port map(
ad0 => (others => '0'),
funkyadd(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0)))),
clk,
open,
funkyq(2*c3width-1 downto c3width));
end generate funkysquare_root;
--! cumpa.
cumpaProc:
process (clk,rst)
begin
if rst=rstMasterValue then
cumpaselector <= (others => '0');
cumpazero <= (others => '0');
cumpaexp <= (others => '0');
cumpaq <= (others => '0');
elsif clk'event and clk='1' then
cumpaselector <= funkyselector;
cumpazero <= funkyzero;
cumpaexp <= funkyexp;
cumpaq <= funkyq;
end if;
end process cumpaProc;
cumpaMux:
process (cumpaq,cumpaexp,cumpaselector)
begin
if cumpaselector='0' then
cumpaN<=cumpaexp(integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
cumpaF<=cumpaq(c3width-1 downto 0);
else
cumpaN<=cumpaexp(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0))));
cumpaF<=cumpaq(2*c3width-1 downto c3width);
end if;
end process cumpaMux;
--! chief.
chiefProc:
process (clk,rst)
begin
if rst=rstMasterValue then
chiefF <= (others => '0');
chiefN <= (others => '0');
elsif clk'event and clk='1' then
chiefF <= cumpaF;
chiefN <= cumpaN;
zero <= cumpazero;
end if;
end process chiefProc;
cumpaShifter: RLshifter
generic map(functype,c3width,owidth)
port map(chiefN,chiefF,result);
end sqrtdiv_arch;
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.