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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

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  • This comparison shows the changes necessary to convert path 
    /raytrac/trunk
    from Rev 73 to Rev 74
    ↔ Reverse comparison
  •

Rev 73 → Rev 74

/arithpack.vhd
53,7 → 53,7
type tbState is (abcd,axb,cxd,stop);
--! Constante con el nivel lógico de reset.
constant rstMasterValue : std_logic := '1';
constant rstMasterValue : std_logic := '0';
--! Constante: periodo del reloj, para una frecuencia de 50 MHz
constant tclk : time := 20 ns;
244,12 → 244,14
--! SqrtDiv Unit::func, func, es una memoria que almacena alguna funci'on en el rango de [1,2). Los valores de la funci'on evaluada en este rango se encuentran almacenados en una memoria ROM que seleccione el desarrollador.
component func
generic (
memoryfilepath : string :="X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif"
memoryfilepath : string :="X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif";
awidth : integer := 9;
qwidth : integer := 18
);
port (
ad0,ad1 : in std_logic_vector (8 downto 0);
clk : in std_logic;
q0,q1 ; : out std_logic_vector(17 downto 0)
ad0,ad1 : in std_logic_vector (awidth-1 downto 0) := (others => '0');
clk : in std_logic;
q0,q1 : out std_logic_vector(qwidth-1 downto 0)
);
end component;
--! SqrtDiv Unit::shifter2xstage, esta unidad funciona tal cual la unidad shifter, pero al doble de la velocidad. El problema es que la entidad entrega dos valores de N: exp es un std_logic_vector la primera mitad entregar'a exp0 y la mitad mas significativa ser'a exp1.
266,8 → 268,22
add : out std_logic_vector (2*address_width-1 downto 0);
zero : out std_logic
);
end shifter2xstage;
end component;
component RLshifter
generic (
shiftFunction : string := "SQUARE_ROOT";
mantissa_width : integer := 18;
iwidth : integer := 32;
owidth : integer := 16
);
port (
exp : in std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
mantis : in std_logic_vector (mantissa_width-1 downto 0);
result : out std_logic_vector (owidth-1 downto 0)
);
end component;
end package;
 
--! Funciones utilitarias, relacionadas sobre todo con el testbench
/sqrtdiv/exposelector.vhd File deleted \ No newline at end of file
/sqrtdiv/RLshifter.vhd
37,13 → 37,14
generic (
shiftFunction : string := "SQUARE_ROOT";
mantissa_width : integer := 18;
width : integer := 32
iwidth : integer := 32;
owidth : integer := 16
);
port (
exp : in std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
exp : in std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
mantis : in std_logic_vector (mantissa_width-1 downto 0);
result : out std_logic_vector (width-1 downto 0)
result : out std_logic_vector (owidth-1 downto 0)
);
end RLshifter;
 
55,15 → 56,19
process (mantis,exp)
variable expi : integer ;
begin
expi:= conv_integer(exp);
if shiftFunction="INVERSION" then
expi:= conv_integer(exp);
else
expi:= conv_integer(exp(exp'high downto 1));
end if;
for i in width-1 downto 0 loop
for i in owidth-1 downto 0 loop
 
result(i)<='0';
 
if shiftFunction="INVERSION" then
if i<=width-1-expi and i>=width-expi-mantissa_width then
result(i)<=mantis(mantissa_width-width+expi+i);
if i<=owidth-1-expi and i>=owidth-expi-mantissa_width then
result(i)<=mantis(mantissa_width-owidth+expi+i);
end if;
end if;
 
/sqrtdiv/shifter2xstage.vhd
49,7 → 49,7
signal add1 : std_logic_vector (address_width-1 downto 0);
signal szero: std_logic_vector (1 downto 0);
function exp0StringParam()return string is
function exp0StringParam return string is
begin
if width rem 2 = 0 then
return "NO";
57,7 → 57,7
return "YES";
end if;
end exp0StringParam;
function exp1StringParam()return string is
function exp1StringParam return string is
begin
if width rem 2 = 0 then
return "YES";
71,10 → 71,10
begin
zero <= szero(1) and szero(0);
evenS:shifter
generic map (address_width,width,exp0StringParam())
generic map (address_width,width,exp0StringParam)
port map (data,exp0,add0,szero(0));
oddS:shifter
generic map (address_width,width,exp1StringParam())
generic map (address_width,width,exp1StringParam)
port map (data,exp1,add1,szero(1));
exp(integer(ceil(log(real(width),2.0)))-1 downto 0)<=exp0;
exp(2*integer(ceil(log(real(width),2.0)))-1 downto integer(ceil(log(real(width),2.0))))<=exp1;
/sqrtdiv/func.vhd
34,12 → 34,16
 
entity func is
generic (
memoryfilepath : string :="X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif";
awidth : integer := 9;
qwidth : integer := 18
);
port (
ad0,ad1 : in std_logic_vector (8 downto 0);
clk : in std_logic;
q0,q1 ; : out std_logic_vector(17 downto 0)
ad0,ad1 : in std_logic_vector (awidth-1 downto 0) := (others => '0');
clk : in std_logic;
q0,q1 : out std_logic_vector(qwidth-1 downto 0)
);
end func;
 
118,7 → 122,7
wrcontrol_wraddress_reg_b => "CLOCK0"
)
port map (
clock0 => clock,
clock0 => clk,
wren_a => '0',
address_b => ad1,
data_b => (others=>'0'),
/sqrtdiv/sqrtdiv.vhd
20,7 → 20,7
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
 
 
library ieee
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
33,9 → 33,9
generic (
reginput: string := "YES";
c3width : integer := 18;
functype: string := "SQUARE_ROOT";
functype: string := "INVERSION";
iwidth : integer := 32;
owidth : integer := 16;
owidth : integer := 18;
awidth : integer := 9
);
port (
69,18 → 69,34
signal cumpaselector : std_logic;
signal cumpazero : std_logic;
signal cumpaN : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal cumpaN : std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal cumpaF : std_logic_vector (c3width-1 downto 0);
--! chief::Cuarta etapa: Corrimiento a la izquierda o derecha, para el caso de la ra'iz cuadrada o la inversi'on respectivamente.
signal chiefN : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal chiefN : std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
signal chiefF : std_logic_vector (c3width-1 downto 0);
--! Constantes para manejar el tama&ntilde;o de los vectores
constant exp1H : integer := 2*integer(ceil(log(real(iwidth),2.0)))-1;
constant exp1L : integer := integer(ceil(log(real(iwidth),2.0)));
constant exp0H : integer := exp1L-1;
constant exp0L : integer := 0;
constant add1H : integer := 2*awidth-1;
constant add1L : integer := awidth;
constant add0H : integer := add1L-1;
constant add0L : integer := 0;
constant c3qHH : integer := 2*c3width-1;
constant c3qHL : integer := c3width;
constant c3qLH : integer := c3width-1;
constant c3qLL : integer := 0;
begin
!-- expomantis.
--! expomantis.
expomantisreg:
if reginput="YES" generate
expomantisProc:
89,14 → 105,16
if rst=rstMasterValue then
expomantisvalue <= (others =>'0');
elsif clk'event and clk='1' then
expomantisvalue <= vale;
expomantisvalue <= value;
end if;
end process expomantisProc;
end generate expomantisreg;
expomantisnoreg;
expomantisnoreg:
if reginput ="NO" generate
expomantisvalue<=value;
end generate expomantisnoreg;
expomantisshifter2x:shifter2xstage
generic map(awidth,iwidth)
port map(expomantisvalue,expomantisexp,expomantisadd,expomantiszero);
103,14 → 121,13
--! funky.
funkyProc:
process (clk,rst)
process (clk,rst,expomantisexp, expomantiszero)
begin
if rst=rstMasterValue then
funkyexp <= (others => '0');
funkyzero <= '0';
else
funkyexp <= expomantisexp;
elsif clk'event and clk='1' then
funkyexp(exp1H downto 0) <= expomantisexp(exp1H downto 0);
funkyzero <= expomantiszero;
end if;
end process funkyProc;
118,22 → 135,23
funkyget:
process (funkyexp)
begin
if (funkyexp(integer(ceil(log(real(iwidth),2.0)))-1 downto 0)>funkyexp(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0))))) then
if (funkyexp(exp0H downto 0)>funkyexp(exp1H downto exp1L)) then
funkyselector<='0';
else
funkyselector<='1';
end if;
end process funkyget;
funkyinversion:
if functype="INVERSION" generate
meminvr:func
generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/meminvr.mif")
port map(
funkyadd(integer(ceil(log(real(iwidth),2.0)))-1 downto 0),
funkyadd(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0)))),
funkyadd(add0H downto add0L),
funkyadd(add1H downto add1L),
clk,
funkyq(c3width-1 downto 0),
funkyq(2*c3width-1 downto c3width));
funkyq(c3qLH downto c3qLL),
funkyq(c3qHH downto c3qHL));
end generate funkyinversion;
funkysquare_root:
if functype="SQUARE_ROOT" generate
140,30 → 158,29
sqrt: func
generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif")
port map(
funkyadd(integer(ceil(log(real(iwidth),2.0)))-1 downto 0),
ad1 => (others => '0'),
funkyadd(add0H downto add0L),
(others => '0'),
clk,
funkyq(c3width-1 downto 0),
funkyq(c3qLH downto c3qLL),
open);
sqrt2x: func
generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt2f.mif")
port map(
ad0 => (others => '0'),
funkyadd(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0)))),
(others => '0'),
funkyadd(add1H downto add1L),
clk,
open,
funkyq(2*c3width-1 downto c3width));
funkyq(c3qHH downto c3qHL));
end generate funkysquare_root;
--! cumpa.
cumpaProc:
process (clk,rst)
begin
if rst=rstMasterValue then
cumpaselector <= (others => '0');
cumpazero <= (others => '0');
cumpaselector <= '0';
cumpazero <= '0';
cumpaexp <= (others => '0');
cumpaq <= (others => '0');
elsif clk'event and clk='1' then
177,11 → 194,11
process (cumpaq,cumpaexp,cumpaselector)
begin
if cumpaselector='0' then
cumpaN<=cumpaexp(integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
cumpaF<=cumpaq(c3width-1 downto 0);
cumpaN<=cumpaexp(exp0H downto exp0L);
cumpaF<=cumpaq(c3qLH downto c3qLL);
else
cumpaN<=cumpaexp(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0))));
cumpaF<=cumpaq(2*c3width-1 downto c3width);
cumpaN<=cumpaexp(exp1H downto exp1L);
cumpaF<=cumpaq(c3qHH downto c3qHL);
end if;
end process cumpaMux;
198,9 → 215,12
zero <= cumpazero;
end if;
end process chiefProc;
cumpaShifter: RLshifter
generic map(functype,c3width,owidth)
port map(chiefN,chiefF,result);
chiefShifter: RLshifter
generic map(functype,c3width,iwidth,owidth)
port map(
chiefN,
chiefF,
result);
end sqrtdiv_arch;

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