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    /raytrac/trunk
    from Rev 77 to Rev 78
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Rev 77 → Rev 78

/raytrac.vhd
98,9 → 98,10
A,B,C,D : in std_logic_vector(18*3-1 downto 0); --! Vectores de entrada A,B,C,D, cada uno de tamano fijo: 3 componentes x 18 bits. \n Input vectors A,B,C,D, each one of fixed size: 3 components x 18 bits.
opcode,addcode : in std_logic; --! Opcode and addcode input bits, opcode selects what operation is going to perform one of the entities included in the design and addcode what operands are going to be involved in such. \n Opcode & addcode, opcode selecciona que operacion se va a llevar a cabo dentro de una de las entidades referenciadas dentro de la descripcion, mientras que addcode decide cuales van a ser los operandos que realizaran tal.
clk,rst,ena : in std_logic; --! Las senales de control usual. The usual control signals.
sqrt0,sqrt1 : out std_logic_vector(17 downto 0);
addABx,addABy,addABz,addCDx,addCDy,addCDz : out std_logic_vector(17 downto 0);--! Suma de vectores.
subABx,subABy,subABz,subCDx,subCDy,subCDz : out std_logic_vector(17 downto 0);--! Suma de vectores.
CPX,CPY,CPZ,DP0,DP1,kvx0,kvy0,kvz0,kvx1,kvy1,kvz1 : out std_logic_vector(31 downto 0);--! Salidas que representan los resultados del RayTrac: pueden ser dos resultados, de dos operaciones de producto punto, o un producto cruz. Por favor revisar el documento de especificacion del dispositivo para tener mas claridad.\n Outputs representing the result of the RayTrac entity: can be the results of two parallel dot product operations or the result of a single cross product, in order to clarify refere to the entity specification documentation.
CPX,CPY,CPZ,DP0,DP1,kvx0,kvy0,kvz0,kvx1,kvy1,kvz1 : out std_logic_vector(31 downto 0) --! Salidas que representan los resultados del RayTrac: pueden ser dos resultados, de dos operaciones de producto punto, o un producto cruz. Por favor revisar el documento de especificacion del dispositivo para tener mas claridad.\n Outputs representing the result of the RayTrac entity: can be the results of two parallel dot product operations or the result of a single cross product, in order to clarify refere to the entity specification documentation.
);
172,19 → 173,35
end process procNotReg;
end generate notreg;
--! El siguiente sumador es un sumador de 18 bits por lo tanto no se utiliza el sumador de 32 bits en la etapa SR del UF.
addABx <= SA(17 downto 0) + SB(17 downto 0);
addABy <= SA(35 downto 18) + SB(35 downto 18);
addABz <= SA(53 downto 36) + SB(53 downto 36);
addCDx <= SC(17 downto 0) + SD(17 downto 0);
addCDy <= SC(35 downto 18) + SD(35 downto 18);
addCDz <= SC(53 downto 36) + SD(53 downto 36);
subABx <= SA(17 downto 0) - SB(17 downto 0);
subABy <= SA(35 downto 18) - SB(35 downto 18);
subABz <= SA(53 downto 36) - SB(53 downto 36);
subCDx <= SC(17 downto 0) - SD(17 downto 0);
subCDy <= SC(35 downto 18) - SD(35 downto 18);
subCDz <= SC(53 downto 36) - SD(53 downto 36);
procaddsub:
process (clk,rst,SA,SB,SC,SD)
begin
if rst=rstMasterValue then
addABx <= (others => '0');
addABy <= (others => '0');
addABz <= (others => '0');
subABx <= (others => '0');
subABy <= (others => '0');
subABz <= (others => '0');
elsif clk'event and clk='1' then
addABx <= SA(17 downto 0) + SB(17 downto 0);
addABy <= SA(35 downto 18) + SB(35 downto 18);
addABz <= SA(53 downto 36) + SB(53 downto 36);
addCDx <= SC(17 downto 0) + SD(17 downto 0);
addCDy <= SC(35 downto 18) + SD(35 downto 18);
addCDz <= SC(53 downto 36) + SD(53 downto 36);
subABx <= SA(17 downto 0) - SB(17 downto 0);
subABy <= SA(35 downto 18) - SB(35 downto 18);
subABz <= SA(53 downto 36) - SB(53 downto 36);
subCDx <= SC(17 downto 0) - SD(17 downto 0);
subCDy <= SC(35 downto 18) - SD(35 downto 18);
subCDz <= SC(53 downto 36) - SD(53 downto 36);
end if;
end process procaddsub;
--! Instantiate Opcoder
opcdr : opcoder
/uf.vhd
27,6 → 27,9
 
use ieee.std_logic_signed.all;
 
--! Paquete para calculo de funciones reales.
use ieee.math_real.all;
 
--! Paquete estandar de texto
use std.textio.all;
 
41,15 → 44,18
--! Esta entidad utiliza las se&ntilde;ales de control clk y rst.
--! \n\n
--! La caracter&iacute;stica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo &oacute; una operaci&oacute;n de producto cruz. La otra caracter&iacute;stica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomar&acute; 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
 
--! Es importante entender que las resultados de las operaciones, correspondientes a las salidas de esta entidad no est'an conectadas directamente a la salida del circuito combinatorio que ejecuta sus repectivas operaciones: en vez de ello, los resutados est'an conectados a la salida de un registro.
--! Este circuito es una ALU
entity uf is
generic (
use_std_logic_signed : string := "NO";
testbench_generation : string := "NO";
carry_logic : string := "CLA"
square_root_width : integer := 16;
use_std_logic_signed : string := "NO";
testbench_generation : string := "NO";
carry_logic : string := "CLA"
);
port (
opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operaci&oacute;n que se lleva a cabo en la primera etapa de sumadores/restadores.
exp0,exp1 : in std_logic_vector(integer(ceil(log(real(square_root_width),2.0)))-1 downto 0); --! Junto con la mantissa este es el exponente del valor flotante, mejora muchisimo la precisi'on.
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripci&oacute;n.
cpx,cpy,cpz,dp0,dp1,kvx0,kvy0,kvz0,kvx1,kvy1,kvz1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritm&eacute;ticas: cpx,cpy,cpz ser&acute;n los componentes del vector que da por resultado el producto cruz entre los vectores AxB &oacute; CxD. kvx0, kvy0, kvz0, kvx1, kvy1, kvz1 es el resultado de los multiplicadores
clk,rst : in std_logic --! Las entradas de control usuales.
61,8 → 67,10
-- Stage 0 signals
 
 
signal stage0p0,stage0p1, stage0p2, stage0p3, stage0p4, stage0p5 : std_logic_vector(31 downto 0); --! Se&ntilde;ales / buses, con los productos de los multiplicadores.
 
signal stage0exp0 : std_logic_vector(integer(ceil(log(real(square_root_width),2.0)))-1 downto 0);
signal stage0exp1 : std_logic_vector(integer(ceil(log(real(square_root_width),2.0)))-1 downto 0);
--Stage 1 signals
69,6 → 77,8
 
 
 
signal stage1exp0 : std_logic_vector(integer(ceil(log(real(square_root_width),2.0)))-1 downto 0);
signal stage1exp1 : std_logic_vector(integer(ceil(log(real(square_root_width),2.0)))-1 downto 0);
-- Some support signals
 
223,61 → 233,7
stage2a4 <= stage2p3+stage2a2;
end generate useIeee;
dontUseIeee:
if use_std_logic_signed="NO" generate
--! Adder 0, 16 bit carry lookahead low adder.
a0low : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stageSRopcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
--Adder 0, 16 bit carry lookahead high adder.
a0high : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stageSRopcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
--! Adder 1, 16 bit carry lookahead low adder.
a1low : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p2(15 downto 0),stage1p3(15 downto 0),'1','0',stage1a1(15 downto 0),stage1_internalCarry(1));
--! Adder 1, 16 bit carry lookahead high adder.
a1high : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p2(31 downto 16),stage1p3(31 downto 16),'1',stage1_internalCarry(1),stage1a1(31 downto 16),open);
--! Adder 2, 16 bit carry lookahead low adder.
a2low : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stageSRopcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
--! Adder 2, 16 bit carry lookahead high adder.
a2high : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stageSRopcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
-- Adder Instantiation (Stage 2)
--! Adder 3, 16 bit carry lookahead low adder.
a3low : adder
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2a0(15 downto 0),stage2p2(15 downto 0),'0','0',stage2a3(15 downto 0),stage2_internalCarry(0));
--Adder 3, 16 bit carry lookahead high adder.
a3high : adder
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2a0(31 downto 16),stage2p2(31 downto 16),'0',stage2_internalCarry(0),stage2a3(31 downto 16),open);
--! Adder 4, 16 bit carry lookahead low adder.
a4low : adder
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2p3(15 downto 0),stage2a2(15 downto 0),'0','0',stage2a4(15 downto 0),stage2_internalCarry(1));
--! Adder 4, 16 bit carry lookahead high adder.
a4high : adder
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2p3(31 downto 16),stage2a2(31 downto 16),'0',stage2_internalCarry(1),stage2a4(31 downto 16),open);
end generate dontUseIeee;
-- Incoming from opcoder.vhd signals into pipeline's stage 0.
stage0mf00 <= m0f0;
stage0mf01 <= m0f1;
303,9 → 259,13
--Outcoming to the rest of the system (by the time i wrote this i dont know where this leads to... jeje)
--May 31 23:31:56 Guess What!, now I know!!!
cpx <= stage1a0;
cpy <= stage1a1;
cpz <= stage1a2;
dp0 <= stage2a3;
dp1 <= stage2a4;
473,8 → 433,62
end process tbproc2;
 
end generate tbgen;
dontUseIeee:
if use_std_logic_signed="NO" generate
--! Adder 0, 16 bit carry lookahead low adder.
a0low : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stageSRopcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
--Adder 0, 16 bit carry lookahead high adder.
a0high : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stageSRopcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
--! Adder 1, 16 bit carry lookahead low adder.
a1low : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p2(15 downto 0),stage1p3(15 downto 0),'1','0',stage1a1(15 downto 0),stage1_internalCarry(1));
--! Adder 1, 16 bit carry lookahead high adder.
a1high : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p2(31 downto 16),stage1p3(31 downto 16),'1',stage1_internalCarry(1),stage1a1(31 downto 16),open);
--! Adder 2, 16 bit carry lookahead low adder.
a2low : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stageSRopcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
--! Adder 2, 16 bit carry lookahead high adder.
a2high : adder
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stageSRopcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
-- Adder Instantiation (Stage 2)
--! Adder 3, 16 bit carry lookahead low adder.
a3low : adder
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2a0(15 downto 0),stage2p2(15 downto 0),'0','0',stage2a3(15 downto 0),stage2_internalCarry(0));
--Adder 3, 16 bit carry lookahead high adder.
a3high : adder
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2a0(31 downto 16),stage2p2(31 downto 16),'0',stage2_internalCarry(0),stage2a3(31 downto 16),open);
--! Adder 4, 16 bit carry lookahead low adder.
a4low : adder
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2p3(15 downto 0),stage2a2(15 downto 0),'0','0',stage2a4(15 downto 0),stage2_internalCarry(1));
--! Adder 4, 16 bit carry lookahead high adder.
a4high : adder
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
-- Dont instantiate Xor gates stage in the adder.
port map (stage2p3(31 downto 16),stage2a2(31 downto 16),'0',stage2_internalCarry(1),stage2a4(31 downto 16),open);
end generate dontUseIeee;
end uf_arch;
/sqrtdiv/RLshifter.vhd
59,7 → 59,7
if shiftFunction="INVERSION" then
expi:= conv_integer(exp);
else
expi:= conv_integer(exp(exp'high downto 1));
expi:= conv_integer(exp(exp'high downto 1)); --! Por qu'e hasta 1 y no hasta 0!? Porque el corrimiento de la raiz cuadrada es 2^(N/2)
end if;
for i in owidth-1 downto 0 loop
/sqrtdiv/sqrtdiv.vhd
34,7 → 34,7
reginput: string := "YES";
c3width : integer := 18;
functype: string := "INVERSION";
iwidth : integer := 32;
iwidth : integer := 18;
owidth : integer := 18;
awidth : integer := 9
);
/sqrtdiv/shift.vhd
34,7 → 34,7
generic (
address_width : integer := 9;
width : integer := 32;
--! Cuando even shifter es "YES" se hara la busqueda del primer bit con valor 1, de izquierda a derecha, pero NO de uno
--! Cuando even shifter es "YES" se hara la busqueda del primer bit con valor 1, de izquierda a derecha, pero NO de uno en uno.
even_shifter : string := "YES"
);

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