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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

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  • This comparison shows the changes necessary to convert path 
    /raytrac
    from Rev 106 to Rev 107
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Rev 106 → Rev 107

/trunk/fpbranch/unrm/unrm1.vhd
8,4 → 8,5
clk,signdelta,signa,signb,zeroa,zerob : in std_logic;
shiftbin, shiftbout : in std_logic_vector (4 downto 0);
expbin,expout : out std_logic_vector(7 downto 0);
clk,
/trunk/fpbranch/unrm/shftr.vhd
5,9 → 5,9
 
entity shftr is
port (
dir : in std_logic;
places : in std_logic_vector (3 downto 0);
data24 : in std_logic_vector (23 downto 0);
sgndelta,signa,sgnb : in std_logic;
places : in std_logic_vector (4 downto 0);
data24a,data24b : in std_logic_vector (22 downto 0);
data40 : out std_logic_vector (39 downto 0)
);
end shftr;
31,66 → 31,112
);
end component;
signal splaces : std_logic_vector (8 downto 0);
signal sdata24 : std_logic_vector (26 downto 0);
signal sdata32 : std_logic_vector (31 downto 0);
signal sresult : std_logic_vector (53 downto 0);
signal pha,phb : std_logic_vector(26 downto 0);
signal sfactora,sfactorb,sfactor : std_logic_vector(8 downto 0);
signal sma,smb,ssma,ssmb,ssm : std_logic_vector(24 downto 0);
signal slaba,slabb : std_logic_vector(14 downto 0);
signal shiftslab : std_logic_vector(23 downto 0);
signal xplaces,splaces : std_logic_vector (4 downto 0);
 
begin
 
process (places(2 downto 0))
--! Decodificar la magnitud del corrimiento
process (sgndelta,places,signa,signb)
begin
case places(2 downto 0) is
when "000" => splaces <= "000000001";
when "001" => splaces <= "000000010";
when "010" => splaces <= "000000100";
when "011" => splaces <= "000001000";
when "100" => splaces <= "000010000";
when "101" => splaces <= "000100000";
when "110" => splaces <= "001000000";
when others => splaces <="010000000";
for i in 4 downto 0 loop
xplaces(i) <= places(i) xor sgndelta;
end loop;
splaces <= xplaces+("0000"&sgndelta);
if sgndelta='1' then
shiftslab <= signa;
else
shiftslab <= signb;
end if;
end process;
--! Decodificar el factor de corrimiento
process (shftslab,splaces)
begin
case splaces(2 downto 0) is
when x"0" => sfactor(8 downto 0) <= shiftslab(0 downto 0) & "10000000";
when x"1" => sfactor(8 downto 0) <= shiftslab(1 downto 0) & "1000000";
when x"2" => sfactor(8 downto 0) <= shiftslab(2 downto 0) & "100000";
when x"3" => sfactor(8 downto 0) <= shiftslab(3 downto 0) & "10000";
when x"4" => sfactor(8 downto 0) <= shiftslab(4 downto 0) & "1000";
when x"5" => sfactor(8 downto 0) <= shiftslab(5 downto 0) & "100";
when x"6" => sfactor(8 downto 0) <= shiftslab(6 downto 0) & "10";
when others => sfactor(8 downto 0) <=shiftslab(7 downto 0) &"1";
end case;
end process;
sdata24(26 downto 24) <= (others => '0');
process (dir,data24,sdata32)
variable offset : integer;
--! Asignar el factor de corrimiento las mantissas
process (sgndelta,signa,signb)
begin
if places(3) ='1' then
offset:=8;
else
offset:=0;
end if;
data40 <= (others => '0');
case sgndelta is
when '1' => -- Negativo b>a : se corre a delta espacios a la derecha y b se queda quieto
sfactorb <= signb&"10000000";
sfactora <= sfactor;
when others => -- Positivo a>=b : se corre a delta espacios a la derecha y a se queda quieto
sfactorb <= sfactor;
sfactora <= signa&"10000000";
end case;
if dir='1' then --! Corrimiento a la derecha
for i in 23 downto 0 loop
sdata24(i) <= data24(23-i);
end loop;
for i in 31 downto 0 loop
data40(i+8-offset) <= sdata32(31-i);
end loop;
else
sdata24(23 downto 0) <= data24;
for i in 31 downto 0 loop
data40(i+offset) <= sdata32(i);
end loop;
end if;
slaba <= (others => signa);
slabb <= (others => signb);
end process
 
--! Correr las mantissas y calcularlas.
 
hmulta: lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","SIGNED","LPM_MULT",9,18,27)
port map (sfactora,signa&'1'&data24a(22 downto 0),pha);
lmulta: lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","SIGNED","LPM_MULT",9,9,27)
port map (sfactora,signa&'1'&data24a(6 downto 0),pla);
hmultb: lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","SIGNED","LPM_MULT",9,18,27)
port map (sfactorb,signb&'1'&data24b(22 downto 0),phb);
lmultb: lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","SIGNED","LPM_MULT",9,9,27)
port map (sfactorb,signb&'1'&data24b(6 downto 0),plb);
sma <= pha(24 downto 0) + (slaba&pla(17 downto 8));
smb <= phb(24 downto 0) + (slabb&plb(17 downto 8));
--! Sumar las mantissas signadas y colocar los 0's que hagan falta
process (sgndelta,sma,smb,splaces(4 downto 3))
begin
splaces <= places+sgndelta;
case sgndelta is
when '1' => -- Negativo b>a : se corre a delta espacios a la derecha y b se queda quieto
ssmb <= smb;
case splaces(4 downto 3) is
when x"3" => ssma <= (sma(24)&shiftslab(23 downto 0));
when x"2" => ssma <= (sma(24)&shiftslab(15 downto 0)&sma(23 downto 16));
when x"1" => ssma <= (sma(24)&shiftslab(7 downto 0)&sma(23 downto 8));
when others => ssma <= sma;
end case;
when others => -- Positivo a>=b : se corre a delta espacios a la derecha y a se queda quieto
case splaces(4 downto 3) is
when x"3" => ssmb <= (smb(24)&shiftslab(23 downto 0));
when x"2" => ssmb <= (smb(24)&shiftslab(15 downto 0)&smb(23 downto 16));
when x"1" => ssmb <= (smb(24)&shiftslab(7 downto 0)&smb(23 downto 8));
when others => ssmb <= smb;
end case;
end case;
ssm <= ssma+ssmb;
end process;
the_shifter:
for i in 2 downto 0 generate
shiftermultiplier: lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
port map (splaces,sdata24(i*9+8 downto i*9),sresult(i*18+17 downto i*18));
end generate;
--! Mantissas sumadas, denormalizar
sdata32(31 downto 27) <= sresult(49 downto 45);
sdata32(26 downto 18) <= sresult(44 downto 36) or sresult(35 downto 27);
sdata32(17 downto 09) <= sresult(26 downto 18) or sresult(17 downto 09);
sdata32(08 downto 00) <= sresult(08 downto 00);
 
end shftr_arch;
/trunk/fpbranch/add/ema32x2.vhd
61,6 → 61,7
signal s3res : std_logic_vector(25 downto 0); -- Signed mantissa result
signal s1pS,s1pH,s1pL,s4nrmL,s4nrmH,s4nrmS : std_logic_vector(17 downto 0); -- Shifert Product
signal s0zeroa,s0zerob,s1zeroa,s1zerob,s1z,s4sgr : std_logic;
signal s2sma,s2smb : std_logic_vector (56 downto 0);
begin
 
76,22 → 77,22
s0b(22 downto 0) <= b32(22 downto 0);
--!Etapa 0,Calcular la manera en que se llevara a cabo la desnormalizacion
s1signa <= s0a(31);
s1signb <= s0b(31);
s1dira <= s0sdelta(7);
s1dirb <= not(s0sdelta(7));
s1uma <= s0a(22 downto 0);
s1umb <= s0b(22 downto 0);
if s0zeroa='0' or s0zerob='0' then
if sa(30 downto 23) = "00000000" or sb(30 downto 23) = "00000000" then
s1expb <= s0b(30 downto 23) or s0a(30 downto 23);
s1udeltaa <= "0000";
s1udeltab <= "0000";
s1zero <= '1';
else
s1expb <= s0b(30 downto 23);
s1udeltaa <= s0udeltaa(3 downto 0);
s1udeltab <= s1udeltab(3 downto 0);
s1zero <= '0';
end if;
s1zeroa <= s0zeroa;
s1zerob <= s0zerob;
--! Etapa 1: Denormalizaci&oacute;n de las mantissas.
217,8 → 218,32
--! Combinatorial Gremlin, Etapa 1 Denormalizaci&oacute;n de las mantissas.
shftra:shftr
port map (s1dira,s1udeltaa(2 downto 0),s1uma,
port map (s1dira,s1udeltaa(3 downto 0),'1'&s1uma,s1data40a);
shftrb:shftr
port map (not(s1dira),s1udeltab(3 downto 0),'1'&s1umb,s1data40b);
process (s1data40b,s1data40a)
begin
if s1dira='1' then
s1signeddata56a(55 downto 40) <= (others => '0');
s1signeddata56b(15 downto 0) <= (others => '0');
for i in 39 downto 0 loop
s1signeddata56a(i) <= s1signa xor s1data40a(i);
s1signeddata56b(i+16) <= s1signb xor s1data40b(i);
end loop;
else
s1signeddata56a(15 downto 0) <= (others => '0');
s1signeddata56b(55 downto 40) <= (others => '0');
for i in 39 downto 0 loop
s1signeddata56a(i+16) <= s1signa xor s1data40a(i);
s1signeddata56b(i) <= s1signb xor s1data40b(i);
end loop;
end if;
end process;
s1b2b1s:
for i in 22 downto 0 generate
b1s(i) <= s1b(22-i);

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