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/branches/fp/dpc.vhd
1,10 → 1,10
--! @file opcoder.vhd
--! @file dpc.vhd
--! @brief Decodificador de operacion.
 
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- opcoder.vhd
-- dpc.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
20,130 → 20,95
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
 
 
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
library ieee;
--! Paquete de definicion estandard de logica. Standard logic definition pack.
use ieee.std_logic_1164.all;
--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
use work.arithpack.all;
 
--! La entidad opcoder es la etapa combinatoria que decodifica la operacion que se va a realizar.
 
--! \n\n
--! Las entradas a esta descripci&oacute;n son: los vectores A,B,C,D, las entradas opcode y addcode. Las salidas del decodificador, estar&aacute;n conectadas a las entradas de los 6 multiplicadores de una entidad uf. Los operandos de los multiplicadores, tambi&eacute;n conocidos como factores, son las salida m0f0, m0f1 para el multiplicador 1 y as&iacute; hasta el multiplicador 5. B&aacute;sicamente lo que opera aqu&iacute; en esta descripci&oacute;n es un multiplexor, el cual selecciona a trav&eacute;s de opcode y addcode qu&eacute; componentes de los vectores se conectaran a los operandos de los multiplicadores.
entity opcoder is
entity dpc is
generic (
width : integer := 18;
structuralDescription : string:= "NO"
width : integer := 32
);
port (
Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (width-1 downto 0);
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (width-1 downto 0);
paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
prd32blko,add32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores y los 6 sumadores.
sqr32blko,inv32blko : in std_logic_vector ((02*width)-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
fifo32o : in std_logic_vector ( width-1 downto 0); --! Salida de la cola intermedia.
instr3 : in std_logic_vector ( 2 downto 0); --! Opcode con la instrucci&oacute;n.
fifo32i : out std_logic_vector ( width-1 downto 0); --! Entrada a la cola intermedia.
prd32blki,add32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 sumandos y de los 12 factores en los 2 bloques de suma y el bloque de multiplicaci&oacute;n respectivamente.
add32blks : out std_logic_vector ( 1 downto 0); --! Signos de operaci&oacute;n que entran en los 2 bloques de suma.
resultoutput : out std_logic_vector ((06*width)-1 downto 0) --! 6 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
opcode,addcode : in std_logic
);
end entity;
end dpc;
 
--! Arquitectura del decodificador de operaci&oacute;n.
 
--! El bloque de arquitectura del decodificador es simplemente una cascada de multiplexores. La selecci&oacute;n se hace en funci&oacute;n de las se&ntilde;ales appcode y addcode\n
--! La siguiente tabla describe el comportamiento de los multiplexores:\n
--! \n\n
--!
--! <table>
--! <tr><th></th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th>&nbsp;</th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th>&nbsp;</th></tr> <tr><td>m0</td><td>0</td><td>0</td><td>Ax</td><td>Bx</td><td>&nbsp;</td><td>0</td><td>0</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>0</td><td>1</td><td>Ax</td><td>Bx</td><td>&nbsp;</td><td>0</td><td>1</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>0</td><td>Ay</td><td>Bz</td><td>&nbsp;</td><td>1</td><td>0</td><td>Ax</td><td>Bz</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>1</td><td>Cy</td><td>Dz</td><td>&nbsp;</td><td>1</td><td>1</td><td>Cx</td><td>Dz</td><td>m3</td></tr> <tr><td>m1</td><td>0</td><td>0</td><td>Ay</td><td>By</td><td>&nbsp;</td><td>0</td><td>0</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>0</td><td>1</td><td>Ay</td><td>By</td><td>&nbsp;</td><td>0</td><td>1</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>0</td><td>Az</td><td>By</td><td>&nbsp;</td><td>1</td><td>0</td><td>Ax</td><td>By</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>1</td><td>Cz</td><td>Dy</td><td>&nbsp;</td><td>1</td><td>1</td><td>Cx</td><td>Dy</td><td>m4</td></tr> <tr><td>m2</td><td>0</td><td>0</td><td>Az</td><td>Bz</td><td>&nbsp;</td><td>0</td><td>0</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>0</td><td>1</td><td>Az</td><td>Bz</td><td>&nbsp;</td><td>0</td><td>1</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>0</td><td>Az</td><td>Bx</td><td>&nbsp;</td><td>1</td><td>0</td><td>Ay</td><td>Bx</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>1</td><td>Cz</td><td>Dx</td><td>&nbsp;</td><td>1</td><td>1</td><td>Cy</td><td>Dx</td><td>m5</td></tr></table>
--! \n\n
 
 
architecture opcoder_arch of opcoder is
architecture dpc_arch of dpc is
signal aycy,bzdz,azcz,bydy,bxdx,axcx: std_logic_vector(width-1 downto 0);
component scfifo
generic (
add_ram_output_register : string;
intended_device_family : string;
lpm_hint : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port (
rd
)
begin
--! Proceso que describe las 2 etapas de multiplexores.
 
constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
constant cz : integer := 06;constant cy : integer := 07;constant cx : integer := 08;constant dz : integer := 09;constant dy : integer := 10;constant dx : integer := 11;
constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
constant s6 : integer := 06;constant s7 : integer := 07;constant s8 : integer := 08;constant s9 : integer := 09;constant s10: integer := 10;constant s11: integer := 11;
constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;constant aa : integer := 03;constant ab : integer := 04;constant ac : integer := 05;
constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
constant sqrt320 : integer := 00;
constant sqrt321 : integer := 01;
constant invr320 : integer := 00;
constant invr321 : integer := 01;
 
originalMuxGen:
if structuralDescription="NO" generate
type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
type vectorblock06 is array (05 downto 0) of std_logic_vector(width-1 downto 0);
type vectorblock02 is array (01 downto 0) of std_logic_vector(width-1 downto 0);
procOpcoder:
process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,aycy,bzdz,azcz,bydy,bxdx,axcx,opcode,addcode)
begin
case (addcode) is
-- Estamos ejecutando CxD
when '1'=>
aycy <= Cy;
bzdz <= Dz;
azcz <= Cz;
bydy <= Dy;
axcx <= Cx;
bxdx <= Dx;
when others =>
-- Estamos ejecutando AxB
aycy <= Ay;
bzdz <= Bz;
azcz <= Az;
bydy <= By;
axcx <= Ax;
bxdx <= Bx;
end case;
case (opcode) is
-- Estamos ejecutando Producto Cruz
when '1' =>
m0f0 <= aycy;
m0f1 <= bzdz;
m1f0 <= azcz;
m1f1 <= bydy;
m2f0 <= axcx;
m2f1 <= bzdz;
m3f0 <= azcz;
m3f1 <= bxdx;
m4f0 <= axcx;
m4f1 <= bydy;
m5f0 <= aycy;
m5f1 <= bxdx;
when others =>
-- Estamos ejecutando Producto Punto
m0f0 <= Ax;
m0f1 <= Bx;
m1f0 <= Ay;
m1f1 <= By;
m2f0 <= Az;
m2f1 <= Bz;
m3f0 <= Cx;
m3f1 <= Dx;
m4f0 <= Cy;
m4f1 <= Dy;
m5f0 <= Cz;
m5f1 <= Dz;
end case;
end process procOpcoder;
end generate originalMuxGen;
fastMuxGen:
if structuralDescription="YES" generate
mux0 : fastmux generic map (width) port map (ay,cy,addcode,aycy);
mux1 : fastmux generic map (width) port map (bz,dz,addcode,bzdz);
mux2 : fastmux generic map (width) port map (az,cz,addcode,azcz);
mux3 : fastmux generic map (width) port map (by,dy,addcode,bydy);
mux4 : fastmux generic map (width) port map (bx,dx,addcode,bxdx);
mux5 : fastmux generic map (width) port map (ax,cx,addcode,axcx);
-- Segunda etapa de multiplexores
muxa : fastmux generic map (width) port map (ax,aycy,opcode,m0f0);
muxb : fastmux generic map (width) port map (bx,bzdz,opcode,m0f1);
muxc : fastmux generic map (width) port map (ay,azcz,opcode,m1f0);
muxd : fastmux generic map (width) port map (by,bydy,opcode,m1f1);
muxe : fastmux generic map (width) port map (az,azcz,opcode,m2f0);
muxf : fastmux generic map (width) port map (bz,bxdx,opcode,m2f1);
muxg : fastmux generic map (width) port map (cx,axcx,opcode,m3f0);
muxh : fastmux generic map (width) port map (dx,bzdz,opcode,m3f1);
muxi : fastmux generic map (width) port map (cy,axcx,opcode,m4f0);
muxj : fastmux generic map (width) port map (dy,bydy,opcode,m4f1);
muxk : fastmux generic map (width) port map (cz,aycy,opcode,m5f0);
muxl : fastmux generic map (width) port map (dz,bxdx,opcode,m5f1);
signal sparaminput,sfactor,ssumando : vectorblock12;
signal sprd32blk,sadd32blk,sresult : vectorblock06;
signal ssqr32blk,sinv32blk : vectorblock02;
begin
end generate fastMuxGen;
--! Connect stuff ....
stuff12:
for i in 11 downto 0 generate
sparaminput(i) <= paraminput(i*width+width-1 downto i*width);
prd32blki(i*width+width-1 downto i*width) <= sfactor(i);
add32blki(i*width+width-1 downto i*width) <= ssumando(i);
end generate stuff12;
stuff06:
for i in 05 downto 0 generate
sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
resultoutput(i*width+width-1 downto i*width) <= sresult(i);
end generate stuff06;
stuff02:
for i in 05 downto 0 generate
ssqr32blk(i) <= sqr32blko(i*width+width-1 downto i*width);
sinv32blk(i) <= inv32blko(i*width+width-1 downto i*width);
end generate stuff02;
 
end opcoder_arch;
fifoconnection_proces:process(instr3)
begin
case (instr3) is
end process;
end dpc_arch;

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