OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /raytrac
    from Rev 141 to Rev 142
    ↔ Reverse comparison
  •

Rev 141 → Rev 142

/branches/fp/sm.vhd
28,62 → 28,77
 
 
entity sm is
generic (
width : integer := 32;
widthadmemblock : integer := 9
--!external_readable_widthad :
)
port (
clk,rst:in std_logic;
add0,add1:out std_logic_vector (8 downto 0);
iq:in std_logic_vector(31 downto 0);
read_memory,ird_ack:out std_logic;
ucsa:out std_logic(3 downto 0);
iempty , rfull, opq_empty : in std_logic;
adda,addb:out std_logic_vector (widthadmemblock-1 downto 0);
sync_chain_d:out std_logic;
--! Instruction Q, instruction.
instrQq:in std_logic_vector(width-1 downto 0);
--! apempty, arithmetical pipeline empty.
arithPbusy, instrQempty ,resultQfull: in std_logic;
--! DataPath Control uca code.
dpc_uca : out std_logic_vector (2 downto 0);
);
end entity;
 
architecture sm_arch of sm is
 
type macState is (IDLE,EXECUTING,FLUSHING);
type macState is (FLUSH_TO_NEXT_INSTRUCTION,EXECUTE_INSTRUCTION);
signal state : macState;
constant rstMasterValue : std_logic:='0';
component customCounter
generic (
width : integer
);
port (
clk,rst,go,set : in std_logic;
setValue : in std_Logic_vector(width-1 downto 0);
count : out std_logic_vector(width-1 downto 0)
)
signal addt0_blocka,addt0_blockb,set_Value_A,set_Value_B : std_logic_vector(widthadmemblock-1 downto 0);
signal add_condition_a, add_condition_b,set_a,set_b : std_logic;
signal s_dpc_uca, s_instrQ_uca : std_logic_vector(2 downto 0);
signal s_block_start_a, s_block_start_b, s_block_end_a, s_block_end_b : std_logic_vector(4 downto 0);
signal sadd0,sadd1:std_logic_vector (8 downto 0);
signal schunk0o,schunk0f,schunk1o,schunk1f: std_logic_vector (3 downto 0);
signal sadd0_now,sadd0_next,sadd0_reg:std_logic_vector(8 downto 0);
signal sadd1_now,sadd1_next,sadd1_reg:std_logic_vector(8 downto 0);
signal sadd0_adder_bit,sadd1_adder_bit,sena:std_logic;
 
begin
 
--! Bloques asignados
s_block_start_a <= instrQq(width-4 downto width-8);
s_block_start_b <= instrQq(width-14 downto width-18);
s_block_end_a <= instrQq(width-9 downto width-13);
s_block_end_b <= instrQq(width-19 downto width-)
--! Address Counters
counterA:customCounter
port map (clk,rst,add_condition_a,set_a,instrQq(width-4 downto width-8)&x"0",addt0_blocka);
counterB:customCounter
port map (clk,rst,add_condition_b,set_b,instrQq(width-9 downto width-12)&x"0",addt0_blockb);
adda <= addt0_blocka;
addb <= addt0_blockb;
schunk0o(3 downto 0) <= iq(19 downto 16);
schunk0f(3 downto 0) <= iq(15 downto 12);
schunk1o(3 downto 0) <= iq(11 downto 8);
schunk1f(3 downto 0) <= iq(7 downto 4);
--! uca code
s_instrQ_uca <= instrQq(31 downto 29);
ucsa <= iq(3 downto 0);
sadd0_next <= sadd0_now+sadd0_adder_bit;
sadd1_next <= sadd1_now+sadd1_adder_bit;
sm_comb:
process (state)
begin
case state is
when IDLE =>
sadd0_now <= schunk0o(3 downto 0)&x"0";
sadd1_now <= schunk1o(3 downto 0)&x"0";
when others =>
sadd0_now <= sadd0_next;
sadd1_now <= sadd1_next;
end case;
end process;
 
 
sm_proc:
process (clk,rst)
begin
90,31 → 105,34
if rst=rstMasterValue then
state <= IDLE;
ird_ack <= '0';
elsif clk='1' and clk'event and sena='1' then
elsif clk='1' and clk'event then
case state is
when IDLE =>
if rfull='0' and iempty='0' then
state <= EXECUTING;
read_memory <= '1';
end if;
when EXCUTING =>
if rfull='0' then
if sadd1_now=schunk1f&"11111" then
if sadd0_now=schunk0f&"11111" then
state <= FLUSHING;
end if;
end if;
end if;
when FLUSHING =>
if opq_empty='1' then
when FLUSH_TO_NEXT_INSTRUCTION =>
--! Chequear si hay una instruccion en la salida de la cola de instruccioens.
if instrQempty='0' then
--! Chequear si la cola de resultados tiene espacio.
if resultQfull='0' then
--! Si el codigo de instruccion (uca) que se encuentra en el DPC es igual al que se encuentra en la instruccion de la salida de la cola de instrucciones, entonces no hay mas validaciones que hacer.
--! Now check that arithmetic pipline is not busy
if arithPbusy='0' then
when EXECUTE_INSTRUCTION =>
if addt1_blockb(4 downto 0)=x"1f" and addt1_blocka=x"1f" then
if addt1_blockb(8 downto )
else
end if;
end case;
end if;
end process;
 
 
nxtadda_proc:
process ()
end architecture;
/branches/fp/dpc.vhd
29,7 → 29,7
--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
);
port (
clk,ena,rst : in std_logic;
clk,rst : in std_logic;
paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
37,7 → 37,7
fifo32x23_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
scalar : in std_logic;
sync_chain_d : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalizaci&oacute;n.
fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
80,51 → 80,52
signal sdpfifo_q : vectorblock02;
signal ssqr32blk,sinv32blk : std_logic_vector(width-1 downto 0);
signal sync_chain : std_logic_vector(27 downto 0);
signal sync_chain_d : std_logic;
signal ssync_chain : std_logic_vector(28 downto 0);
signal ssync_chain_d : std_logic;
constant rstMasterValue : std_logic := '0';
begin
--! Cadena de sincronizaci&oacute;n: 28 posiciones.
--! Cadena de sincronizaci&oacute;n: 29 posiciones.
ssync_chain_d <= sync_chain_d;
sync_chain_proc:
process(clk,rst)
begin
if rst=rstMasterValue then
sync_chain <= (others => '0');
ssync_chain <= (others => '0');
elsif clk'event and clk='1' then
sync_chain(0) <= sync_chain_d;
for i in 27 downto 1 loop
sync_chain(i) <= sync_chain(i-1);
ssync_chain(0) <= ssync_chain_d;
for i in 28 downto 1 loop
ssync_chain(i) <= ssync_chain(i-1);
end loop;
end if;
end process sync_chain_proc;
--! Escritura en las colas de resultados y escritura/lectura en las colas intermedias mediante cadena de resultados.
fifo32x09_w <= sync_chain(4);
fifo32x23_w <= sync_chain(0);
fifo32x09_r <= sync_chain();
fifo32x23_r <= sync_chain();
fifo32x09_w <= ssync_chain(4);
fifo32x23_w <= ssync_chain(0);
fifo32x09_r <= ssync_chain(12);
fifo32x23_r <= ssync_chain(23);
res0w <= sync_chain(22);
res4w <= sync_chain(20);
res0w <= ssync_chain(22);
res4w <= ssync_chain(20);
sync_chain_comb:
process (sync_chain,addsub,crossprod)
process (ssync_chain,addsub,crossprod,unary)
begin
if unary='1' then
res567w <= sync_chain(27);
res567w <= ssync_chain(27);
else
res567w <= sync_chain(3);
res567w <= ssync_chain(3);
end if;
if addsub='1' then
res13w <= sync_chain(8);
res2w <= sync_chain(8);
res13w <= ssync_chain(8);
res2w <= ssync_chain(8);
else
res13w <= sync_chain(12);
res13w <= ssync_chain(12);
if crossprod='1' then
res2w <= res13w;
res2w <= ssync_chain(12);
else
res2w <= sync_chain(21);
res2w <= ssync_chain(21);
end if;
end if;
end process sync_chain_comb;
214,10 → 215,10
ssumando(s7) <= sdpfifo_q(dpfifocd);
mul:process(unary,addsub,crossprod,scalar,sparaminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,snormfifo_q)
mul:process(unary,addsub,crossprod,sparaminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,snormfifo_q)
begin
sfactor(f4) <= sparaminput(az);
if unary='1' then
--! Magnitud y normalizacion
sfactor(f0) <= sparaminput(ax);
224,47 → 225,62
sfactor(f1) <= sparaminput(ax);
sfactor(f2) <= sparaminput(ay);
sfactor(f3) <= sparaminput(ay);
sfactor(f4) <= sparaminput(az);
sfactor(f5) <= sparaminput(az);
sfactor(f6) <= snormfifo_q(ax);
sfactor(f7) <= sinv32blk;
sfactor(f8) <= snormfifo_q(ay);
sfactor(f9) <= sinv32blk;
sfactor(f10) <= snormfifo_q(az);
sfactor(f11) <= sinv32blk;
elsif crossprod='1' then
--! Solo productos punto
sfactor(f0) <= sparaminput(ay);
sfactor(f1) <= sparaminput(bz);
sfactor(f2) <= sparaminput(az);
sfactor(f3) <= sparaminput(by);
sfactor(f4) <= sparaminput(az);
sfactor(f5) <= sparaminput(bx);
sfactor(f6) <= sparaminput(ax);
sfactor(f7) <= sparaminput(bz);
sfactor(f8) <= sparaminput(ax);
sfactor(f9) <= sparaminput(by);
sfactor(f10) <= sparaminput(ay);
sfactor(f11) <= sparaminput(bx);
elsif scalar='0' then --! Producto punto
sfactor(f0) <= sparaminput(ax) ;
sfactor(f1) <= sparaminput(bx) ;
sfactor(f2) <= sparaminput(ay) ;
sfactor(f3) <= sparaminput(by) ;
sfactor(f4) <= sparaminput(az) ;
sfactor(f5) <= sparaminput(bz) ;
sfactor(f6) <= sparaminput(cx) ;
sfactor(f7) <= sparaminput(dx) ;
sfactor(f8) <= sparaminput(cy) ;
sfactor(f9) <= sparaminput(dy) ;
sfactor(f10) <= sparaminput(cz) ;
sfactor(f11) <= sparaminput(dz) ;
if crossprod='1' and addsub='1' then
sfactor(f6) <= sparaminput(cx);
sfactor(f7) <= sparaminput(dx);
sfactor(f8) <= sparaminput(cy);
sfactor(f9) <= sparaminput(dx);
sfactor(f10) <= sparaminput(cz);
sfactor(f11) <= sparaminput(dx);
else
sfactor(f6) <= snormfifo_q(ax);
sfactor(f7) <= sinv32blk;
sfactor(f8) <= snormfifo_q(ay);
sfactor(f9) <= sinv32blk;
sfactor(f10) <= snormfifo_q(az);
sfactor(f11) <= sinv32blk;
end if;
elsif addsub='0' then
--! Solo productos punto o cruz
if crossprod='1' then
sfactor(f0) <= sparaminput(ay);
sfactor(f1) <= sparaminput(bz);
sfactor(f2) <= sparaminput(az);
sfactor(f3) <= sparaminput(by);
sfactor(f5) <= sparaminput(bx);
sfactor(f6) <= sparaminput(ax);
sfactor(f7) <= sparaminput(bz);
sfactor(f8) <= sparaminput(ax);
sfactor(f9) <= sparaminput(by);
sfactor(f10) <= sparaminput(ay);
sfactor(f11) <= sparaminput(bx);
else
sfactor(f0) <= sparaminput(ax) ;
sfactor(f1) <= sparaminput(bx) ;
sfactor(f2) <= sparaminput(ay) ;
sfactor(f3) <= sparaminput(by) ;
sfactor(f5) <= sparaminput(bz) ;
sfactor(f6) <= sparaminput(cx) ;
sfactor(f7) <= sparaminput(dx) ;
sfactor(f8) <= sparaminput(cy) ;
sfactor(f9) <= sparaminput(dy) ;
sfactor(f10) <= sparaminput(cz) ;
sfactor(f11) <= sparaminput(dz) ;
end if;
else
sfactor(f0) <= sparaminput(ax) ;
sfactor(f1) <= sparaminput(bx) ;
sfactor(f2) <= sparaminput(ay) ;
sfactor(f3) <= sparaminput(by) ;
sfactor(f4) <= sparaminput(az) ;
sfactor(f5) <= sparaminput(bz) ;
sfactor(f6) <= sparaminput(cx) ;
sfactor(f7) <= sparaminput(dx) ;
272,7 → 288,6
sfactor(f9) <= sparaminput(dx) ;
sfactor(f10) <= sparaminput(cz) ;
sfactor(f11) <= sparaminput(dx) ;
end if;
/branches/fp/customCounter.vhd
0,0 → 1,70
--! @file sm.vhd
--! @brief Maquina de Estados. Controla la operación interna y genera los mecanismos de sincronización con el exterior (interrupciones).
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- sm.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
entity customCounter is
generic (
width : integer := 9;
)
port (
clk,rst,go,set : in std_logic;
setValue : in std_logic_vector(width - 1 downto 0);
count : out std_logic_vector (width - 1 downto 0)
);
end entity;
 
 
 
architecture customCounter_arch of customCounter is
 
constant rstMasterValue : std_logic := '0';
signal scount_d, scount_q : std_logic_vector(width-1 downto 0);
 
begin
count <= scount_d;
add_proc:
process (scount_q,go,set,setValue)
begin
case set is
when '1' => scount_d <= setValue;
when others => scount_d <= scount_q+go;
end case;
end process;
count_proc:
process (clk,rst)
begin
if rst=rstMasterValue then
scount_q <= (others => '0');
elsif clk='1' and clk'event then
scount_q <= scount_d;
end if;
end process;
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.