URL
https://opencores.org/ocsvn/raytrac/raytrac/trunk
Subversion Repositories raytrac
Compare Revisions
- This comparison shows the changes necessary to convert path
/raytrac
- from Rev 177 to Rev 178
- ↔ Reverse comparison
Rev 177 → Rev 178
/branches/fp/raytrac_hw.tcl
0,0 → 1,160
# TCL File Generated by Component Editor 11.0 |
# Fri May 11 19:33:05 COT 2012 |
# DO NOT MODIFY |
|
|
# +----------------------------------- |
# | |
# | raytrac "raytrac" v1.0 |
# | null 2012.05.11.19:33:05 |
# | |
# | |
# | //IMACJULIAN/imac/Code/Indigo/fp/fp/raytrac.vhd |
# | |
# | ./raytrac.vhd syn |
# | ./arithpack.vhd syn |
# | ./meminvr.mif |
# | ./memsqrt.mif |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | request TCL package from ACDS 11.0 |
# | |
package require -exact sopc 11.0 |
# | |
# +----------------------------------- |
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# +----------------------------------- |
# | module raytrac |
# | |
set_module_property NAME raytrac |
set_module_property VERSION 1.0 |
set_module_property INTERNAL false |
set_module_property OPAQUE_ADDRESS_MAP true |
set_module_property DISPLAY_NAME raytrac |
set_module_property TOP_LEVEL_HDL_FILE raytrac.vhd |
set_module_property TOP_LEVEL_HDL_MODULE raytrac |
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true |
set_module_property EDITABLE true |
set_module_property ANALYZE_HDL TRUE |
set_module_property STATIC_TOP_LEVEL_MODULE_NAME "" |
set_module_property FIX_110_VIP_PATH false |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | files |
# | |
add_file raytrac.vhd SYNTHESIS |
add_file arithpack.vhd SYNTHESIS |
add_file meminvr.mif "" |
add_file memsqrt.mif "" |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | parameters |
# | |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | display items |
# | |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point clock |
# | |
add_interface clock clock end |
set_interface_property clock clockRate 0 |
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set_interface_property clock ENABLED true |
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add_interface_port clock clk clk Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point avalon_slave_0 |
# | |
add_interface avalon_slave_0 avalon end |
set_interface_property avalon_slave_0 addressAlignment DYNAMIC |
set_interface_property avalon_slave_0 addressUnits WORDS |
set_interface_property avalon_slave_0 associatedClock clock |
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false |
set_interface_property avalon_slave_0 explicitAddressSpan 0 |
set_interface_property avalon_slave_0 holdTime 0 |
set_interface_property avalon_slave_0 isMemoryDevice false |
set_interface_property avalon_slave_0 isNonVolatileStorage false |
set_interface_property avalon_slave_0 linewrapBursts false |
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 |
set_interface_property avalon_slave_0 printableDevice false |
set_interface_property avalon_slave_0 readLatency 0 |
set_interface_property avalon_slave_0 readWaitTime 1 |
set_interface_property avalon_slave_0 setupTime 0 |
set_interface_property avalon_slave_0 timingUnits Cycles |
set_interface_property avalon_slave_0 writeWaitTime 0 |
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set_interface_property avalon_slave_0 ENABLED true |
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add_interface_port avalon_slave_0 wr write Input 1 |
add_interface_port avalon_slave_0 q readdata Output 32 |
add_interface_port avalon_slave_0 rd read Input 1 |
add_interface_port avalon_slave_0 add address Input 13 |
add_interface_port avalon_slave_0 d writebyteenable_n Input 32 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point avalon_slave |
# | |
add_interface avalon_slave avalon end |
set_interface_property avalon_slave addressAlignment DYNAMIC |
set_interface_property avalon_slave addressUnits WORDS |
set_interface_property avalon_slave associatedClock clock |
set_interface_property avalon_slave burstOnBurstBoundariesOnly false |
set_interface_property avalon_slave explicitAddressSpan 0 |
set_interface_property avalon_slave holdTime 0 |
set_interface_property avalon_slave isMemoryDevice false |
set_interface_property avalon_slave isNonVolatileStorage false |
set_interface_property avalon_slave linewrapBursts false |
set_interface_property avalon_slave maximumPendingReadTransactions 0 |
set_interface_property avalon_slave printableDevice false |
set_interface_property avalon_slave readLatency 0 |
set_interface_property avalon_slave readWaitTime 1 |
set_interface_property avalon_slave setupTime 0 |
set_interface_property avalon_slave timingUnits Cycles |
set_interface_property avalon_slave writeWaitTime 0 |
|
set_interface_property avalon_slave ENABLED true |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point reset_sink |
# | |
add_interface reset_sink reset end |
set_interface_property reset_sink associatedClock clock |
set_interface_property reset_sink synchronousEdges DEASSERT |
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set_interface_property reset_sink ENABLED true |
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add_interface_port reset_sink rst reset Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point interrupt_sender |
# | |
add_interface interrupt_sender interrupt end |
set_interface_property interrupt_sender associatedAddressablePoint "" |
set_interface_property interrupt_sender associatedClock clock |
|
set_interface_property interrupt_sender ENABLED true |
|
add_interface_port interrupt_sender int irq Output 8 |
# | |
# +----------------------------------- |