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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /raytrac
    from Rev 178 to Rev 179
    ↔ Reverse comparison
  •

Rev 178 → Rev 179

/branches/fp/raytrac_hw.tcl
1,5 → 1,5
# TCL File Generated by Component Editor 11.0
# Fri May 11 19:33:05 COT 2012
# Sat May 26 10:44:07 COT 2012
# DO NOT MODIFY
 
 
6,15 → 6,27
# +-----------------------------------
# |
# | raytrac "raytrac" v1.0
# | null 2012.05.11.19:33:05
# | null 2012.05.26.10:44:07
# |
# |
# | //IMACJULIAN/imac/Code/Indigo/fp/fp/raytrac.vhd
# |
# | ./arithblock.vhd syn
# | ./arithpack.vhd syn
# | ./customCounter.vhd syn
# | ./dpc.vhd syn
# | ./fadd32.vhd syn
# | ./fmul32.vhd syn
# | ./im.vhd syn
# | ./invr32.vhd syn
# | ./memblock.vhd syn
# | ./meminvr.mif syn
# | ./memsqrt.mif syn
# | ./mulblock.vhd syn
# | ./raytrac.vhd syn
# | ./arithpack.vhd syn
# | ./meminvr.mif
# | ./memsqrt.mif
# | ./raytrac_hw.tcl
# | ./sm.vhd syn, sim
# | ./sqrt32.vhd syn, sim
# |
# +-----------------------------------
 
46,10 → 58,22
# +-----------------------------------
# | files
# |
add_file arithblock.vhd SYNTHESIS
add_file arithpack.vhd SYNTHESIS
add_file customCounter.vhd SYNTHESIS
add_file dpc.vhd SYNTHESIS
add_file fadd32.vhd SYNTHESIS
add_file fmul32.vhd SYNTHESIS
add_file im.vhd SYNTHESIS
add_file invr32.vhd SYNTHESIS
add_file memblock.vhd SYNTHESIS
add_file meminvr.mif SYNTHESIS
add_file memsqrt.mif SYNTHESIS
add_file mulblock.vhd SYNTHESIS
add_file raytrac.vhd SYNTHESIS
add_file arithpack.vhd SYNTHESIS
add_file meminvr.mif ""
add_file memsqrt.mif ""
add_file raytrac_hw.tcl ""
add_file sm.vhd {SYNTHESIS SIMULATION}
add_file sqrt32.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
 
69,7 → 93,7
# | connection point clock
# |
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock clockRate 50000000
 
set_interface_property clock ENABLED true
 
84,6 → 108,7
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset_sink
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
101,39 → 126,14
set_interface_property avalon_slave_0 ENABLED true
 
add_interface_port avalon_slave_0 wr write Input 1
add_interface_port avalon_slave_0 add address Input 13
add_interface_port avalon_slave_0 q readdata Output 32
add_interface_port avalon_slave_0 rd read Input 1
add_interface_port avalon_slave_0 add address Input 13
add_interface_port avalon_slave_0 d writebyteenable_n Input 32
add_interface_port avalon_slave_0 d writedata Input 32
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point avalon_slave
# |
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressAlignment DYNAMIC
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave isMemoryDevice false
set_interface_property avalon_slave isNonVolatileStorage false
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave printableDevice false
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitTime 1
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
 
set_interface_property avalon_slave ENABLED true
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point reset_sink
# |
add_interface reset_sink reset end
147,14 → 147,113
# +-----------------------------------
 
# +-----------------------------------
# | connection point interrupt_sender
# | connection point is06
# |
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint ""
set_interface_property interrupt_sender associatedClock clock
add_interface is06 interrupt end
set_interface_property is06 associatedAddressablePoint avalon_slave_0
set_interface_property is06 associatedClock clock
set_interface_property is06 associatedReset reset_sink
 
set_interface_property interrupt_sender ENABLED true
set_interface_property is06 ENABLED true
 
add_interface_port interrupt_sender int irq Output 8
add_interface_port is06 int06 irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point is04
# |
add_interface is04 interrupt end
set_interface_property is04 associatedAddressablePoint avalon_slave_0
set_interface_property is04 associatedClock clock
set_interface_property is04 associatedReset reset_sink
 
set_interface_property is04 ENABLED true
 
add_interface_port is04 int04 irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point is03
# |
add_interface is03 interrupt end
set_interface_property is03 associatedAddressablePoint avalon_slave_0
set_interface_property is03 associatedClock clock
set_interface_property is03 associatedReset reset_sink
 
set_interface_property is03 ENABLED true
 
add_interface_port is03 int03 irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point is02
# |
add_interface is02 interrupt end
set_interface_property is02 associatedAddressablePoint avalon_slave_0
set_interface_property is02 associatedClock clock
set_interface_property is02 associatedReset reset_sink
 
set_interface_property is02 ENABLED true
 
add_interface_port is02 int02 irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point is01
# |
add_interface is01 interrupt end
set_interface_property is01 associatedAddressablePoint avalon_slave_0
set_interface_property is01 associatedClock clock
set_interface_property is01 associatedReset reset_sink
 
set_interface_property is01 ENABLED true
 
add_interface_port is01 int01 irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point is00
# |
add_interface is00 interrupt end
set_interface_property is00 associatedAddressablePoint avalon_slave_0
set_interface_property is00 associatedClock clock
set_interface_property is00 associatedReset reset_sink
 
set_interface_property is00 ENABLED true
 
add_interface_port is00 int00 irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point is07
# |
add_interface is07 interrupt end
set_interface_property is07 associatedAddressablePoint avalon_slave_0
set_interface_property is07 associatedClock clock
set_interface_property is07 associatedReset reset_sink
 
set_interface_property is07 ENABLED true
 
add_interface_port is07 int07 irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point is05
# |
add_interface is05 interrupt end
set_interface_property is05 associatedAddressablePoint avalon_slave_0
set_interface_property is05 associatedClock clock
set_interface_property is05 associatedReset reset_sink
 
set_interface_property is05 ENABLED true
 
add_interface_port is05 int05 irq Output 1
# |
# +-----------------------------------
/branches/fp/dpc.vhd
249,6 → 249,7
ssumando(s7) <= sdpfifo_q(dpfifocd);
--!El siguiente proceso conecta la se&ntilde;al de cola "casi llena", de la cola que corresponde al resultado de la operaci&oacute;n indicada por los bit UCA (Unary, Crossprod, Addsub).
--!Adicionalmente codifca en formato one HOT la cola de la instruccion en la que se escriben los resultados de la ultima instrucci&oacute;n que haya finalizado.
sres0f <= resf_vector(0);
sres123f <= resf_vector(1);
sres24f <= resf_vector(2);
256,18 → 257,15
fullQ:process(sres0f,sres123f,sres24f,sres567f,unary,crossprod,addsub,eoi_int)
begin
if unary='0' then
if addsub='1' then
--! Suma o Resta
 
if addsub='1' or crossprod='1' then
--! Suma o Resta o producto cruz, comparten la misma cola de resultados.
eoi_demuxed_int <= "00"&eoi_int&'0';
resf_event <= sres123f;
elsif crossprod='0' then
--! Producto Punto
else
--! Producto Punto utiliza como salida las colas 2 y 4
eoi_demuxed_int <= '0'&eoi_int&"00";
resf_event <= sres24f;
else
--! Producto Cruz
eoi_demuxed_int <= "00"&eoi_int&'0';
resf_event <= sres123f;
end if;
elsif crossprod='1' then

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