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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /raytrac
    from Rev 229 to Rev 230
    ↔ Reverse comparison
  •

Rev 229 → Rev 230

/branches/fp_sgdma/arithblock.vhd
58,7 → 58,6
a0 : out std_logic_vector(31 downto 0);
a1 : out std_logic_vector(31 downto 0);
a2 : out std_logic_vector(31 downto 0);
a3 : out std_logic_vector(31 downto 0);
--add32blko : out vectorblock03;
p0 : out std_logic_vector(31 downto 0);
152,14 → 151,6
b32 => sumando5,
c32 => a2
);
adder_i_3 : fadd32long
port map (
clk => clk,
dpc => sign,
a32 => sumando4,
b32 => sumando5,
c32 => a3
);
--!TBXINSTANCESTART
mul_i_0 : fmul32
port map (
/branches/fp_sgdma/ap_n_dpc.vhd
32,15 → 32,10
entity ap_n_dpc is
port (
sumando5 : out std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
dx : out std_logic_vector(31 downto 0);
dy : out std_logic_vector(31 downto 0);
dz : out std_logic_vector(31 downto 0);
dsc : out std_logic_vector(31 downto 0);
ax : in std_logic_vector(31 downto 0);
ay : in std_logic_vector(31 downto 0);
az : in std_logic_vector(31 downto 0);
117,7 → 112,7
signal sa0 : std_logic_vector(31 downto 0);
signal sa1 : std_logic_vector(31 downto 0);
signal sa2 : std_logic_vector(31 downto 0);
signal sa3 : std_logic_vector(31 downto 0);
constant adder2_delay: integer := 2;
--signal sadd32blk : vectorblock03;
158,7 → 153,6
signal sa0o : std_logic_vector(31 downto 0);
signal sa1o : std_logic_vector(31 downto 0);
signal sa2o : std_logic_vector(31 downto 0);
signal sa3o : std_logic_vector(31 downto 0);
--signal sadd32blko : vectorblock03; --! Salidas de los 3 sumadores.
signal sp0o : std_logic_vector(31 downto 0);
206,7 → 200,6
a0 : out std_logic_vector(31 downto 0);
a1 : out std_logic_vector(31 downto 0);
a2 : out std_logic_vector(31 downto 0);
a3 : out std_logic_vector(31 downto 0);
--add32blko : out vectorblock03;
p0 : out std_logic_vector(31 downto 0);
224,8 → 217,6
end component;
begin
--! Debug
sumando5 <= sa2o;
 
--! Bloque Aritm&eacute;tico
ap : arithblock
260,7 → 251,6
a0=>sa0o,
a1=>sa1o,
a2=>sa2o,
a3=>sa3o,
--add32blko => sadd32blko,
p0=>sp0o,
283,20 → 273,8
begin
if rst=rstMasterValue then
ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
dx <= (others => '0');
dy <= (others => '0');
dz <= (others => '0');
dsc <= (others => '0');
 
elsif clk'event and clk='1' then
if sqr_w='1' then
dx <= ssumando4;
dy <= ssumando5;
dz <= sa3;
dsc <= sqr_dsc;
end if;
for i in ssync_chain_max downto ssync_chain_min+1 loop
ssync_chain(i) <= ssync_chain(i-1);
end loop;
322,7 → 300,6
sa0 <= sa0o;
sa1 <= sa1o;
sa2 <= sa2o;
sa3 <= sa3o;
sinv32 <= sinv32o;
ssq32 <= ssq32o;
end if;
362,7 → 339,7
sqr_dy <= sa1;
sqr_dz <= sa2;
sqr_w <= ssync_chain(13);
sqr_w <= ssync_chain(13+adder2_delay);
when"000"|"001" =>
 
394,7 → 371,7
sqr_dy <= sa1;
sqr_dz <= sa2;
sqr_w <= ssync_chain(9);
sqr_w <= ssync_chain(9+adder2_delay);
when"110" |"100" =>
/branches/fp_sgdma/fadd32long.vhd
38,11 → 38,11
c32 : out std_logic_vector(31 downto 0)
);
end entity;
architecture fadd32_arch of fadd32long is
architecture fadd32long_arch of fadd32long is
--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
--attribute altera_attribute : string;
--attribute altera_attribute of fadd32_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
attribute altera_attribute : string;
attribute altera_attribute of fadd32long_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
--!TBXSTART:STAGE0
signal s0delta : std_logic_vector(8 downto 0);
/branches/fp_sgdma/raytrac.vhd
74,13 → 74,10
 
architecture raytrac_arch of raytrac is
 
--! Debug
signal ssumando5 : xfloat32;
signal sphantom_q: std_logic_vector(31 downto 0);
 
--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
--attribute altera_attribute : string;
--attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
attribute altera_attribute : string;
attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
 
type registerblock is array (15 downto 0) of xfloat32;
151,7 → 148,7
--! State Machine and event signaling
signal sm : transferState;
signal sr_e : std_logic;
signal sr_e : std_logic;
signal sr_ack : std_logic;
signal soutb_ack : std_logic;
201,16 → 198,8
--! Arithmetic Pipeline and Data Path Control
component ap_n_dpc
port (
sumando5 : out xfloat32;
clk : in std_logic;
rst : in std_logic;
dx : out std_logic_vector(31 downto 0);
dy : out std_logic_vector(31 downto 0);
dz : out std_logic_vector(31 downto 0);
dsc : out std_logic_vector(31 downto 0);
ax : in std_logic_vector(31 downto 0);
ay : in std_logic_vector(31 downto 0);
az : in std_logic_vector(31 downto 0);
223,22 → 212,14
sc : out std_logic_vector(31 downto 0);
ack : in std_logic;
empty : out std_logic;
--paraminput : in vectorblock06; --! Vectores A,B
dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_1 : in std_logic; --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
pipeline_pending : out std_logic --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.
--qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
);
end component;
--! Nets para la salida de la cola de resultados y entrada del multiplexor del upload state machine.
signal svx,svy,svz,ssc : std_logic_vector(31 downto 0);
signal sdx,sdy,sdz,sdsc : std_logic_vector(31 downto 0);
begin
 
253,14 → 234,8
--! Arithpipeline and Datapath Control Instance
arithmetic_pipeline_and_datapath_controller : ap_n_dpc
port map (
sumando5 => ssumando5,
 
clk => clk,
rst => rst,
dx => sdx,
dy => sdy,
dz => sdz,
dsc => sdsc,
ax => sreg_block(reg_ax),
ay => sreg_block(reg_ay),
az => sreg_block(reg_az),
745,32 → 720,8
sslave_read <= slave_read;
sslave_writedata <= slave_writedata;
if soutb_w='1' and supload_chain=DMA then
sreg_block(reg_vx) <= sdx;
else
sreg_block(reg_vx) <= sdx;
end if;
if soutb_w='1' and supload_chain=DMA then
sreg_block(reg_vy) <= sdy;
else
sreg_block(reg_vy) <= sdy;
end if;
if soutb_w='1' and supload_chain=DMA then
sreg_block(reg_scratch00) <= sdz;
sreg_block(reg_vz) <= sdz;
else
sreg_block(reg_scratch00) <= sdz;
sreg_block(reg_vz) <= sdz;
end if;
if soutb_w='1' and supload_chain=DMA then
sreg_block(reg_scalar) <= sdsc;
else
sreg_block(reg_scalar) <= sdsc;
end if;
for i in reg_scratch00-5 downto reg_vz loop
for i in reg_scratch00 downto reg_vz loop
if sslave_address=i then
if sslave_write='1' then
sreg_block(i) <= sslave_writedata;

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