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URL https://opencores.org/ocsvn/rf68000/rf68000/trunk

Subversion Repositories rf68000

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    /rf68000/trunk/rtl
    from Rev 2 to Rev 3
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Rev 2 → Rev 3

/cpu/io_bitmap.sv
148,7 → 148,7
.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence
// on the data output of port B.
 
.addra({asid_i[5:0],adr_i[ 8: 2]}), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
.addra(adr_i[14: 2]), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
.addrb({asid_i[5:0],adr_i[19:13]}), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
.clka(clk_i), // 1-bit input: Clock signal for port A. Also clocks port B when
// parameter CLOCKING_MODE is "common_clock".
220,7 → 220,7
else
dat_o <= 32'd0;
 
always_comb
gate_o <= doutb[adr_i[12:8]];
always_ff @(posedge clk_i)
gate_o <= doutb[adr_i[12:8]] & enb;
endmodule
/cpu/rf68000.sv
48,6 → 48,8
//`define SUPPORT_010 1'b1
`define SUPPORT_BITPAIRS 1'b1
 
//`define HAS_MMU 1'b1
 
//`define SUPPORT_TASK 1'b1
 
//`define SUPPORT_B24 1'b1 // To support 23-bit branch displacements
93,6 → 95,7
`define STH 16'b0010_xxx1xx_xxxxxx
`define STW 16'b0011_xxx1xx_xxxxxx
 
// DBcc also for Scc
`define DBRA 8'h50
`define DBSR 8'h51
`define DBHI 8'h52
472,6 → 475,14
reg [31:0] a5 = 'd0;
reg [31:0] a6 = 'd0;
reg [31:0] sp = 'd0;
reg [127:0] fp0 = 'd0;
reg [127:0] fp1 = 'd0;
reg [127:0] fp2 = 'd0;
reg [127:0] fp3 = 'd0;
reg [127:0] fp4 = 'd0;
reg [127:0] fp5 = 'd0;
reg [127:0] fp6 = 'd0;
reg [127:0] fp7 = 'd0;
reg [31:0] d0i;
reg [31:0] d1i;
reg [31:0] d2i;
639,6 → 650,7
//wire [31:0] rfoRnn = rrrr==4'b1111 ? sp : regfile[rrrr];
wire clk_g;
reg rfwrL,rfwrB,rfwrW;
reg rfwrFp;
reg takb;
reg [8:0] resB;
reg [16:0] resW;
680,9 → 692,9
reg [31:0] tr;
reg [31:0] tcba;
reg [31:0] mmus, ios, iops;
assign mmus_o = adr_o[31:2] >= mmus[31:2] && adr_o[31:2] < mmus[31:2]+10'd512;
assign iops_o = adr_o[31:2] >= iops[31:2] && adr_o[31:2] < iops[31:2]+8'd128;
assign ios_o = adr_o[31:2] >= ios [31:2] && adr_o[31:2] < ios [31:2]+24'h100000;
assign mmus_o = adr_o[31:20] == mmus[31:20];
assign iops_o = adr_o[31:16] == iops[31:16];
assign ios_o = adr_o[31:20] == ios [31:20];
 
wire [16:0] lfsr_o;
lfsr17 ulfsr1
1555,6 → 1567,7
stb_o <= 1'b1;
sel_o <= 4'b1111;
adr_o <= pc;
goto (IFETCH);
end
end
else if (ack_i) begin
1575,6 → 1588,7
stb_o <= 1'b1;
sel_o <= 4'b1111;
adr_o <= pc;
goto (IFETCH2);
end
else if (ack_i) begin
cyc_o <= 1'b0;
1924,13 → 1938,13
//-----------------------------------------------------------------------------
5'h5:
begin
casez(ir[7:4])
casez(ir[7:3])
// When optimizing DBRA for performance, the memory access cycle to fetch
// the displacement constant is not done, instead the PC is incremented by
// two if not doing the DBRA. This is an extra PC increment that increases
// the code size. It is slower, but more hardware efficient to just always
// fetch the displacement.
4'b1100: // DBRA
5'b11001: // DBRA
`ifdef OPT_PERF
if (~takb) begin
call(FETCH_IMM16,DBRA);
1942,7 → 1956,7
`else
call(FETCH_IMM16,DBRA);
`endif
4'b11??: // Scc
5'b11???: // Scc
begin
resL <= {32{takb}};
resW <= {16{takb}};
5391,14 → 5405,14
case(imm[11:0])
12'h000: begin sfc <= rfoRnn; ret(); end
12'h001: begin dfc <= rfoRnn; ret(); end
12'h003: begin asid <= rfoDnn[7:0]; ret(); end
12'h010: begin apc <= rfoDnn; ret(); end
12'h011: begin cpl <= rfoDnn[7:0]; ret(); end
12'h012: begin tr <= rfoDnn; ret(); end
12'h013: begin tcba <= rfoDnn; ret(); end
12'h014: begin mmus <= rfoDnn; ret(); end
12'h015: begin ios <= rfoDnn; ret(); end
12'h016: begin iops <= rfoDnn; ret(); end
12'h003: begin asid <= rfoRnn[7:0]; ret(); end
12'h010: begin apc <= rfoRnn; ret(); end
12'h011: begin cpl <= rfoRnn[7:0]; ret(); end
12'h012: begin tr <= rfoRnn; ret(); end
12'h013: begin tcba <= rfoRnn; ret(); end
12'h014: begin mmus <= rfoRnn; ret(); end
12'h015: begin ios <= rfoRnn; ret(); end
12'h016: begin iops <= rfoRnn; ret(); end
12'h800: begin usp <= rfoRnn; ret(); end
12'h801: begin vbr <= rfoRnn; ret(); end
/*
/cpu/rf68000_mmu.sv
247,6 → 247,8
pea_o[15: 0] <= s_adr_i[15:0];
pea_o[31:16] <= doutb[15:0];
pdat_o <= s_dat_i;
if (s_cs_i)
pea_o <= 'd0;
if (cs) begin
cyc_o <= 1'b0;
stb_o <= 1'b0;

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