OpenCores
URL https://opencores.org/ocsvn/riscompatible/riscompatible/trunk

Subversion Repositories riscompatible

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  • This comparison shows the changes necessary to convert path
    /riscompatible/trunk
    from Rev 1 to Rev 2
    Reverse comparison

Rev 1 → Rev 2

/bench/riscompatible_tb.vhd
0,0 → 1,99
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
entity riscompatible_tb is
end riscompatible_tb;
-------------------------------------------------------------------------------------------------------------------
architecture behavioral of riscompatible_tb is
constant C_NumBitsProgramMemory : Natural:=14;
constant C_NumBitsDataMemory : Natural:=7;
constant C_NumBitsRegBank : natural:=5;
constant C_NumBitsInputPorts : natural:=2;
constant C_NumBitsOutputPorts : natural:=2;
component riscompatible is
generic
(
NumBitsProgramMemory : Natural:=5;
NumBitsDataMemory : Natural:=5;
NumBitsRegBank : natural:=5;
NumBitsInputPorts : natural:=2;
NumBitsOutputPorts : natural:=2
);
port
(
Clk_I : in std_logic;
Reset_I : in std_logic;
Int_I : in std_logic;
IntAck_O : out std_logic;
InputPorts_I : in std_logic_vector(NumBitsInputPorts-1 downto 0);
OutputPorts_O : out std_logic_vector(NumBitsOutputPorts-1 downto 0)
);
end component;
signal Clk_W : std_logic;
signal Reset_W : std_logic;
signal Int_W : std_logic;
signal IntAck_W : std_logic;
signal InputPorts_W : std_logic_vector(C_NumBitsInputPorts-1 downto 0):="10";
signal OutputPorts_W : std_logic_vector(C_NumBitsOutputPorts-1 downto 0);
begin
---------------------------------------------
-- Clock Generation
---------------------------------------------
process
begin
Clk_W <= '1';
wait for 10 ns;
Clk_W <= '0';
wait for 10 ns;
end process;
 
---------------------------------------------
-- Reset Generation
---------------------------------------------
process
begin
Reset_W <= '1';
wait for 20 ns;
Reset_W <= '0';
wait;
end process;
 
---------------------------------------------
-- Interruption Generation
---------------------------------------------
process
begin
Int_W <= '0';
wait for 1 us;
Int_W <= '1';
wait for 500 ns;
Int_W <= '0';
wait;
end process;
---------------------------------------------
-- Risco Instance
---------------------------------------------
Riscompatible1: riscompatible
generic map
(
NumBitsProgramMemory => C_NumBitsProgramMemory,
NumBitsDataMemory => C_NumBitsDataMemory,
NumBitsRegBank => C_NumBitsRegBank,
NumBitsInputPorts => C_NumBitsInputPorts,
NumBitsOutputPorts => C_NumBitsOutputPorts
)
port map
(
Clk_I => Clk_W,
Reset_I => Reset_W,
Int_I => Int_W,
IntAck_O => IntAck_W,
InputPorts_I => InputPorts_W,
OutputPorts_O => OutputPorts_W
);
end behavioral;
/bench/program.txt
0,0 → 1,15376
1c021900
013c081e
0104080a
29062801
010820c0
0b0a20c0
0b0c3080
a006480a
8004480a
aa064140
aa064140
a8063140
a8063140
ae083140
ae083140
8a0e4140
8a0e4140
880e4140
880e4140
8e103140
8e103140
703e0801
d0081080
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8e020780
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1c021900
8a3e0780
/bench/data.txt
0,0 → 1,24
00010203
04050607
08090A0B
10010203
14050607
18090A0B
20010203
24050607
28090A0B
30010203
34050607
38090A0B
40010203
44050607
48090A0B
50010203
54050607
58090A0B
60010203
64050607
68090A0B
70010203
74050607
78090A0B
/rtl/registerbank.vhd
0,0 → 1,47
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
entity RegisterBank is
generic
(
NumBitsAddr : natural:=4;
DataWidth : natural:=32
);
port
(
Clk_I : in std_logic;
Enable_I : in std_logic;
Write_I : in std_logic;
RegisterW_I : in std_logic_vector(NumBitsAddr-1 downto 0);
Register1_I : in std_logic_vector(NumBitsAddr-1 downto 0);
Register2_I : in std_logic_vector(NumBitsAddr-1 downto 0);
InputData_I : in std_logic_vector(DataWidth-1 downto 0);
FT1OutputData_O : out std_logic_vector(DataWidth-1 downto 0);
FT2OutputData_O : out std_logic_vector(DataWidth-1 downto 0)
);
end RegisterBank;
-------------------------------------------------------------------------------------------------------------------
architecture behavioral of RegisterBank is
type TMemory is array (natural range <> ) of TRiscoWord;
signal Memory : TMemory (2**NumBitsAddr-1 downto 0):=(others=>(others=>'0'));
begin
 
process (Clk_I,Enable_I,Write_I,RegisterW_I,Register1_I,Register2_I,InputData_I,Memory)
begin
if rising_edge(Clk_I) then
if (Enable_I = '1') then
if (Write_I = '1') then
if to_integer(unsigned(RegisterW_I))/=0 then -- Never write to R00!
Memory(to_integer(unsigned(RegisterW_I))) <= InputData_I;
end if;
end if;
end if;
end if;
FT1OutputData_O <= Memory(to_integer(unsigned(Register1_I)));
FT2OutputData_O <= Memory(to_integer(unsigned(Register2_I)));
end process;
end behavioral;
-------------------------------------------------------------------------------------------------------------------
/rtl/select_and_control.vhd
0,0 → 1,656
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
entity select_and_control is
generic
(
NumBitsProgramMemory : natural:=5;
NumBitsDataMemory : natural:=5;
NumBitsRegBank : natural:=5
);
port
(
Clk_I : in std_logic;
Reset_I : in std_logic;
PMem_Enable_O : out std_logic;
PMem_Address_O : out std_logic_vector(NumBitsProgramMemory-1 downto 0);
PMem_Write_O : out std_logic;
PMem_OutputData_I : in TRiscoWord;
DMem_Enable_O : out std_logic;
DMem_Write_O : out std_logic;
DMem_Address_O : out std_logic_vector(NumBitsDataMemory-1 downto 0);
DMem_InputData_O : out TRiscoWord;
DMem_OutputData_I : in TRiscoWord;
RegBnk_Register1_O : out std_logic_vector(NumBitsRegBank - 1 downto 0);
RegBnk_Register2_O : out std_logic_vector(NumBitsRegBank - 1 downto 0);
RegBnk_RegisterW_O : out std_logic_vector(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O : out std_logic;
RegBnk_InputData_O : out TRiscoWord;
RegBnk_FT1_OutputData_I : in TRiscoWord;
RegBnk_FT2_OutputData_I : in TRiscoWord;
ULA_Function_O : out std_logic_vector(4 downto 0);
ULA_Output_I : in TRiscoWord;
ULA_Ng_O_I : in std_logic; -- Negative
ULA_Cy_O_I : in std_logic; -- Carry
ULA_Ov_O_I : in std_logic; -- Overflow
ULA_Zr_O_I : in std_logic; -- Zero
UD_Function_O : out std_logic_vector(4 downto 0);
UD_OutputData_I : in TRiscoWord;
UD_Cy_O_I : in std_logic;
RUA_Clr_O : out std_logic;
RUB_Clr_O : out std_logic;
RDA_Clr_O : out std_logic;
RDB_Clr_O : out std_logic;
RUA_Wen_O : out std_logic;
RUB_Wen_O : out std_logic;
RDA_Wen_O : out std_logic;
RDB_Wen_O : out std_logic;
RUA_Data_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
RUB_Data_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
RDA_Data_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
RDB_Data_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
PC_Clr_O : out std_logic;
PC_Wen_O : out std_logic;
PC_Data_I : in std_logic_vector(C_NumBitsWord-1 downto 0);
PC_Data_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
PSW_Clr_O : out std_logic;
PSW_Wen_O : out std_logic;
PSW_Data_I : in std_logic_vector(C_NumBitsWord-1 downto 0);
PSW_Data_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
Int_I : in std_logic;
IntAck_O : out std_logic
);
end select_and_control;
-------------------------------------------------------------------------------------------------------------------
architecture Ark1 of select_and_control is
---------------------------------------------
-- Special Registers
---------------------------------------------
constant C_R00 : integer range 0 to 31:=0;
constant C_PSW : integer range 0 to 31:=1;
constant C_PC : integer range 0 to 31:=2**NumBitsRegBank - 1;
constant C_SPISR : integer range 0 to 31:=C_PC - 1; -- SP of the Interrupt Service Routine
---------------------------------------------
alias InterruptEnable_w : std_logic is PSW_Data_I(8);
---------------------------------------------
signal DMem_Address_W : std_logic_vector(NumBitsDataMemory-1 downto 0);
---------------------------------------------
procedure p_DecomposeInstructionIntoFields
(
PMemOutputData_I : in TRiscoWord;
T1_T0_O : out std_logic_vector(1 downto 0);
C4_C0_O : out std_logic_vector(4 downto 0);
F1_F0_SS2_O : out std_logic_vector(2 downto 0);
APS_O : out std_logic;
DST_O : out std_logic_vector(4 downto 0);
FT1_O : out std_logic_vector(4 downto 0);
FT2_O : out std_logic_vector(4 downto 0);
Kp_O : out std_logic_vector(10 downto 0);
Kg_O : out std_logic_vector(16 downto 0)
) is
begin
T1_T0_O := PMemOutputData_I(31 downto 30);
C4_C0_O := PMemOutputData_I(29 downto 25);
APS_O := PMemOutputData_I(24);
F1_F0_SS2_O := PMemOutputData_I(23 downto 22)&PMemOutputData_I(11);
DST_O := PMemOutputData_I(21 downto 17);
FT1_O := PMemOutputData_I(16 downto 12);
FT2_O := PMemOutputData_I(10 downto 6);
Kg_O := PMemOutputData_I(16 downto 0);
Kp_O := PMemOutputData_I(10 downto 0);
end procedure p_DecomposeInstructionIntoFields;
---------------------------------------------
function f_SelectRegOutput
(
FTx_I : in std_logic_vector(NumBitsRegBank - 1 downto 0);
PSW_I : in TRiscoWord;
PC_I : in TRiscoWord;
RegBnk_OutputData_I : in TRiscoWord
) return TRiscoWord is
variable FTxi : integer;
begin
FTXi := to_integer(unsigned(FTx_I));
case FTxi is
when C_R00 =>
return (others => '0');
when C_PSW =>
return PSW_I;
when C_PC =>
return PC_I;
when others =>
return RegBnk_OutputData_I; -- Source 1 and Source 2
end case;
end function f_SelectRegOutput;
---------------------------------------------
procedure p_SelectRegInput1
(
F1_F0_SS2_I : in std_logic_vector(2 downto 0);
DST_I : in std_logic_vector(4 downto 0);
FT1_I : in std_logic_vector(4 downto 0);
FT2_I : in std_logic_vector(4 downto 0);
signal RegBnk_Register1_O : out std_logic_vector(NumBitsRegBank - 1 downto 0)
) is
variable F1_F0_SS2_v : std_logic_vector(2 downto 0);
begin
if F1_F0_SS2_I(2 downto 1) /= "00" then
F1_F0_SS2_v(0) := '0'; -- Remove X
else
F1_F0_SS2_v(0) := F1_F0_SS2_I(0);
end if;
F1_F0_SS2_v(2 downto 1) := F1_F0_SS2_I(2 downto 1);
case F1_F0_SS2_v is
when FFS_DST_DST_Kgh | FFS_DST_DST_Kgl =>
RegBnk_Register1_O <= DST_I(NumBitsRegBank - 1 downto 0);
when FFS_DST_FT1_FT2 | FFS_DST_FT1_Kp =>
RegBnk_Register1_O <= FT1_I(NumBitsRegBank - 1 downto 0);
when others =>
RegBnk_Register1_O <= (others=>'0');
end case;
end procedure p_SelectRegInput1;
---------------------------------------------
procedure p_SelectRegInput2
(
F1_F0_SS2_I : in std_logic_vector(2 downto 0);
DST_I : in std_logic_vector(4 downto 0);
FT1_I : in std_logic_vector(4 downto 0);
FT2_I : in std_logic_vector(4 downto 0);
signal RegBnk_Register2_O : out std_logic_vector(NumBitsRegBank - 1 downto 0)
) is
variable F1_F0_SS2_v : std_logic_vector(2 downto 0);
begin
if F1_F0_SS2_I(2 downto 1) /= "00" then
F1_F0_SS2_v(0) := '0'; -- Remove X
else
F1_F0_SS2_v(0) := F1_F0_SS2_I(0);
end if;
F1_F0_SS2_v(2 downto 1) := F1_F0_SS2_I(2 downto 1);
case F1_F0_SS2_v is
when FFS_DST_FT1_FT2 =>
RegBnk_Register2_O <= FT2_I(NumBitsRegBank - 1 downto 0);
when others =>
RegBnk_Register2_O <= (others=>'0');
end case;
end procedure p_SelectRegInput2;
---------------------------------------------
begin
 
p_select_and_control: process(Reset_I,Clk_I,PMem_OutputData_I,DMem_OutputData_I,RegBnk_FT1_OutputData_I,RegBnk_FT2_OutputData_I,ULA_Output_I,ULA_Ng_O_I,ULA_Cy_O_I,ULA_Ov_O_I,ULA_Zr_O_I,UD_OutputData_I,UD_Cy_O_I,PC_Data_I,DMem_Address_W,PSW_Data_I,PSW_Data_I)
type TPhase is (RESET,IFETCH,IDECODE,OFETCH,IEXEC1,IEXEC2,IEXEC3);
variable Phase_v : TPhase; -- Phase of the Machine Cycle
variable NextPhase_v : TPhase;
variable T1_T0_v : std_logic_vector(1 downto 0); -- Instruction Type
variable C4_C0_v : std_logic_vector(4 downto 0); -- Instruction inside its type
variable F1_F0_SS2_v : std_logic_vector(2 downto 0); -- Format of operands
variable APS_v : std_logic; -- Update or not Status Word
variable DST_v : std_logic_vector(4 downto 0); -- Index of Destination
variable FT1_v : std_logic_vector(4 downto 0); -- Index of Source 1
variable FT2_v : std_logic_vector(4 downto 0); -- Index of Source 2
variable Kp_v : std_logic_vector(10 downto 0); -- Small Constant (Used to determine Constext)
variable Kg_v : std_logic_vector(16 downto 0); -- Large Constant (Used to determine Constext)
variable Condition_v : std_logic; -- Evaluate Condition
variable IntAck_v : std_logic; -- Interrupt Acknowledge
variable IntMask_v : std_logic; -- Masks interruption during first instruction of the ISR
begin
if rising_edge(Clk_I) then
-------
-- FSM
-------
Phase_v := NextPhase_v;
if Reset_I ='1' then
NextPhase_v := RESET;
Phase_v := RESET;
IntAck_v := '0';
IntMask_v := '0';
elsif Phase_v = RESET then
NextPhase_v := IFETCH;
elsif Phase_v = IFETCH then
NextPhase_v := IDECODE;
if Int_I = '0' then
IntAck_v := '0';
end if;
elsif Phase_v = IDECODE then
--
NextPhase_v := OFETCH;
elsif Phase_v = OFETCH then
if Int_I = '0' or IntMask_v = '1' or InterruptEnable_w = '0' then -- without reentrant interrupts...
p_DecomposeInstructionIntoFields(PMem_OutputData_I,T1_T0_v,C4_C0_v,F1_F0_SS2_v,APS_v,DST_v,FT1_v,FT2_v,Kp_v,Kg_v);
IntMask_v := '0';
else -- Interrupt = inst sub; SPISR = R30 (original); SPISR = SPISR - 1; M[R30] = PC; PC = R00 + Kpe(0400h)
T1_T0_v := INST_SUB;
C4_C0_v := C_TR;
F1_F0_SS2_v := FFS_DST_FT1_Kp;
APS_v := '0';
DST_v := std_logic_vector(to_unsigned(C_SPISR,DST_v'high+1)); -- beware with the register used to recover the PC with smaller sizes of RegBank...
FT1_v := std_logic_vector(to_unsigned(C_R00,FT1_v'high+1));
Kp_v := "10000000000"; -- 400h -> address FFFFFC00
IntAck_v := '1';
IntMask_v := '1';
end if;
NextPhase_v := IEXEC1;
elsif Phase_v = IEXEC1 then
IntAck_v := '0';
if T1_T0_v = INST_ULA then
NextPhase_v := IFETCH;
elsif T1_T0_v = INST_MEM and C4_C0_v = C_ST then
NextPhase_v := IFETCH;
else
NextPhase_v := IEXEC2;
end if;
elsif Phase_v = IEXEC2 then
if (T1_T0_v = INST_MEM and (C4_C0_v = C_LDPOI or C4_C0_v = C_LDPOD or C4_C0_v = C_LDPRI)) or (T1_T0_v = INST_SUB) then
NextPhase_v := IEXEC3;
else
NextPhase_v := IFETCH;
end if;
elsif Phase_v = IEXEC3 then
NextPhase_v := IFETCH;
 
end if;
end if;
-------------------------
-- Selectors and Outputs
-------------------------
 
if Reset_I = '1' then
IntAck_O <= '0';
IntAck_v := '0';
else
IntAck_O <= IntAck_v;
end if;
if Reset_I = '1' then
PMem_Enable_O <= '0';
DMem_Enable_O <= '0';
else
PMem_Enable_O <= '1';
DMem_Enable_O <= '1';
end if;
-- Condition
Condition_v := '0';
if Phase_v = OFETCH then
case C4_C0_v is
when C_TR => Condition_v := '1';
when C_NS => Condition_v := ULA_Ng_O_I;
when C_CS => Condition_v := ULA_Cy_O_I;
when C_OS => Condition_v := ULA_Ov_O_I;
when C_ZS => Condition_v := ULA_Zr_O_I;
when C_GE => Condition_v := (not ULA_Ng_O_I);
when C_GT => Condition_v := (not ULA_Ng_O_I) and (not ULA_Zr_O_I);
when C_EQ => Condition_v := ULA_Zr_O_I;
when C_FL => Condition_v := '0';
when C_NN => Condition_v := not ULA_Ng_O_I;
when C_NC => Condition_v := not ULA_Cy_O_I;
when C_NO => Condition_v := not ULA_Ov_O_I;
when C_NZ => Condition_v := not ULA_Zr_O_I;
when C_LT => Condition_v := ULA_Ng_O_I;
when C_LE => Condition_v := ULA_Ng_O_I or ULA_Zr_O_I;
when C_NE => Condition_v := not ULA_Zr_O_I;
when others => Condition_v := '0';
end case;
end if;
-- Data Memory
DMem_Address_W <= (others => '0');-- Default
DMem_InputData_O <= (others => '0');
DMem_Write_O <= '0';
case Phase_v is
when IEXEC1 =>
if T1_T0_v = INST_MEM and (C4_C0_v = C_ST or C4_C0_v = C_STPOI or C4_C0_v = C_STPOD) then
DMem_Address_W <= ULA_Output_I(DMem_Address_W'range);
DMem_InputData_O <= RegBnk_FT1_OutputData_I;
DMem_Write_O <= '1';
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_LD or C4_C0_v = C_LDPOI or C4_C0_v = C_LDPOD) then
DMem_Address_W <= ULA_Output_I(DMem_Address_W'range);
elsif T1_T0_v = INST_SUB and Condition_v = '1' then
DMem_Address_W <= ULA_Output_I(DMem_Address_W'range);
DMem_InputData_O <= PC_Data_I;
DMem_Write_O <= '1';
end if;
when IEXEC2 =>
if T1_T0_v = INST_MEM and C4_C0_v = C_STPRI then
DMem_Address_W <= ULA_Output_I(DMem_Address_W'range);
DMem_InputData_O <= RegBnk_FT1_OutputData_I;
DMem_Write_O <= '1';
elsif T1_T0_v = INST_MEM and C4_C0_v = C_LDPRI then
DMem_Address_W <= ULA_Output_I(DMem_Address_W'range);
DMem_InputData_O <= RegBnk_FT1_OutputData_I;
end if;
when others =>
DMem_Address_W <= (others => '0');
DMem_InputData_O <= (others => '0');
DMem_Write_O <= '0';
end case;
-- Register Bank
RegBnk_Register1_O <= (others=>'0');-- Default
RegBnk_Register2_O <= (others=>'0');
RegBnk_RegisterW_O <= (others=>'0');
RegBnk_Write_O <= '0';
RegBnk_InputData_O <= (others => '0');
case Phase_v is
when OFETCH =>
-- Type of operands
if T1_T0_v = INST_ULA then
p_SelectRegInput1(F1_F0_SS2_v,DST_v,FT1_v,FT2_v,RegBnk_Register1_O);
p_SelectRegInput2(F1_F0_SS2_v,DST_v,FT1_v,FT2_v,RegBnk_Register2_O);
elsif T1_T0_v = INST_MEM or T1_T0_v = INST_JMP then
p_SelectRegInput1(F1_F0_SS2_v,DST_v,FT1_v,FT2_v,RegBnk_Register1_O);
p_SelectRegInput2(F1_F0_SS2_v,DST_v,FT1_v,FT2_v,RegBnk_Register2_O);
RegBnk_RegisterW_O <= DST_v(NumBitsRegBank - 1 downto 0);
elsif T1_T0_v = INST_SUB then
RegBnk_Register1_O <= DST_v(NumBitsRegBank - 1 downto 0);
end if;
when IEXEC1 =>
-- Execute
if T1_T0_v = INST_ULA and DST_v(NumBitsRegBank - 1 downto 0) /= std_logic_vector(to_unsigned(C_PC,RegBnk_Register1_O'high+1)) then --If DST=PC, write to PC
RegBnk_RegisterW_O <= DST_v(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O <= '1';
case C4_C0_v is -- Choose between ULA and UD result
-- ULA
when C_ADD | C_ADDC | C_SUB | C_SUBC | C_SUBR | C_SUBRC | C_AND | C_OR | C_XOR =>
RegBnk_InputData_O <= ULA_Output_I;
-- Shifter
when C_SRL | C_SLL | C_SRA | C_SLA | C_RRL | C_RLL | C_RRA | C_RLA =>
RegBnk_InputData_O <= UD_OutputData_I;
when C_SRLC | C_SLLC | C_SRAC | C_SLAC | C_RRLC | C_RLLC | C_RRAC | C_RLAC =>
RegBnk_InputData_O <= UD_OutputData_I;
when others =>
RegBnk_InputData_O <= (others => '0');
end case;
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_ST or C4_C0_v = C_STPOI or C4_C0_v = C_STPOD) then
RegBnk_Register1_O <= DST_v(NumBitsRegBank - 1 downto 0);
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_STPRI or C4_C0_v = C_LDPRI) then
RegBnk_RegisterW_O <= FT2_v(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O <= '1';
RegBnk_InputData_O <= ULA_Output_I;
p_SelectRegInput1(F1_F0_SS2_v,DST_v,FT1_v,FT2_v,RegBnk_Register1_O);
elsif T1_T0_v = INST_SUB and Condition_v = '1' then
RegBnk_RegisterW_O <= DST_v(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O <= '1';
RegBnk_InputData_O <= ULA_Output_I;
p_SelectRegInput1(F1_F0_SS2_v,DST_v,FT1_v,FT2_v,RegBnk_Register1_O);
p_SelectRegInput2(F1_F0_SS2_v,DST_v,FT1_v,FT2_v,RegBnk_Register2_O);
end if;
when IEXEC2 =>
if T1_T0_v = INST_MEM and (C4_C0_v = C_LD or C4_C0_v = C_LDPOI or C4_C0_v = C_LDPOD) then
RegBnk_RegisterW_O <= DST_v(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O <= '1';
RegBnk_InputData_O <= DMem_OutputData_I;
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_STPOI or C4_C0_v = C_STPOD) then
RegBnk_RegisterW_O <= FT2_v(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O <= '1';
RegBnk_InputData_O <= ULA_Output_I;
elsif T1_T0_v = INST_MEM and C4_C0_v = C_STPRI then
RegBnk_Register1_O <= DST_v(NumBitsRegBank - 1 downto 0);
end if;
when IEXEC3 =>
if T1_T0_v = INST_MEM and C4_C0_v = C_LDPRI then
RegBnk_RegisterW_O <= DST_v(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O <= '1';
RegBnk_InputData_O <= DMem_OutputData_I;
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_LDPOI or C4_C0_v = C_LDPOD) then
RegBnk_RegisterW_O <= FT2_v(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O <= '1';
RegBnk_InputData_O <= ULA_Output_I;
end if;
when others =>
RegBnk_Register1_O <= (others => '0');
RegBnk_Register2_O <= (others => '0');
RegBnk_Write_O <= '0';
RegBnk_InputData_O <= (others => '0');
end case;
-- PSW
-- When APS = 1, update flags for ULA/UD operations with flags values
-- When APS = 0, update flags only via store operation on PSW (R01)
PSW_Data_O <= (others => '0');
PSW_Wen_O <= '0';
case Phase_v is
when IEXEC1 =>
if T1_T0_v = INST_ULA then
case C4_C0_v is -- Choose between ULA and UD result
-- ULA
when C_ADD | C_ADDC | C_SUB | C_SUBC | C_SUBR | C_SUBRC | C_AND | C_OR | C_XOR =>
if DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= ULA_Output_I;
else
PSW_Data_O <= PSW_Data_I;
end if;
if APS_v = '1' then
PSW_Data_O(7 downto 4) <= ULA_Ng_O_I & ULA_Ov_O_I & ULA_Zr_O_I & ULA_Cy_O_I;
end if;
-- Shifter
when C_SRL | C_SLL | C_SRA | C_SLA | C_RRL | C_RLL | C_RRA | C_RLA =>
if DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= UD_OutputData_I;
else
PSW_Data_O <= PSW_Data_I;
end if;
 
when C_SRLC | C_SLLC | C_SRAC | C_SLAC | C_RRLC | C_RLLC | C_RRAC | C_RLAC =>
if DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= UD_OutputData_I;
else
PSW_Data_O <= PSW_Data_I;
end if;
if APS_v = '1' then
PSW_Data_O(4) <= UD_Cy_O_I;
end if;
when others =>
PSW_Data_O <= (others => '0');
end case;
PSW_Wen_O <= '1';
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_STPRI or C4_C0_v = C_LDPRI) and FT2_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= ULA_Output_I;
PSW_Wen_O <= '1';
elsif T1_T0_v = INST_SUB and Condition_v = '1' and DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= ULA_Output_I;
PSW_Wen_O <= '1';
end if;
when IEXEC2 =>
if T1_T0_v = INST_MEM and (C4_C0_v = C_LD or C4_C0_v = C_LDPOI or C4_C0_v = C_LDPOD) and DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= DMem_OutputData_I;
PSW_Wen_O <= '1';
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_STPOI or C4_C0_v = C_STPOD) and FT2_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= ULA_Output_I;
PSW_Wen_O <= '1';
end if;
when IEXEC3 =>
if T1_T0_v = INST_MEM and C4_C0_v = C_LDPRI and DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= DMem_OutputData_I;
PSW_Wen_O <= '1';
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_LDPOI or C4_C0_v = C_LDPOD) and FT2_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PSW,RegBnk_Register1_O'high+1)) then
PSW_Data_O <= ULA_Output_I;
PSW_Wen_O <= '1';
end if;
when others =>
PSW_Data_O <= (others => '0');
PSW_Wen_O <= '0';
end case;
-- PC
PC_Wen_O <= '0';
PC_Data_O <= (others => '0');
case Phase_v is
when IEXEC1 =>
if (T1_T0_v = INST_ULA and DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PC,RegBnk_Register1_O'high+1))) then -- PC=R31
PC_Wen_O <= '1';
PC_Data_O <= ULA_Output_I;
elsif (T1_T0_v = INST_JMP and Condition_v = '1' and DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PC,RegBnk_Register1_O'high + 1))) then
PC_Wen_O <= '1';
PC_Data_O <= ULA_Output_I;
else
PC_Wen_O <= '1';
PC_Data_O <= std_logic_vector(unsigned(PC_Data_I) + 1);
end if;
when IEXEC2 =>
if T1_T0_v = INST_SUB and Condition_v = '1' then
PC_Wen_O <= '1';
PC_Data_O <= ULA_Output_I;
elsif T1_T0_v = INST_MEM and C4_C0_v = C_LDPOI and DST_v(NumBitsRegBank - 1 downto 0) = std_logic_vector(to_unsigned(C_PC,RegBnk_Register1_O'high + 1)) then
PC_Wen_O <= '1';
PC_Data_O <= DMem_OutputData_I;
end if;
when others =>
PC_Wen_O <= '0';
PC_Data_O <= (others => '0');
end case;
-- ULA,UD
ULA_Function_O <= (others=>'0');-- default
UD_Function_O <= (others=>'0');
case Phase_v is
when IEXEC1 =>
-- ULA/UD Function
if T1_T0_v = INST_ULA then
ULA_Function_O <= C4_C0_v;
UD_Function_O <= C4_C0_v;
elsif T1_T0_v = INST_MEM and C4_C0_v = C_ST then
ULA_Function_O <= C_ADD;
elsif T1_T0_v = INST_MEM and C4_C0_v = C_LD then
ULA_Function_O <= C_ADD;
elsif T1_T0_v = INST_JMP then
ULA_Function_O <= C_ADD;
elsif T1_T0_v = INST_SUB then
ULA_Function_O <= C_SUB;
end if;
when IEXEC2 =>
case T1_T0_v is -- ULA and UD function based on instruction type
when INST_MEM =>
if C4_C0_v = C_STPOI or C4_C0_v = C_STPOD then
ULA_Function_O <= C_ADD;
end if;
when INST_SUB =>
if Condition_v = '1' then
ULA_Function_O <= C_ADD;
end if;
when others =>
ULA_Function_O <= (others=>'0');
UD_Function_O <= (others=>'0');
end case;
when IEXEC3 =>
if T1_T0_v = INST_MEM and (C4_C0_v = C_LDPOI or C4_C0_v = C_LDPOD) then
ULA_Function_O <= C_ADD;
end if;
when others =>
ULA_Function_O <= (others=>'0');
UD_Function_O <= (others=>'0');
end case;
-- RUA,RUB,RDA,RDB
RUA_Wen_O <= '0'; RUB_Wen_O <= '0'; RDA_Wen_O <= '0'; RDB_Wen_O <= '0';
RUA_Data_O <= (others=>'0'); RUB_Data_O <= (others=>'0');
RDA_Data_O <= (others=>'0'); RDB_Data_O <= (others=>'0');
case Phase_v is
when OFETCH =>
RUA_Wen_O <= '1'; RUB_Wen_O <= '1'; RDA_Wen_O <= '1'; RDB_Wen_O <= '1';
if T1_T0_v = INST_MEM and (C4_C0_v = C_STPRI or C4_C0_v = C_LDPRI) then
RUA_Data_O <= std_logic_vector(to_unsigned(1,RUA_Data_O'high+1));
case (F1_F0_SS2_v) is
when FFS_DST_FT1_FT2 => RUB_Data_O <= f_SelectRegOutput(FT2_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT2_OutputData_I);
when FFS_DST_FT1_Kp => RUB_Data_O <= Kpe_F(Kp_v); -- Source 1 and Kp
when FFS_DST_R00_Kgl => RUB_Data_O <= Kgl_F(Kg_v); -- R00 and Kgl
when FFS_DST_DST_Kgl => RUB_Data_O <= Kgl_F(Kg_v); -- DST and Kgl
when others => RUB_Data_O <= (others=>'0'); -- Not Specified
end case;
elsif T1_T0_v = INST_SUB then
RUA_Data_O <= f_SelectRegOutput(DST_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I;
RUB_Data_O <= std_logic_vector(to_unsigned(1,RUA_Data_O'high+1));
else
-- Operand fetch for ULA and UD
case (F1_F0_SS2_v) is
when FFS_DST_FT1_FT2 => RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I; -- Source 1 and Source 2
RUB_Data_O <= f_SelectRegOutput(FT2_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT2_OutputData_I); --RegBnk_FT2_OutputData_I;
RDA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I;
RDB_Data_O <= f_SelectRegOutput(FT2_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT2_OutputData_I); --RegBnk_FT2_OutputData_I;
when FFS_DST_FT1_Kp => RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I; -- Source 1 and Kp
RUB_Data_O <= Kpe_F(Kp_v);
RDA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I;
RDB_Data_O <= Kpe_F(Kp_v);
when FFS_DST_R00_Kgl => RUA_Data_O <= (others => '0'); -- R00 and Kgl
RUB_Data_O <= Kgl_F(Kg_v);
RDA_Data_O <= (others => '0');
RDB_Data_O <= Kgl_F(Kg_v);
when FFS_DST_DST_Kgl => RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I; -- DST and Kgl
RUB_Data_O <= Kgl_F(Kg_v);
RDA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I;
RDB_Data_O <= Kgl_F(Kg_v);
when others => RUA_Data_O <= (others=>'0'); -- Not Specified
RUB_Data_O <= (others=>'0');
RDA_Data_O <= (others=>'0');
RDB_Data_O <= (others=>'0');
end case;
end if;
when IEXEC1 =>
if T1_T0_v = INST_MEM and (C4_C0_v = C_STPOI or C4_C0_v = C_LDPOI) then
RUA_Data_O <= std_logic_vector(to_unsigned(1,RUA_Data_O'high+1));
RUA_Wen_O <= '1';
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_STPOD or C4_C0_v = C_LDPOD) then
RUA_Data_O <= std_logic_vector(to_signed(-1,RUA_Data_O'high+1));
RUA_Wen_O <= '1';
elsif T1_T0_v = INST_MEM and (C4_C0_v = C_STPRI or C4_C0_v = C_LDPRI) then
case (F1_F0_SS2_v) is
when FFS_DST_FT1_FT2 => RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I;
when FFS_DST_FT1_Kp => RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I;
when FFS_DST_R00_Kgl => RUA_Data_O <= (others => '0');
when FFS_DST_DST_Kgl => RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I;
when others => RUA_Data_O <= (others=>'0');
end case;
RUA_Wen_O <= '1';
RUB_Data_O <= ULA_Output_I;
RUB_Wen_O <= '1';
elsif T1_T0_v = INST_SUB and Condition_v = '1' then
case (F1_F0_SS2_v) is
when FFS_DST_FT1_FT2 =>
RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I; -- Source 1 and Source
RUB_Data_O <= f_SelectRegOutput(FT2_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT2_OutputData_I); --RegBnk_FT2_OutputData_I;
when FFS_DST_FT1_Kp =>
RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I; -- Source 1 and K
RUB_Data_O <= Kpe_F(Kp_v);
when FFS_DST_R00_Kgl =>
RUA_Data_O <= (others => '0'); -- R00 and Kgl
RUB_Data_O <= Kgl_F(Kg_v);
when FFS_DST_DST_Kgl =>
RUA_Data_O <= f_SelectRegOutput(FT1_v(NumBitsRegBank - 1 downto 0),PSW_Data_I,PC_Data_I,RegBnk_FT1_OutputData_I); --RegBnk_FT1_OutputData_I; -- DST and Kgl
RUB_Data_O <= Kgl_F(Kg_v);
when others =>
RUA_Data_O <= (others=>'0'); -- Not Specified
RUB_Data_O <= (others=>'0');
end case;
RUA_Wen_O <= '1';
RUB_Wen_O <= '1';
end if;
when others =>
RUA_Wen_O <= '0'; RUB_Wen_O <= '0'; RDA_Wen_O <= '0'; RDB_Wen_O <= '0';
RUA_Data_O <= (others=>'0'); RUB_Data_O <= (others=>'0');
RDA_Data_O <= (others=>'0'); RDB_Data_O <= (others=>'0');
end case;
 
-- RUA_Clr_O, RUB_Clr_O, RDA_Clr_O, RDB_Clr_O, PSW_Clr_O
case Phase_v is
when RESET =>
RUA_Clr_O <= '1'; RUB_Clr_O <= '1'; RDA_Clr_O <= '1'; RDB_Clr_O <= '1'; PC_Clr_O <= '1'; PSW_Clr_O <= '1';
when others =>
RUA_Clr_O <= '0'; RUB_Clr_O <= '0'; RDA_Clr_O <= '0'; RDB_Clr_O <= '0'; PC_Clr_O <= '0'; PSW_Clr_O <= '0';
end case;
 
end process;
 
PMem_Write_O <= '0'; -- Program Memory Read
PMem_Address_O <= PC_Data_I(PMem_Address_O'range) when Reset_I = '0' else -- Set memory address
(others => '0');
DMem_Address_O <= DMem_Address_W when Reset_I = '0' else -- Set memory address
(others => '0');
 
end Ark1;
/rtl/ula.vhd
0,0 → 1,58
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
entity Ula is
port
(
Cy_I : in std_logic;
Source1_I : in TRiscoWord;
Source2_I : in TRiscoWord;
Function_I : in std_logic_vector(4 downto 0);
Output_O : out TRiscoWord;
Cy_O : out std_logic;
Ov_O : out std_logic;
Zr_O : out std_logic;
Ng_O : out std_logic
);
end Ula;
-------------------------------------------------------------------------------------------------------------------
architecture behavioral of ula is
signal UlaTemp_W : std_logic_vector(32 downto 0);
signal Carry_W : TRiscoWord;
begin
Carry_W(0) <= Cy_I;
Carry_W(TRiscoWord'high downto 1) <= (others => '0');
with Function_I select
-- Fig. 5.8 of [1]
-- Carry -> bit 32
UlaTemp_W <=
('0'&Source1_I) and ('0'&Source2_I) when C_AND,
('0'&Source1_I) or ('0'&Source2_I) when C_OR,
('0'&Source1_I) xor ('0'&Source2_I) when C_XOR,
 
std_logic_vector(unsigned('0'&not(Source1_I)) + unsigned('0'&Source2_I) + unsigned(not(Carry_W))) when C_SUBRC,
std_logic_vector(unsigned('0'&not(Source1_I)) + unsigned('0'&Source2_I) + unsigned(Carry_W) ) when C_SUBRCNOT,
std_logic_vector(unsigned('0'&not(Source1_I)) + unsigned('0'&Source2_I) + 1 ) when C_SUBR,
std_logic_vector(unsigned('0'&not(Source1_I)) + unsigned('0'&Source2_I) + 0 ) when C_SUBRNC,
 
std_logic_vector(unsigned('0'&Source1_I) + unsigned('0'&not(Source2_I)) + unsigned(not(Carry_W))) when C_SUBC,
std_logic_vector(unsigned('0'&Source1_I) + unsigned('0'&not(Source2_I)) + unsigned(Carry_W) ) when C_SUBCNOT,
std_logic_vector(unsigned('0'&Source1_I) + unsigned('0'&not(Source2_I)) + 1 ) when C_SUB,
std_logic_vector(unsigned('0'&Source1_I) + unsigned('0'&not(Source2_I)) + 0 ) when C_SUBNC,
 
std_logic_vector(unsigned('0'&Source1_I) + unsigned('0'&Source2_I) + unsigned(not(Carry_W))) when C_ADDCNOT,
std_logic_vector(unsigned('0'&Source1_I) + unsigned('0'&Source2_I) + unsigned(Carry_W) ) when C_ADDC,
std_logic_vector(unsigned('0'&Source1_I) + unsigned('0'&Source2_I) + 1 ) when C_ADD1,
std_logic_vector(unsigned('0'&Source1_I) + unsigned('0'&Source2_I) + 0 ) when C_ADD,
 
(others => '0') when others;
Output_O <= UlaTemp_W(Output_O'range);
Cy_O <= UlaTemp_W(32);
Ov_O <= UlaTemp_W(32);
Zr_O <= IsZero_F(UlaTemp_W);
Ng_O <= UlaTemp_W(31);
end behavioral;
-------------------------------------------------------------------------------------------------------------------
/rtl/ud_package.vhd
0,0 → 1,729
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
package ud_package is
---------------------------------------------
function SRLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function SRL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function SLLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function SLL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function SRAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function SRA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function SLAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function SLA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function RRLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function RRL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function RLLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function RLL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function RRAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function RRA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function RLAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function RLA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
function SRLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function SRLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function SLLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function SLLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function SRACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function SRAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function SLACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function SLAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
 
function RRLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function RRLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function RLLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function RLLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function RRACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function RRAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function RLACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
function RLAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
---------------------------------------------
end package;
package body ud_package is
--
-- Estas funcoes necessitam uma validacao.
-- Alguns casos nao estao completamente claros no texto original.
--
-- C - Carry
-- S - Signal (bit 31)
-- bn - bit n
-- |bm -> bn| - bit m to bit n shift to right
-- |bm <- bn| - bit m to bit n shift to left
---------------------------------------------
-- Shift Right Logical
-- 0-> |b31 -> b0|
--
-- Generic
function SRLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1((TRiscoWord'high-to_integer(unsigned(FT2))) downto 0):=Source1(TRiscoWord'high downto to_integer(unsigned(FT2)));
VSource1(TRiscoWord'high downto (TRiscoWord'high-to_integer(unsigned(FT2))+1)):=(others =>'0');
return VSource1;
end function SRLg_F;
--
-- Original (only 1,2,4,8,16)
function SRL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
case to_integer(unsigned(FT2)) is
when 1 =>
VSource1(TRiscoWord'high-1 downto 0):=Source1(TRiscoWord'high downto 1);
VSource1(TRiscoWord'high):='0';
when 2 =>
VSource1(TRiscoWord'high-2 downto 0):=Source1(TRiscoWord'high downto 2);
VSource1(TRiscoWord'high downto TRiscoWord'high-1):=(others =>'0');
when 4 =>
VSource1(TRiscoWord'high-4 downto 0):=Source1(TRiscoWord'high downto 4);
VSource1(TRiscoWord'high downto TRiscoWord'high-3):=(others =>'0');
when 8 =>
VSource1(TRiscoWord'high-8 downto 0):=Source1(TRiscoWord'high downto 8);
VSource1(TRiscoWord'high downto TRiscoWord'high-7):=(others =>'0');
when others => --16
VSource1(TRiscoWord'high-16 downto 0):=Source1(TRiscoWord'high downto 16);
VSource1(TRiscoWord'high downto TRiscoWord'high-15):=(others =>'0');
end case;
return VSource1;
end function SRL_F;
---------------------------------------------
-- Shift Left Logical
-- |b31 <- b0| <-0
--
-- Generic
function SLLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high downto to_integer(unsigned(FT2))):=Source1(TRiscoWord'high-to_integer(unsigned(FT2)) downto 0);
VSource1(to_integer(unsigned(FT2))-1 downto 0):=(others =>'0');
return VSource1;
end function SLLg_F;
--
-- Original (only 1,2,4,8,6)
function SLL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
case to_integer(unsigned(FT2)) is
when 1 =>
VSource1(TRiscoWord'high downto 1):=Source1(TRiscoWord'high-1 downto 0);
VSource1(0):='0';
when 2 =>
VSource1(TRiscoWord'high downto 2):=Source1(TRiscoWord'high-2 downto 0);
VSource1(1 downto 0):=(others =>'0');
when 4 =>
VSource1(TRiscoWord'high downto 4):=Source1(TRiscoWord'high-4 downto 0);
VSource1(3 downto 0):=(others =>'0');
when 8=>
VSource1(TRiscoWord'high downto 8):=Source1(TRiscoWord'high-8 downto 0);
VSource1(7 downto 0):=(others =>'0');
when others => -- 16
VSource1(TRiscoWord'high downto 16):=Source1(TRiscoWord'high-16 downto 0);
VSource1(15 downto 0):=(others =>'0');
end case;
return VSource1;
end function SLL_F;
---------------------------------------------
-- Shift Right Arithmetic
-- S-> |b30 -> b0|
--
-- Generic
function SRAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high-to_integer(unsigned(FT2)) downto 0):=Source1(TRiscoWord'high downto to_integer(unsigned(FT2)));
VSource1(TRiscoWord'high downto TRiscoWord'high-to_integer(unsigned(FT2))+1):=(others => Source1(Source1'high));
return VSource1;
end function SRAg_F;
--
-- Original (only 1,2,4,8,16)
function SRA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
case to_integer(unsigned(FT2)) is
when 1 =>
VSource1(TRiscoWord'high-1 downto 0):=Source1(TRiscoWord'high downto 1);
VSource1(TRiscoWord'high):=Source1(Source1'high);
when 2 =>
VSource1(TRiscoWord'high-2 downto 0):=Source1(TRiscoWord'high downto 2);
VSource1(TRiscoWord'high downto TRiscoWord'high-1):=(others =>Source1(Source1'high));
when 4 =>
VSource1(TRiscoWord'high-4 downto 0):=Source1(TRiscoWord'high downto 4);
VSource1(TRiscoWord'high downto TRiscoWord'high-3):=(others =>Source1(Source1'high));
when 8=>
VSource1(TRiscoWord'high-8 downto 0):=Source1(TRiscoWord'high downto 8);
VSource1(TRiscoWord'high downto TRiscoWord'high-7):=(others =>Source1(Source1'high));
when others => -- 16
VSource1(TRiscoWord'high-16 downto 0):=Source1(TRiscoWord'high downto 16);
VSource1(TRiscoWord'high downto TRiscoWord'high-15):=(others =>Source1(Source1'high));
end case;
return VSource1;
end function SRA_F;
---------------------------------------------
-- Shift Left Arithmetic
-- S |b30 <- b0|
--
-- Generic
function SLAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
VSource1(TRiscoWord'high-1 downto to_integer(unsigned(FT2))):=Source1(TRiscoWord'high-to_integer(unsigned(FT2))-1 downto 0);
VSource1(to_integer(unsigned(FT2))-1 downto 0):=(others =>'0');
return VSource1;
end function SLAg_F;
--
-- Original (only 1,2,4,8,6)
function SLA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
case to_integer(unsigned(FT2)) is
when 1 =>
VSource1(TRiscoWord'high-1 downto 1):=Source1(TRiscoWord'high-2 downto 0);
VSource1(0):='0';
when 2 =>
VSource1(TRiscoWord'high-1 downto 2):=Source1(TRiscoWord'high-3 downto 0);
VSource1(1 downto 0):=(others =>'0');
when 4 =>
VSource1(TRiscoWord'high-1 downto 4):=Source1(TRiscoWord'high-5 downto 0);
VSource1(3 downto 0):=(others =>'0');
when 8=>
VSource1(TRiscoWord'high-1 downto 8):=Source1(TRiscoWord'high-9 downto 0);
VSource1(7 downto 0):=(others =>'0');
when others => -- 16
VSource1(TRiscoWord'high-1 downto 16):=Source1(TRiscoWord'high-17 downto 0);
VSource1(15 downto 0):=(others =>'0');
end case;
return VSource1;
end function SLA_F;
---------------------------------------------
-- Rotate Right Logical
-- b0-> |b31 -> b0|
--
-- Generic
function RRLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high-to_integer(unsigned(FT2)) downto 0):=Source1(TRiscoWord'high downto to_integer(unsigned(FT2)));
VSource1(TRiscoWord'high downto TRiscoWord'high-to_integer(unsigned(FT2))+1):=Source1(to_integer(unsigned(FT2))-1 downto 0);
return VSource1;
end function RRLg_F;
--
-- Original (only 1,2,4,8,6)
function RRL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
case to_integer(unsigned(FT2)) is
when 1 =>
VSource1(TRiscoWord'high-1 downto 0):=Source1(TRiscoWord'high downto 1);
VSource1(TRiscoWord'high):=Source1(0);
when 2 =>
VSource1(TRiscoWord'high-2 downto 0):=Source1(TRiscoWord'high downto 2);
VSource1(TRiscoWord'high downto TRiscoWord'high-1):=Source1(1 downto 0);
when 4 =>
VSource1(TRiscoWord'high-4 downto 0):=Source1(TRiscoWord'high downto 4);
VSource1(TRiscoWord'high downto TRiscoWord'high-3):=Source1(3 downto 0);
when 8=>
VSource1(TRiscoWord'high-8 downto 0):=Source1(TRiscoWord'high downto 8);
VSource1(TRiscoWord'high downto TRiscoWord'high-7):=Source1(7 downto 0);
when others => -- 16
VSource1(TRiscoWord'high-16 downto 0):=Source1(TRiscoWord'high downto 16);
VSource1(TRiscoWord'high downto TRiscoWord'high-15):=Source1(15 downto 0);
end case;
return VSource1;
end function RRL_F;
---------------------------------------------
-- Rotate Left Logical
-- |b31 <- b0| <-b31
--
-- Generic
function RLLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high downto to_integer(unsigned(FT2))):=Source1(TRiscoWord'high-to_integer(unsigned(FT2)) downto 0);
VSource1(to_integer(unsigned(FT2))-1 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-to_integer(unsigned(FT2))+1);
return VSource1;
end function RLLg_F;
--
-- Original (only 1,2,4,8,6)
function RLL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
case to_integer(unsigned(FT2)) is
when 1 =>
VSource1(TRiscoWord'high downto 1):=Source1(TRiscoWord'high-1 downto 0);
VSource1(0):=Source1(TRiscoWord'high);
when 2 =>
VSource1(TRiscoWord'high downto 2):=Source1(TRiscoWord'high-2 downto 0);
VSource1(1 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-1);
when 4 =>
VSource1(TRiscoWord'high downto 4):=Source1(TRiscoWord'high-4 downto 0);
VSource1(3 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-3);
when 8 =>
VSource1(TRiscoWord'high downto 8):=Source1(TRiscoWord'high-8 downto 0);
VSource1(7 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-7);
when others => -- 16
VSource1(TRiscoWord'high downto 16):=Source1(TRiscoWord'high-16 downto 0);
VSource1(15 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-15);
end case;
return VSource1;
end function RLL_F;
---------------------------------------------
-- Rotate Right Arithmetical
-- b0-> |b30 -> b0|
--
-- Generic
function RRAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high-to_integer(unsigned(FT2))-1 downto 0):=Source1(TRiscoWord'high-1 downto to_integer(unsigned(FT2)));
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-to_integer(unsigned(FT2))):=Source1(to_integer(unsigned(FT2))-1 downto 0);
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
return VSource1;
end function RRAg_F;
--
-- Original (only 1,2,4,8,6)
function RRA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
case to_integer(unsigned(FT2)) is
when 1 =>
VSource1(TRiscoWord'high-2 downto 0):=Source1(TRiscoWord'high-1 downto 1);
VSource1(TRiscoWord'high-1):=Source1(0);
when 2 =>
VSource1(TRiscoWord'high-3 downto 0):=Source1(TRiscoWord'high-1 downto 2);
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-2):=Source1(1 downto 0);
when 4 =>
VSource1(TRiscoWord'high-5 downto 0):=Source1(TRiscoWord'high-1 downto 4);
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-4):=Source1(3 downto 0);
when 8=>
VSource1(TRiscoWord'high-9 downto 0):=Source1(TRiscoWord'high-1 downto 8);
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-8):=Source1(7 downto 0);
when others => -- 16
VSource1(TRiscoWord'high-17 downto 0):=Source1(TRiscoWord'high-1 downto 16);
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-16):=Source1(15 downto 0);
end case;
return VSource1;
end function RRA_F;
---------------------------------------------
-- Rotate Left Arithmetical
-- |b31 <- b0| <-b31
--
-- Generic
function RLAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high-1 downto to_integer(unsigned(FT2))):=Source1(TRiscoWord'high-to_integer(unsigned(FT2))-1 downto 0);
VSource1(to_integer(unsigned(FT2))-1 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-to_integer(unsigned(FT2)));
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
return VSource1;
end function RLAg_F;
--
-- Original (only 1,2,4,8,6)
function RLA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
variable VSource1 : TRiscoWord;
begin
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
case to_integer(unsigned(FT2)) is
when 1 =>
VSource1(TRiscoWord'high-1 downto 1):=Source1(TRiscoWord'high-2 downto 0);
VSource1(0):=Source1(TRiscoWord'high-1);
when 2 =>
VSource1(TRiscoWord'high-1 downto 2):=Source1(TRiscoWord'high-3 downto 0);
VSource1(1 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-2);
when 4 =>
VSource1(TRiscoWord'high-1 downto 4):=Source1(TRiscoWord'high-5 downto 0);
VSource1(3 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-4);
when 8=>
VSource1(TRiscoWord'high-1 downto 8):=Source1(TRiscoWord'high-9 downto 0);
VSource1(7 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-8);
when others => -- 16
VSource1(TRiscoWord'high-1 downto 16):=Source1(TRiscoWord'high-17 downto 0);
VSource1(15 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-16);
end case;
return VSource1;
end function RLA_F;
---------------------------------------------
-- Shift Right Logical Carry
-- 0-> C-> |b31 -> b0|
-- Diss. Risco, 3.4.1 d) O carry comporta-se como bit 32
-- Generic
function SRLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Cy;
VSource1(VSource1'high-1 downto 0):=Source1;
VSource2((VSource2'high-to_integer(unsigned(FT2))) downto 0):=VSource1(VSource1'high downto to_integer(unsigned(FT2)));
VSource2(VSource2'high downto (VSource2'high-to_integer(unsigned(FT2))+1)):=(others => '0');
return VSource2;
end function SRLCg_F;
--
-- Original (only 1,2,4,8,16)
function SRLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Cy;
VSource1(VSource1'high-1 downto 0):=Source1;
case to_integer(unsigned(FT2)) is
when 1 =>
VSource2(VSource2'high-1 downto 0):=VSource1(VSource1'high downto 1);
VSource2(VSource2'high):='0';
when 2 =>
VSource2(VSource2'high-2 downto 0):=VSource1(VSource1'high downto 2);
VSource2(VSource2'high downto VSource2'high-1):=(others => '0');
when 4 =>
VSource2(VSource2'high-4 downto 0):=VSource1(VSource1'high downto 4);
VSource2(VSource2'high downto VSource2'high-3):=(others => '0');
when 8 =>
VSource2(VSource2'high-8 downto 0):=VSource1(VSource1'high downto 8);
VSource2(VSource2'high downto VSource2'high-7):=(others => '0');
when others => --16
VSource2(VSource2'high-16 downto 0):=VSource1(VSource1'high downto 16);
VSource2(VSource2'high downto VSource2'high-15):=(others => '0');
end case;
return VSource2;
end function SRLC_F;
---------------------------------------------
-- Shift Left Logical Carry
-- C <-|b31 <- b0| <-0
-- Diss. Risco, 3.4.1 d) O carry comporta-se como bit 32
-- Generic
function SLLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Cy;
VSource1(VSource1'high-1 downto 0):=Source1;
VSource2((VSource2'high) downto to_integer(unsigned(FT2))):=VSource1(VSource1'high-to_integer(unsigned(FT2)) downto 0);
VSource2((to_integer(unsigned(FT2))-1) downto 0):=(others => '0');
return VSource2;
end function SLLCg_F;
--
-- Original (only 1,2,4,8,16)
function SLLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Cy;
VSource1(VSource1'high-1 downto 0):=Source1;
case to_integer(unsigned(FT2)) is
when 1 =>
VSource2(VSource2'high downto 1):=VSource1(VSource1'high-1 downto 0);
VSource2(0):='0';
when 2 =>
VSource2(VSource2'high downto 2):=VSource1(VSource1'high-2 downto 0);
VSource2(1 downto 0):=(others => '0');
when 4 =>
VSource2(VSource2'high downto 4):=VSource1(VSource1'high-4 downto 0);
VSource2(3 downto 0):=(others => '0');
when 8 =>
VSource2(VSource2'high downto 8):=VSource1(VSource1'high-8 downto 0);
VSource2(7 downto 0):=(others => '0');
when others => --16
VSource2(VSource2'high downto 16):=VSource1(VSource1'high-16 downto 0);
VSource2(15 downto 0):=(others => '0');
end case;
return VSource2;
end function SLLC_F;
---------------------------------------------
-- Shift Right Arithmetical Carry
-- 0-> C-> |b31 -> b0|
-- Diss. Risco, 3.4.1 d) O carry comporta-se como bit 32
-- Generic
function SRACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Source1(Source1'high);
VSource1(VSource1'high-1):=Cy;
VSource1(VSource1'high-2 downto 0):=Source1(Source1'high-1 downto 0);
VSource2(VSource2'high-to_integer(unsigned(FT2))-1 downto 0):=VSource1(VSource1'high-1 downto to_integer(unsigned(FT2)));
VSource2(VSource2'high-1 downto VSource2'high-to_integer(unsigned(FT2))):=(others => VSource1(VSource1'high));
VSource2(VSource2'high):=VSource1(VSource1'high);
 
VSourceR:=VSource2(VSource2'high-1)&VSource2(VSource2'high)&VSource2(VSource2'high-2 downto 0);
return VSourceR;
end function SRACg_F;
--
-- Original (only 1,2,4,8,16)
function SRAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Source1(Source1'high);
VSource1(VSource1'high-1):=Cy;
VSource1(VSource1'high-2 downto 0):=Source1(Source1'high-1 downto 0);
case to_integer(unsigned(FT2)) is
when 1 =>
VSource2(VSource2'high-2 downto 0):=VSource1(VSource1'high-1 downto 1);
VSource2(VSource2'high-1):=VSource1(VSource1'high);
VSource2(VSource2'high):=VSource1(VSource1'high);
when 2 =>
VSource2(VSource2'high-3 downto 0):=VSource1(VSource1'high-1 downto 2);
VSource2(VSource2'high-1 downto VSource2'high-2):=(others => VSource1(VSource1'high));
VSource2(VSource2'high):=VSource1(VSource1'high);
when 4 =>
VSource2(VSource2'high-5 downto 0):=VSource1(VSource1'high-1 downto 4);
VSource2(VSource2'high-1 downto VSource2'high-4):=(others => VSource1(VSource1'high));
VSource2(VSource2'high):=VSource1(VSource1'high);
when 8 =>
VSource2(VSource2'high-9 downto 0):=VSource1(VSource1'high-1 downto 8);
VSource2(VSource2'high-1 downto VSource2'high-8):=(others => VSource1(VSource1'high));
VSource2(VSource2'high):=VSource1(VSource1'high);
when others => --16
VSource2(VSource2'high-17 downto 0):=VSource1(VSource1'high-1 downto 16);
VSource2(VSource2'high-1 downto VSource2'high-16):=(others => VSource1(VSource1'high));
VSource2(VSource2'high):=VSource1(VSource1'high);
end case;
VSourceR:=VSource2(VSource2'high-1)&VSource2(VSource2'high)&VSource2(VSource2'high-2 downto 0);
return VSourceR;
end function SRAC_F;
---------------------------------------------
-- Shift Left Arithmetical Carry
-- C <-|b31 <- b0| <-0
-- Diss. Risco, 3.4.1 d) O carry comporta-se como bit 32
-- Generic
function SLACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Source1(Source1'high);
VSource1(VSource1'high-1):=Cy;
VSource1(VSource1'high-2 downto 0):=Source1(Source1'high-1 downto 0);
VSource2(VSource2'high-1 downto to_integer(unsigned(FT2))):=VSource1(VSource1'high-1-to_integer(unsigned(FT2)) downto 0);
VSource2(to_integer(unsigned(FT2))-1 downto 0):=(others => '0');
VSource2(VSource2'high):=VSource1(VSource1'high);
VSourceR:=VSource2(VSource2'high-1)&VSource2(VSource2'high)&VSource2(VSource2'high-2 downto 0);
return VSourceR;
end function SLACg_F;
--
-- Original (only 1,2,4,8,16)
function SLAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Source1(Source1'high);
VSource1(VSource1'high-1):=Cy;
VSource1(VSource1'high-2 downto 0):=Source1(Source1'high-1 downto 0);
case to_integer(unsigned(FT2)) is
when 1 =>
VSource2(VSource2'high-1 downto 1):=VSource1(VSource1'high-2 downto 0);
VSource2(0):='0';
VSource2(VSource2'high):=VSource1(VSource1'high);
when 2 =>
VSource2(VSource2'high-1 downto 2):=VSource1(VSource1'high-3 downto 0);
VSource2(1 downto 0):=(others => '0');
VSource2(VSource2'high):=VSource1(VSource1'high);
when 4 =>
VSource2(VSource2'high-1 downto 4):=VSource1(VSource1'high-5 downto 0);
VSource2(3 downto 0):=(others => '0');
VSource2(VSource2'high):=VSource1(VSource1'high);
when 8 =>
VSource2(VSource2'high-1 downto 8):=VSource1(VSource1'high-9 downto 0);
VSource2(7 downto 0):=(others => '0');
VSource2(VSource2'high):=VSource1(VSource1'high);
when others => --16
VSource2(VSource2'high-1 downto 16):=VSource1(VSource1'high-17 downto 0);
VSource2(15 downto 0):=(others => '0');
VSource2(VSource2'high):=VSource1(VSource1'high);
end case;
VSourceR:=VSource2(VSource2'high-1)&VSource2(VSource2'high)&VSource2(VSource2'high-2 downto 0);
return VSourceR;
end function SLAC_F;
---------------------------------------------
-- Rotate Right Logical through carry
-- C-> |b31 -> b0| -> C
--
-- Generic
function RRLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Cy;
VSource1(VSource1'high-1 downto 0):=Source1;
VSource2(VSource2'high-to_integer(unsigned(FT2)) downto 0):=VSource1(VSource1'high downto to_integer(unsigned(FT2)));
VSource2(VSource2'high downto VSource2'high-to_integer(unsigned(FT2))+1):=VSource1(to_integer(unsigned(FT2))-1 downto 0);
return VSource2;
end function RRLCg_F;
--
-- Original (only 1,2,4,8,6)
function RRLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Cy;
VSource1(VSource1'high-1 downto 0):=Source1;
case to_integer(unsigned(FT2)) is
when 1 =>
VSource2(VSource2'high-1 downto 0):=VSource1(VSource1'high downto 1);
VSource2(VSource2'high):=VSource1(0);
when 2 =>
VSource2(VSource2'high-2 downto 0):=VSource1(VSource1'high downto 2);
VSource2(VSource2'high downto VSource2'high-1):=VSource1(1 downto 0);
when 4 =>
VSource2(VSource2'high-4 downto 0):=VSource1(VSource1'high downto 4);
VSource2(VSource2'high downto VSource2'high-3):=VSource1(3 downto 0);
when 8=>
VSource2(VSource2'high-8 downto 0):=VSource1(VSource1'high downto 8);
VSource2(VSource2'high downto VSource2'high-7):=VSource1(7 downto 0);
when others => -- 16
VSource2(VSource2'high-16 downto 0):=VSource1(VSource1'high downto 16);
VSource2(VSource2'high downto VSource2'high-15):=VSource1(15 downto 0);
end case;
return VSource2;
end function RRLC_F;
---------------------------------------------
-- Rotate Left Logical through carry
-- C <-|b31 <- b0| <-C
--
-- Generic
function RLLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Cy;
VSource1(VSource1'high-1 downto 0):=Source1;
VSource2(VSource2'high downto to_integer(unsigned(FT2))):=Source1(VSource1'high-to_integer(unsigned(FT2)) downto 0);
VSource2(to_integer(unsigned(FT2))-1 downto 0):=VSource1(VSource1'high downto VSource1'high-to_integer(unsigned(FT2))+1);
return VSource2;
end function RLLCg_F;
--
-- Original (only 1,2,4,8,6)
function RLLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(VSource1'high):=Cy;
VSource1(VSource1'high-1 downto 0):=Source1;
case to_integer(unsigned(FT2)) is
when 1 =>
VSource2(VSource2'high downto 1):=Source1(VSource1'high-1 downto 0);
VSource2(0):=VSource1(VSource1'high);
when 2 =>
VSource2(VSource2'high downto 2):=Source1(VSource1'high-2 downto 0);
VSource2(1 downto 0):=VSource1(VSource2'high downto VSource1'high-1);
when 4 =>
VSource2(VSource2'high downto 4):=Source1(VSource1'high-4 downto 0);
VSource2(3 downto 0):=VSource1(VSource2'high downto VSource1'high-3);
when 8=>
VSource2(VSource2'high downto 8):=Source1(VSource1'high-8 downto 0);
VSource2(7 downto 0):=VSource1(VSource2'high downto VSource1'high-7);
when others => -- 16
VSource2(VSource2'high downto 16):=Source1(VSource1'high-16 downto 0);
VSource2(15 downto 0):=VSource1(VSource2'high downto VSource1'high-15);
end case;
return VSource2;
end function RLLC_F;
---------------------------------------------
-- Rotate Right Arithmetical through carry
-- C-> |b30 -> b0| -> C
--
-- Generic
function RRACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(0):=Cy;
VSource1(VSource1'high downto 1):=Source1;
VSource2(VSource2'high-to_integer(unsigned(FT2))-1 downto 0):=VSource1(VSource1'high-1 downto to_integer(unsigned(FT2)));
VSource2(VSource2'high-1 downto VSource2'high-to_integer(unsigned(FT2))):=VSource1(to_integer(unsigned(FT2))-1 downto 0);
VSource2(VSource2'high):=VSource1(VSource1'high);
VSourceR:=VSource2(0) & VSource2(VSource2'high downto 1);
return VSourceR;
end function RRACg_F;
--
-- Original (only 1,2,4,8,6)
function RRAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(0):=Cy;
VSource1(VSource1'high downto 1):=Source1;
VSource2(VSource2'high):=VSource1(VSource1'high);
case to_integer(unsigned(FT2)) is
when 1 =>
VSource2(VSource2'high-2 downto 0):=VSource1(VSource1'high-1 downto 1);
VSource2(VSource2'high-1):=VSource1(0);
when 2 =>
VSource2(VSource2'high-3 downto 0):=VSource1(VSource1'high-1 downto 2);
VSource2(VSource2'high-1 downto VSource2'high-2):=VSource1(1 downto 0);
when 4 =>
VSource2(VSource2'high-5 downto 0):=VSource1(VSource1'high-1 downto 4);
VSource2(VSource2'high-1 downto VSource2'high-4):=VSource1(3 downto 0);
when 8=>
VSource2(VSource2'high-9 downto 0):=VSource1(VSource1'high-1 downto 8);
VSource2(VSource2'high-1 downto VSource2'high-8):=VSource1(7 downto 0);
when others => -- 16
VSource2(VSource2'high-17 downto 0):=VSource1(VSource1'high-1 downto 16);
VSource2(VSource2'high-1 downto VSource2'high-16):=VSource1(15 downto 0);
end case;
VSourceR:=VSource2(0) & VSource2(VSource2'high downto 1);
return VSourceR;
end function RRAC_F;
---------------------------------------------
-- Rotate Left Arithmetical through carry
-- C <-|b30 <- b0| <-C
--
-- Generic
function RLACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(0):=Cy;
VSource1(VSource1'high downto 1):=Source1;
VSource2(VSource2'high-1 downto to_integer(unsigned(FT2))):=VSource1(VSource1'high-1-to_integer(unsigned(FT2)) downto 0);
VSource2(to_integer(unsigned(FT2))-1 downto 0):=VSource1(VSource2'high-1 downto VSource1'high-to_integer(unsigned(FT2)));
VSource2(VSource2'high):=VSource1(VSource1'high);
VSourceR:=VSource2(0) & VSource2(VSource2'high downto 1);
return VSourceR;
end function RLACg_F;
--
-- Original (only 1,2,4,8,6)
function RLAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
begin
VSource1(0):=Cy;
VSource1(VSource1'high downto 1):=Source1;
VSource2(VSource2'high):=VSource1(VSource1'high);
case to_integer(unsigned(FT2)) is
when 1 =>
VSource2(VSource2'high-1 downto 1):=VSource1(VSource1'high-2 downto 0);
VSource2(0):=VSource1(VSource2'high-1);
when 2 =>
VSource2(VSource2'high-1 downto 2):=VSource1(VSource1'high-3 downto 0);
VSource2(1 downto 0):=VSource1(VSource2'high-1 downto VSource2'high-2);
when 4 =>
VSource2(VSource2'high-1 downto 4):=VSource1(VSource1'high-5 downto 0);
VSource2(3 downto 0):=VSource1(VSource2'high-1 downto VSource2'high-4);
when 8=>
VSource2(VSource2'high-1 downto 8):=VSource1(VSource1'high-9 downto 0);
VSource2(7 downto 0):=VSource1(VSource2'high-1 downto VSource2'high-8);
when others => -- 16
VSource2(VSource2'high-1 downto 16):=VSource1(VSource1'high-17 downto 0);
VSource2(15 downto 0):=VSource1(VSource2'high-1 downto VSource2'high-16);
end case;
VSourceR:=VSource2(0) & VSource2(VSource2'high downto 1);
return VSourceR;
end function RLAC_F;
end ud_package;
/rtl/riscompatible_core.vhd
0,0 → 1,239
-------------------------------------------------------------------------------------------------------------------
-- ____________ _____ ___________ ___________ ___________
-- |||| \ |||| | |||| | |||| | |||| |
-- ||||_____ | |||| | |||| _____| |||| _____| |||| __ |
-- ______|||| | |||| | |||| |_____ |||| | |||| |||| |
-- |||| / |||| | |||| | |||| | |||| |||| |
-- |||| ___ \ |||| | ||||_____ | |||| | |||| |||| |
-- |||| |||| | |||| | ______|||| | |||| |_____ |||| |||| |
-- |||| |||| | |||| | |||| | |||| | |||| |
-- ||||__||||__| ||||__| ||||________| ||||________| ||||________|mpatible Core
--
-- RISCOmpatible - Implementation Based on the Instruction Set developed in:
-- "[1] RISCO - Microprocessador RISC CMOS de 32 Bits",
-- by Alexandre Ambrozi Junqueira and Altamiro Amadeu Suzim, 1993.
-- http://hdl.handle.net/10183/21530
-- HDL code by Andre Borin Soares
--
-- Current Features: Harvard architecture, single clock phase, multicycle operation.
--
-- USE THIS CODE AT YOUR OWN RISK !
-- HDL code 'as is' without warranty. Author liable for nothing.
-------------------------------------------------------------------------------------------------------------------
-- Suffixes and prefixes used in the code:
-- _W - Wire
-- _R - Register
-- _F - Function
-- _O - Output
-- _I - Input
-- C_ - Constant
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
entity riscompatible_core is
generic
(
NumBitsProgramMemory : natural:=5;
NumBitsDataMemory : natural:=5;
NumBitsRegBank : natural:=5
);
port
(
Clk_I : in std_logic;
Reset_I : in std_logic;
PMem_Enable_O : out std_logic;
PMem_Write_O : out std_logic;
PMem_Address_O : out std_logic_vector(NumBitsProgramMemory-1 downto 0);
PMem_InputData_O : out TRiscoWord;
PMem_OutputData_I : in TRiscoWord;
DMem_Enable_O : out std_logic;
DMem_Write_O : out std_logic;
DMem_Address_O : out std_logic_vector(NumBitsDataMemory-1 downto 0);
DMem_InputData_O : out TRiscoWord;
DMem_OutputData_I : in TRiscoWord;
Int_I : in std_logic;
IntAck_O : out std_logic
);
end riscompatible_core;
-------------------------------------------------------------------------------------------------------------------
architecture behavioral of riscompatible_core is
---------------------------------------------
-- Registers
---------------------------------------------
signal PSW_W : TRiscoReg;
signal PC_W : TRiscoReg;
signal RUA_W : TRiscoReg;
signal RUB_W : TRiscoReg;
signal RDA_W : TRiscoReg;
signal RDB_W : TRiscoReg;
---------------------------------------------
-- Wires
---------------------------------------------
-- Register Bank Signals ------------------------------
signal RegBnk_Write_W : std_logic;
signal RegBnk_RegisterW_W : std_logic_vector(NumBitsRegBank - 1 downto 0);
signal RegBnk_Register1_W : std_logic_vector(NumBitsRegBank - 1 downto 0);
signal RegBnk_Register2_W : std_logic_vector(NumBitsRegBank - 1 downto 0);
signal RegBnk_InputData_W : TRiscoWord;
signal RegBkn_FT1_OutputDatai_W : TRiscoWord;
signal RegBkn_FT2_OutputDatai_W : TRiscoWord;
-- ULA Signals ----------------------------------------
alias ULA_Cy_I_W : std_logic is PSW_W.Data_O(4);
signal ULA_Cy_O_W : std_logic;
signal ULA_Ng_O_W : std_logic;
signal ULA_Ov_O_W : std_logic;
signal ULA_Zr_O_W : std_logic;
signal ULA_Function_W : std_logic_vector(4 downto 0);
signal ULA_Output_W : TRiscoWord;
-- UD Signals -----------------------------------------
alias UD_InputData_W : TRiscoWord is RDA_W.Data_O;
alias UD_ShiftAmount_W : std_logic_vector(4 downto 0) is RDB_W.Data_O(4 downto 0);
signal UD_OutputData_W : TRiscoWord;
signal UD_Function_W : std_logic_vector(4 downto 0);
alias UD_Cy_I_W : std_logic is PSW_W.Data_O(4);
signal UD_Cy_O_W : std_logic;
-------------------------------------------------------
begin
 
PMem_InputData_O <= (others => '0');
 
---------------------------------------------
-- Registers
---------------------------------------------
 
-- Flags
PSW1:reg generic map (NumBits => C_NumBitsWord) port map (Clk_I => Clk_I, Clr_I => PSW_W.Clr_I, Wen_I => PSW_W.Wen_I, Data_I => PSW_W.Data_I, Data_O => PSW_W.Data_O);
 
-- PC
PC1:reg generic map (NumBits => C_NumBitsWord) port map (Clk_I => Clk_I, Clr_I => PC_W.Clr_I, Wen_I => PC_W.Wen_I, Data_I => PC_W.Data_I, Data_O => PC_W.Data_O);
 
-- Ula Inputs
RUA1:reg generic map (NumBits => C_NumBitsWord) port map (Clk_I => Clk_I, Clr_I => RUA_W.Clr_I, Wen_I => RUA_W.Wen_I, Data_I => RUA_W.Data_I, Data_O => RUA_W.Data_O);
RUB1:reg generic map (NumBits => C_NumBitsWord) port map (Clk_I => Clk_I, Clr_I => RUB_W.Clr_I, Wen_I => RUB_W.Wen_I, Data_I => RUB_W.Data_I, Data_O => RUB_W.Data_O);
 
-- UD inputs
RDA1:reg generic map (NumBits => C_NumBitsWord) port map (Clk_I => Clk_I, Clr_I => RDA_W.Clr_I, Wen_I => RDA_W.Wen_I, Data_I => RDA_W.Data_I, Data_O => RDA_W.Data_O);
RDB1:reg generic map (NumBits => C_NumBitsWord) port map (Clk_I => Clk_I, Clr_I => RDB_W.Clr_I, Wen_I => RDB_W.Wen_I, Data_I => RDB_W.Data_I, Data_O => RDB_W.Data_O);
 
---------------------------------------------
-- Register Bank
---------------------------------------------
RegisterBank1: RegisterBank
generic map
(
NumBitsAddr => NumBitsRegBank,
DataWidth => 32
)
port map
(
Clk_I => Clk_I,
Enable_I => '1',
Write_I => RegBnk_Write_W,
RegisterW_I => RegBnk_RegisterW_W,
Register1_I => RegBnk_Register1_W,
Register2_I => RegBnk_Register2_W,
InputData_I => RegBnk_InputData_W,
FT1OutputData_O => RegBkn_FT1_OutputDatai_W,
FT2OutputData_O => RegBkn_FT2_OutputDatai_W
);
 
---------------------------------------------
-- ULA - Arithmetic Logic Unit
---------------------------------------------
Ula1: Ula
port map
(
Cy_I => ULA_Cy_I_W,
Source1_I => RUA_W.Data_O,
Source2_I => RUB_W.Data_O,
Function_I => ULA_Function_W,
Output_O => ULA_Output_W,
Cy_O => ULA_Cy_O_W,
Ov_O => ULA_Ov_O_W,
Zr_O => ULA_Zr_O_W,
Ng_O => ULA_Ng_O_W
);
 
---------------------------------------------
-- UD - Shift Unit
---------------------------------------------
UD1: UD
port map
(
InputData_I => UD_InputData_W,
ShiftAmount_I => UD_ShiftAmount_W,
OutputData_O => UD_OutputData_W,
Function_I => UD_Function_W,
Cy_I => UD_Cy_I_W,
Cy_O => UD_Cy_O_W
);
 
---------------------------------------------
-- Control and Signal Selectors
---------------------------------------------
SelectAndControl1 : select_and_control
generic map
(
NumBitsProgramMemory => NumBitsProgramMemory,
NumBitsDataMemory => NumBitsDataMemory,
NumBitsRegBank => NumBitsRegBank
)
port map
(
Clk_I => Clk_I,
Reset_I => Reset_I,
PMem_Enable_O => PMem_Enable_O,
PMem_Address_O => PMem_Address_O,
PMem_Write_O => PMem_Write_O,
PMem_OutputData_I => PMem_OutputData_I,
DMem_Enable_O => DMem_Enable_O,
DMem_Write_O => DMem_Write_O,
DMem_Address_O => DMem_Address_O,
DMem_InputData_O => DMem_InputData_O,
DMem_OutputData_I => DMem_OutputData_I,
RegBnk_Register1_O => RegBnk_Register1_W,
RegBnk_Register2_O => RegBnk_Register2_W,
RegBnk_RegisterW_O => RegBnk_RegisterW_W,
RegBnk_Write_O => RegBnk_Write_W,
RegBnk_InputData_O => RegBnk_InputData_W,
RegBnk_FT1_OutputData_I => RegBkn_FT1_OutputDatai_W,
RegBnk_FT2_OutputData_I => RegBkn_FT2_OutputDatai_W,
ULA_Function_O => ULA_Function_W,
ULA_Output_I => ULA_Output_W,
ULA_Ng_O_I => ULA_Ng_O_W,
ULA_Cy_O_I => ULA_Cy_O_W,
ULA_Ov_O_I => ULA_Ov_O_W,
ULA_Zr_O_I => ULA_Zr_O_W,
UD_Function_O => UD_Function_W,
UD_OutputData_I => UD_OutputData_W,
UD_Cy_O_I => UD_Cy_O_W,
RUA_Clr_O => RUA_W.Clr_I,
RUB_Clr_O => RUB_W.Clr_I,
RDA_Clr_O => RDA_W.Clr_I,
RDB_Clr_O => RDB_W.Clr_I,
RUA_Wen_O => RUA_W.Wen_I,
RUB_Wen_O => RUB_W.Wen_I,
RDA_Wen_O => RDA_W.Wen_I,
RDB_Wen_O => RDB_W.Wen_I,
RUA_Data_O => RUA_W.Data_I,
RUB_Data_O => RUB_W.Data_I,
RDA_Data_O => RDA_W.Data_I,
RDB_Data_O => RDB_W.Data_I,
PC_Clr_O => PC_W.Clr_I,
PC_Wen_O => PC_W.Wen_I,
PC_Data_I => PC_W.Data_O,
PC_Data_O => PC_W.Data_I,
PSW_Clr_O => PSW_W.Clr_I,
PSW_Wen_O => PSW_W.Wen_I,
PSW_Data_I => PSW_W.Data_O,
PSW_Data_O => PSW_W.Data_I,
Int_I => Int_I,
IntAck_O => IntAck_O
);
 
end behavioral;
/rtl/ud.vhd
0,0 → 1,46
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.riscompatible_package.all;
use work.ud_package.all;
-------------------------------------------------------------------------------------------------------------------
entity UD is
port
(
InputData_I : in TRiscoWord;
ShiftAmount_I : in std_logic_vector(4 downto 0);
OutputData_o : out TRiscoWord;
Function_I : in std_logic_vector(4 downto 0);
Cy_I : in std_logic;
Cy_O : out std_logic
);
end UD;
-------------------------------------------------------------------------------------------------------------------
architecture behavioral of UD is
signal OutputData_w : TRiscoWordPlusCarry;
begin
with Function_I select
OutputData_w <=
Cy_I & SRL_F(InputData_I,ShiftAmount_I) when C_SRL,
Cy_I & SLL_F(InputData_I,ShiftAmount_I) when C_SLL,
Cy_I & SRA_F(InputData_I,ShiftAmount_I) when C_SRA,
Cy_I & SLA_F(InputData_I,ShiftAmount_I) when C_SLA,
Cy_I & RRL_F(InputData_I,ShiftAmount_I) when C_RRL,
Cy_I & RLL_F(InputData_I,ShiftAmount_I) when C_RLL,
Cy_I & RRA_F(InputData_I,ShiftAmount_I) when C_RRA,
Cy_I & RLA_F(InputData_I,ShiftAmount_I) when C_RLA,
SRLC_F(InputData_I,ShiftAmount_I,Cy_I) when C_SRLC,
SLLC_F(InputData_I,ShiftAmount_I,Cy_I) when C_SLLC,
SRAC_F(InputData_I,ShiftAmount_I,Cy_I) when C_SRAC,
SLAC_F(InputData_I,ShiftAmount_I,Cy_I) when C_SLAC,
RRLC_F(InputData_I,ShiftAmount_I,Cy_I) when C_RRLC,
RLLC_F(InputData_I,ShiftAmount_I,Cy_I) when C_RLLC,
RRAC_F(InputData_I,ShiftAmount_I,Cy_I) when C_RRAC,
RLAC_F(InputData_I,ShiftAmount_I,Cy_I) when C_RLAC,
(others => '0') when others;
OutputData_O <= OutputData_w(OutputData_O'high downto 0);
Cy_O <= OutputData_w(OutputData_w'high);
end behavioral;
-------------------------------------------------------------------------------------------------------------------
/rtl/riscompatible_package.vhd
0,0 → 1,327
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------------------------------------
package riscompatible_package is
---------------------------------------------
constant C_NumBitsWord : integer:=32;
constant C_NumBitsRegBank : natural:=3;
subtype TRiscoWord is std_logic_vector(C_NumBitsWord-1 downto 0);
subtype TRiscoWordPlusCarry is std_logic_vector(C_NumBitsWord downto 0); -- Carry = bit 32
---------------------------------------------
-- Flags
---------------------------------------------
type TRiscoFlag is record
Clr_I : std_logic;
Wen_I : std_logic;
Data_I : std_logic;
Data_O : std_logic;
end record;
---------------------------------------------
-- Registers
---------------------------------------------
type TRiscoReg is record
Clr_I : std_logic;
Wen_I : std_logic;
Data_I : std_logic_vector(C_NumBitsWord-1 downto 0);
Data_O : std_logic_vector(C_NumBitsWord-1 downto 0);
end record;
---------------------------------------------
-- Instruction Types
---------------------------------------------
constant INST_ULA : std_logic_vector(1 downto 0):="00";
constant INST_MEM : std_logic_vector(1 downto 0):="10";
constant INST_JMP : std_logic_vector(1 downto 0):="01";
constant INST_SUB : std_logic_vector(1 downto 0):="11";
---------------------------------------------
-- Arithmetic Logical Instructions
---------------------------------------------
-- ALU
constant C_AND : std_logic_vector(4 downto 0):="01111";
constant C_OR : std_logic_vector(4 downto 0):="01110";
constant C_XOR : std_logic_vector(4 downto 0):="01101";
constant C_SUBRC : std_logic_vector(4 downto 0):="01011";
constant C_SUBRCNOT : std_logic_vector(4 downto 0):="01010";
constant C_SUBR : std_logic_vector(4 downto 0):="01001";
constant C_SUBRNC : std_logic_vector(4 downto 0):="01000";
constant C_SUBC : std_logic_vector(4 downto 0):="00111";
constant C_SUBCNOT : std_logic_vector(4 downto 0):="00110";
constant C_SUB : std_logic_vector(4 downto 0):="00101";
constant C_SUBNC : std_logic_vector(4 downto 0):="00100";
constant C_ADDCNOT : std_logic_vector(4 downto 0):="00011";
constant C_ADDC : std_logic_vector(4 downto 0):="00010";
constant C_ADD1 : std_logic_vector(4 downto 0):="00001";
constant C_ADD : std_logic_vector(4 downto 0):="00000";
-- UD
constant C_RLL : std_logic_vector(4 downto 0):="10000";
constant C_RLLC : std_logic_vector(4 downto 0):="10001";
constant C_RLA : std_logic_vector(4 downto 0):="10010";
constant C_RLAC : std_logic_vector(4 downto 0):="10011";
constant C_RRL : std_logic_vector(4 downto 0):="10100";
constant C_RRLC : std_logic_vector(4 downto 0):="10101";
constant C_RRA : std_logic_vector(4 downto 0):="10110";
constant C_RRAC : std_logic_vector(4 downto 0):="10111";
constant C_SLL : std_logic_vector(4 downto 0):="11000";
constant C_SLLC : std_logic_vector(4 downto 0):="11001";
constant C_SLA : std_logic_vector(4 downto 0):="11010";
constant C_SLAC : std_logic_vector(4 downto 0):="11011";
constant C_SRL : std_logic_vector(4 downto 0):="11100";
constant C_SRLC : std_logic_vector(4 downto 0):="11101";
constant C_SRA : std_logic_vector(4 downto 0):="11110";
constant C_SRAC : std_logic_vector(4 downto 0):="11111";
-- NOT PRESENT (PG 101,PG 220,PG 234): C_ADD1, C_ADDCNOT, C_SUBCNOT, C_SUBNC, C_SUBRNC, C_SUBRCNOT
-- PRESENT ON PG 136
---------------------------------------------
-- Memory Access Instructions
---------------------------------------------
constant C_LD : std_logic_vector(4 downto 0):="00000";
constant C_LDPRI : std_logic_vector(4 downto 0):="00111";
constant C_LDPOI : std_logic_vector(4 downto 0):="00101";
constant C_LDPOD : std_logic_vector(4 downto 0):="00100";
constant C_ST : std_logic_vector(4 downto 0):="10000";
constant C_STPRI : std_logic_vector(4 downto 0):="10111";
constant C_STPOI : std_logic_vector(4 downto 0):="10101";
constant C_STPOD : std_logic_vector(4 downto 0):="10100";
---------------------------------------------
-- Conditions
---------------------------------------------
constant C_TR : std_logic_vector(4 downto 0):="11111";
constant C_NS : std_logic_vector(4 downto 0):="10001";
constant C_CS : std_logic_vector(4 downto 0):="10010";
constant C_OS : std_logic_vector(4 downto 0):="10100";
constant C_ZS : std_logic_vector(4 downto 0):="11000";
constant C_GE : std_logic_vector(4 downto 0):="10011";
constant C_GT : std_logic_vector(4 downto 0):="10110";
constant C_EQ : std_logic_vector(4 downto 0):="11100";
constant C_FL : std_logic_vector(4 downto 0):="00000";
constant C_NN : std_logic_vector(4 downto 0):="00001";
constant C_NC : std_logic_vector(4 downto 0):="00010";
constant C_NO : std_logic_vector(4 downto 0):="00100";
constant C_NZ : std_logic_vector(4 downto 0):="01000";
constant C_LT : std_logic_vector(4 downto 0):="00011";
constant C_LE : std_logic_vector(4 downto 0):="00110";
constant C_NE : std_logic_vector(4 downto 0):="01100";
---------------------------------------------
-- Source Operands
---------------------------------------------
-- FT1 - Register number of source 1
-- FT2 - Register number of source 2
-- SS2 - Bit used to define format
-- Kp - Small constant, 11 bits, extends signal
-- Kgl - Large constant, 17 bits, extends signal
-- Kgh - Large constant, 16 bits, most significant part
constant FFS_DST_FT1_FT2 : std_logic_vector(2 downto 0):="000";
constant FFS_DST_FT1_Kp : std_logic_vector(2 downto 0):="001";
constant FFS_DST_R00_Kgl : std_logic_vector(2 downto 0):="010";--01X
constant FFS_DST_DST_Kgh : std_logic_vector(2 downto 0):="100";--10X
constant FFS_DST_DST_Kgl : std_logic_vector(2 downto 0):="110";--11X
---------------------------------------------
-- Specific Functions
---------------------------------------------
--- CONSTEXT calculation
function Kpe_F(Kp : std_logic_vector(10 downto 0)) return TRiscoWord;
function Kgl_F(Kg : std_logic_vector(16 downto 0)) return TRiscoWord;
function Kgh_F(Kg : std_logic_vector(16 downto 0)) return TRiscoWord;
---
function IsZero_F(Source : std_logic_vector) return std_logic;
---------------------------------------------
-- Components
---------------------------------------------
component riscompatible_core is
generic
(
NumBitsProgramMemory : Natural:=5;
NumBitsDataMemory : Natural:=5;
NumBitsRegBank : natural:=5
);
port
(
Clk_I : in std_logic;
Reset_I : in std_logic;
PMem_Enable_O : out std_logic;
PMem_Write_O : out std_logic;
PMem_Address_O : out std_logic_vector(NumBitsProgramMemory-1 downto 0);
PMem_InputData_O : out TRiscoWord;
PMem_OutputData_I : in TRiscoWord;
DMem_Enable_O : out std_logic;
DMem_Write_O : out std_logic;
DMem_Address_O : out std_logic_vector(NumBitsDataMemory-1 downto 0);
DMem_InputData_O : out TRiscoWord;
DMem_OutputData_I : in TRiscoWord;
Int_I : in std_logic;
IntAck_O : out std_logic
);
end component;
component RegisterBank is
generic
(
NumBitsAddr : natural:=4;
DataWidth : natural:=32
);
port
(
Clk_I : in std_logic;
Enable_I : in std_logic;
Write_I : in std_logic;
RegisterW_I : in std_logic_vector(NumBitsAddr-1 downto 0);
Register1_I : in std_logic_vector(NumBitsAddr-1 downto 0);
Register2_I : in std_logic_vector(NumBitsAddr-1 downto 0);
InputData_I : in std_logic_vector(DataWidth-1 downto 0);
FT1OutputData_O : out std_logic_vector(DataWidth-1 downto 0);
FT2OutputData_O : out std_logic_vector(DataWidth-1 downto 0)
);
end component;
component Ula is
port
(
Cy_I : in std_logic;
Source1_I : in TRiscoWord;
Source2_I : in TRiscoWord;
Function_I : in std_logic_vector(4 downto 0);
Output_O : out TRiscoWord;
Cy_O : out std_logic;
Ov_O : out std_logic;
Zr_O : out std_logic;
Ng_O : out std_logic
);
end component;
component UD is
port
(
InputData_I : in TRiscoWord;
ShiftAmount_I : in std_logic_vector(4 downto 0);
OutputData_o : out TRiscoWord;
Function_I : in std_logic_vector(4 downto 0);
Cy_I : in std_logic;
Cy_O : out std_logic
);
end component;
component select_and_control is
generic
(
NumBitsProgramMemory : Natural:=5;
NumBitsDataMemory : Natural:=5;
NumBitsRegBank : natural:=5
);
port
(
Clk_I : in std_logic;
Reset_I : in std_logic;
PMem_Enable_O : out std_logic;
PMem_Address_O : out std_logic_vector(NumBitsProgramMemory - 1 downto 0);
PMem_Write_O : out std_logic;
PMem_OutputData_I : in TRiscoWord;
DMem_Enable_O : out std_logic;
DMem_Write_O : out std_logic;
DMem_Address_O : out std_logic_vector(NumBitsDataMemory - 1 downto 0);
DMem_InputData_O : out TRiscoWord;
DMem_OutputData_I : in TRiscoWord;
RegBnk_Register1_O : out std_logic_vector(NumBitsRegBank - 1 downto 0);
RegBnk_Register2_O : out std_logic_vector(NumBitsRegBank - 1 downto 0);
RegBnk_RegisterW_O : out std_logic_vector(NumBitsRegBank - 1 downto 0);
RegBnk_Write_O : out std_logic;
RegBnk_InputData_O : out TRiscoWord;
RegBnk_FT1_OutputData_I : in TRiscoWord;
RegBnk_FT2_OutputData_I : in TRiscoWord;
ULA_Function_O : out std_logic_vector(4 downto 0);
ULA_Output_I : in TRiscoWord;
ULA_Ng_O_I : in std_logic;
ULA_Cy_O_I : in std_logic;
ULA_Ov_O_I : in std_logic;
ULA_Zr_O_I : in std_logic;
UD_Function_O : out std_logic_vector(4 downto 0);
UD_OutputData_I : in TRiscoWord;
UD_Cy_O_I : in std_logic;
RUA_Clr_O : out std_logic;
RUB_Clr_O : out std_logic;
RDA_Clr_O : out std_logic;
RDB_Clr_O : out std_logic;
RUA_Wen_O : out std_logic;
RUB_Wen_O : out std_logic;
RDA_Wen_O : out std_logic;
RDB_Wen_O : out std_logic;
RUA_Data_O : out std_logic_vector(C_NumBitsWord - 1 downto 0);
RUB_Data_O : out std_logic_vector(C_NumBitsWord - 1 downto 0);
RDA_Data_O : out std_logic_vector(C_NumBitsWord - 1 downto 0);
RDB_Data_O : out std_logic_vector(C_NumBitsWord - 1 downto 0);
PC_Clr_O : out std_logic;
PC_Wen_O : out std_logic;
PC_Data_I : in std_logic_vector(C_NumBitsWord - 1 downto 0);
PC_Data_O : out std_logic_vector(C_NumBitsWord - 1 downto 0);
PSW_Clr_O : out std_logic;
PSW_Wen_O : out std_logic;
PSW_Data_I : in std_logic_vector(C_NumBitsWord - 1 downto 0);
PSW_Data_O : out std_logic_vector(C_NumBitsWord - 1 downto 0);
Int_I : in std_logic;
IntAck_O : out std_logic
);
end component;
component reg is
generic
(
NumBits : Natural:=5
);
port
(
Clk_I : in std_logic;
Clr_I : in std_logic;
Wen_I : in std_logic;
Data_I : in std_logic_vector (NumBits-1 downto 0);
Data_O : out std_logic_vector (NumBits-1 downto 0)
);
end component;
end package;
package body riscompatible_package is
---------------------------------------------
-- Implementation of functions
---------------------------------------------
-- Extends signal of Kp
function Kpe_F(Kp : std_logic_vector(10 downto 0)) return TRiscoWord is
variable VKpe : TRiscoWord;
begin
VKpe(10 downto 0):=Kp;
VKpe(TRiscoWord'high downto 11):=(others=>Kp(10));
return VKpe;
end function Kpe_F;
---------------------------------------------
-- Extends signal of Kg
function Kgl_F(Kg : std_logic_vector(16 downto 0)) return TRiscoWord is
variable VKgl : TRiscoWord;
begin
VKgl(16 downto 0):=Kg;
VKgl(TRiscoWord'high downto 17):=(others=>Kg(16));
return VKgl;
end function Kgl_F;
---------------------------------------------
-- Kg go to high order bits; low order bits receive the signal extension of Kg
function Kgh_F(Kg : std_logic_vector(16 downto 0)) return TRiscoWord is
variable VKgh : TRiscoWord;
begin
VKgh(31 downto 16):=Kg(15 downto 0);
VKgh(15 downto 0):=(others=>Kg(16));
return VKgh;
end function Kgh_F;
---------------------------------------------
-- Set if word is equal to zero
function IsZero_F(Source : std_logic_vector) return std_logic is
variable counter : integer range Source'range;
variable accumulator : std_logic:='0';
begin
for counter in 0 to Source'high loop
accumulator:=accumulator or Source(counter);
end loop;
return (not accumulator);
end function IsZero_F;
end riscompatible_package;
-------------------------------------------------------------------------------------------------------------------
/rtl/memory.vhd
0,0 → 1,66
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.riscompatible_package.all;
-- synopsys translate_off;
use std.textio.all;
use ieee.std_logic_textio.all;
-- synopsys translate_on;
-------------------------------------------------------------------------------------------------------------------
entity Memory is
generic
(
-- synopsys translate_off;
FileName : String:="dummie.txt";
-- synopsys translate_on;
NumBitsAddr : natural:=4;
DataWidth : natural:=32
);
port
(
Clk_I : in std_logic;
Enable_I : in std_logic;
Write_I : in std_logic;
Address_I : in std_logic_vector(NumBitsAddr-1 downto 0);
InputData_I : in std_logic_vector(DataWidth-1 downto 0);
OutputData_O : out std_logic_vector(DataWidth-1 downto 0)
);
end Memory;
-------------------------------------------------------------------------------------------------------------------
architecture behavioral of Memory is
-- synopsys translate_off;
file arq_in_0 : TEXT open READ_MODE is FileName;
-- synopsys translate_on;
type TMemory is array (natural range <> ) of TRiscoWord;
signal Memory : TMemory (2**NumBitsAddr-1 downto 0) := (others => (others=>'Z'));
begin
 
process (Clk_I,Address_I)
-- synopsys translate_off;
variable file_line : LINE := NULL;
variable dvalue : std_logic_vector(31 downto 0);
variable counter,i : integer:=0;
-- synopsys translate_on;
begin
if Clk_I'event and Clk_I = '1' then
if (Enable_I = '1') then
if (Write_I = '1') then
Memory(to_integer(unsigned(Address_I))) <= InputData_I;
end if;
-- synopsys translate_off;
else
while not endfile(arq_in_0) loop
readline(arq_in_0, file_line); --read line of file
Hread(file_line,dvalue); --extract value from line
Memory(counter)<=dvalue;
counter:=counter+1;
end loop;
-- synopsys translate_on;
end if;
OutputData_O <= Memory(to_integer(unsigned(Address_I)));
end if;
end process;
 
end behavioral;
-------------------------------------------------------------------------------------------------------------------
/rtl/data_sel.vhd
0,0 → 1,22
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
entity data_sel is
port
(
DMEM_OutputData_I : in TRiscoWord;
GPIO_OutputData_I : in TRiscoWord;
OutputData_Vld_I : in std_logic;
MSPC_OutputData_O : out TRiscoWord
);
end data_sel;
-------------------------------------------------------------------------------------------------------------------
architecture ark1 of data_sel is
begin
MSPC_OutputData_O <= DMEM_OutputData_I when OutputData_Vld_I = '0' else
GPIO_OutputData_I;
end ark1;
-------------------------------------------------------------------------------------------------------------------
/rtl/riscompatible.vhd
0,0 → 1,225
-------------------------------------------------------------------------------------------------------------------
-- ____________ _____ ___________ ___________ ___________
-- |||| \ |||| | |||| | |||| | |||| |
-- ||||_____ | |||| | |||| _____| |||| _____| |||| __ |
-- ______|||| | |||| | |||| |_____ |||| | |||| |||| |
-- |||| / |||| | |||| | |||| | |||| |||| |
-- |||| ___ \ |||| | ||||_____ | |||| | |||| |||| |
-- |||| |||| | |||| | ______|||| | |||| |_____ |||| |||| |
-- |||| |||| | |||| | |||| | |||| | |||| |
-- ||||__||||__| ||||__| ||||________| ||||________| ||||________|mpatible
--
-- RISCOmpatible - Implementation Based on the Instruction Set developed in:
-- "[1] RISCO - Microprocessador RISC CMOS de 32 Bits",
-- by Alexandre Ambrozi Junqueira and Altamiro Amadeu Suzim, 1993.
-- http://hdl.handle.net/10183/21530
-- HDL code by Andre Borin Soares
--
-- Current Features: Harvard architecture, single clock phase, multicycle operation.
--
-- USE THIS CODE AT YOUR OWN RISK !
-- HDL code 'as is' without warranty. Author liable for nothing.
-------------------------------------------------------------------------------------------------------------------
-- Suffixes and prefixes used in the code:
-- _W - Wire
-- _R - Register
-- _F - Function
-- _O - Output
-- _I - Input
-- C_ - Constant
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
entity riscompatible is
generic
(
NumBitsProgramMemory : Natural:=5;
NumBitsDataMemory : Natural:=5;
NumBitsRegBank : natural:=5;
NumBitsInputPorts : natural:=2;
NumBitsOutputPorts : natural:=2
);
port
(
Clk_I : in std_logic;
Reset_I : in std_logic;
Int_I : in std_logic;
IntAck_O : out std_logic;
InputPorts_I : in std_logic_vector(NumBitsInputPorts-1 downto 0);
OutputPorts_O : out std_logic_vector(NumBitsOutputPorts-1 downto 0)
);
end riscompatible;
-------------------------------------------------------------------------------------------------------------------
architecture behavioral of riscompatible is
---------------------------------------------
-- Wires
---------------------------------------------
-- Program Memory Signals -----------------------------
signal PMem_Enable_W : std_logic;
signal PMem_Write_W : std_logic;
signal PMem_Address_W : std_logic_vector(NumBitsProgramMemory-1 downto 0);
signal PMem_InputData_W : TRiscoWord;
signal PMem_OutputData_W : TRiscoWord;
-- Data Memory Signals --------------------------------
signal DMem_Enable_W : std_logic;
signal DMem_Write_W : std_logic;
signal DMem_Address_W : std_logic_vector(NumBitsDataMemory-1 downto 0);
signal DMem_InputData_W : TRiscoWord;
signal DMem_OutputData_W : TRiscoWord;
-------------------------------------------------------
signal GPIO_OutputData_W : TRiscoWord;
signal MSPC_OutputData_W : TRiscoWord;
signal OutputData_Vld_W : std_logic;
-------------------------------------------------------
component GPIO is
generic
(
NumBitsAddr : natural:=1;
NumBitsInputPorts : natural:=2;
NumBitsOutputPorts : natural:=2
);
port
(
Clk_I : in std_logic;
Enable_I : in std_logic;
Write_I : in std_logic;
Address_I : in std_logic_vector(NumBitsAddr-1 downto 0);
InputData_I : in std_logic_vector(C_NumBitsWord-1 downto 0);
OutputData_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
OutputData_Vld_O : out std_logic;
InputPorts_I : in std_logic_vector(NumBitsInputPorts-1 downto 0);
OutputPorts_O : out std_logic_vector(NumBitsOutputPorts-1 downto 0)
);
end component;
component Memory is
generic
(
FileName : String:="dummy.txt";
NumBitsAddr : natural:=4;
DataWidth : natural:=32
);
port
(
Clk_I : in std_logic;
Enable_I : in std_logic;
Write_I : in std_logic;
Address_I : in std_logic_vector(NumBitsAddr-1 downto 0);
InputData_I : in std_logic_vector(DataWidth-1 downto 0);
OutputData_O : out std_logic_vector(DataWidth-1 downto 0)
);
end component;
component data_sel is
port
(
DMEM_OutputData_I : in TRiscoWord;
GPIO_OutputData_I : in TRiscoWord;
OutputData_Vld_I : in std_logic;
MSPC_OutputData_O : out TRiscoWord
);
end component;
begin
 
---------------------------------------------
-- Program Memory
---------------------------------------------
u_Program_Memory: Memory
generic map
(
FileName => "../../bench/program.txt",
NumBitsAddr => NumBitsProgramMemory,
DataWidth => 32
)
port map
(
Clk_I => Clk_I,
Enable_I => PMem_Enable_W,
Write_I => PMem_Write_W,
Address_I => PMem_Address_W,
InputData_I => PMem_InputData_W,
OutputData_O => PMem_OutputData_W
);
 
---------------------------------------------
-- Data Memory
---------------------------------------------
u_Data_Memory: Memory
generic map
(
FileName => "../../bench/data.txt",
NumBitsAddr => NumBitsDataMemory-1,
DataWidth => 32
)
port map
(
Clk_I => Clk_I,
Enable_I => DMem_Enable_W,
Write_I => DMem_Write_W,
Address_I => DMem_Address_W(NumBitsDataMemory-2 downto 0),
InputData_I => DMem_InputData_W,
OutputData_O => DMem_OutputData_W
);
 
---------------------------------------------
-- Risco Core
---------------------------------------------
u_Riscompatible_Core: Riscompatible_Core
generic map
(
NumBitsProgramMemory => NumBitsProgramMemory,
NumBitsDataMemory => NumBitsDataMemory,
NumBitsRegBank => NumBitsRegBank
)
port map
(
Clk_I => Clk_I,
Reset_I => Reset_I,
PMem_Enable_O => PMem_Enable_W,
PMem_Write_O => PMem_Write_W,
PMem_Address_O => PMem_Address_W,
PMem_InputData_O => PMem_InputData_W,
PMem_OutputData_I => PMem_OutputData_W,
DMem_Enable_O => DMem_Enable_W,
DMem_Write_O => DMem_Write_W,
DMem_Address_O => DMem_Address_W,
DMem_InputData_O => DMem_InputData_W,
DMem_OutputData_I => MSPC_OutputData_W,
Int_I => Int_I,
IntAck_O => IntAck_O
);
---------------------------------------------
-- GPIO
---------------------------------------------
u_GPIO: GPIO
generic map
(
NumBitsAddr => NumBitsDataMemory,
NumBitsInputPorts => NumBitsInputPorts,
NumBitsOutputPorts => NumBitsOutputPorts
)
port map
(
Clk_I => Clk_I,
Enable_I => DMem_Enable_W,
Write_I => DMem_Write_W,
Address_I => DMem_Address_W,
InputData_I => DMem_InputData_W,
OutputData_O => GPIO_OutputData_W,
OutputData_Vld_O => OutputData_Vld_W,
InputPorts_I => InputPorts_I,
OutputPorts_O => OutputPorts_O
);
u_data_sel: data_sel
port map
(
DMEM_OutputData_I => DMEM_OutputData_W,
GPIO_OutputData_I => GPIO_OutputData_W,
OutputData_Vld_I => OutputData_Vld_W,
MSPC_OutputData_O => MSPC_OutputData_W
);
 
end behavioral;
/rtl/reg.vhd
0,0 → 1,33
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------------------------------------------
entity reg is
generic
(
NumBits : Natural:=5
);
port
(
Clk_I : in std_logic;
Clr_I : in std_logic;
Wen_I : in std_logic;
Data_I : in std_logic_vector (NumBits-1 downto 0);
Data_O : out std_logic_vector (NumBits-1 downto 0)
);
end reg;
-------------------------------------------------------------------------------------------------------------------
architecture ark1 of reg is
begin
process (Clk_I)
variable Data_v : std_logic_vector (Numbits-1 downto 0);
begin
if rising_edge(Clk_I) then
if Clr_I = '1' then
Data_v := (others => '0');
elsif Wen_I = '1' then
Data_v := Data_i;
end if;
end if;
Data_O <= Data_v;
end process;
end ark1;
/rtl/gpio.vhd
0,0 → 1,78
-------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.riscompatible_package.all;
-------------------------------------------------------------------------------------------------------------------
entity GPIO is
generic
(
NumBitsAddr : natural:=1;
NumBitsInputPorts : natural:=2;
NumBitsOutputPorts : natural:=2
);
port
(
Clk_I : in std_logic;
Enable_I : in std_logic;
Write_I : in std_logic;
Address_I : in std_logic_vector(NumBitsAddr-1 downto 0);
InputData_I : in std_logic_vector(C_NumBitsWord-1 downto 0);
OutputData_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
OutputData_Vld_O : out std_logic;
InputPorts_I : in std_logic_vector(NumBitsInputPorts-1 downto 0);
OutputPorts_O : out std_logic_vector(NumBitsOutputPorts-1 downto 0)
);
end GPIO;
-------------------------------------------------------------------------------------------------------------------
architecture behavioral of GPIO is
function num_bits(num_io : integer) return integer is
begin
case num_io is
when 0|1|2 =>
return (1);
when 3|4 =>
return (2);
when 5|6|7|8 =>
return (3);
when 9|10|11|12|13|14|15|16 =>
return (4);
when 17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32 =>
return (5);
when others => return (-1);
end case;
 
end function num_bits;
begin
 
process (Clk_I,Address_I)
begin
if Clk_I'event and Clk_I = '1' then
if (Enable_I = '1') then
if (Write_I = '1') and Address_I(Address_I'high)='1' then
if to_integer(unsigned(Address_I(Address_I'high-1 downto 0))) * C_NumBitsWord < NumBitsOutputPorts then
for i in 0 to 31 loop
if to_integer(unsigned(Address_I(Address_I'high-1 downto 0))) * C_NumBitsWord + i < NumBitsOutputPorts then
OutputPorts_O(i) <= InputData_I(i);
end if;
end loop;
end if;
end if;
end if;
if Address_I(Address_I'high)='1' then
OutputData_Vld_O <= '1';
else
OutputData_Vld_O <= '0';
end if;
for i in 0 to 31 loop
if to_integer(unsigned(Address_I(Address_I'high-1 downto 0))) * C_NumBitsWord + i < NumBitsInputPorts then
OutputData_O(i) <= InputPorts_I(i);
else
OutputData_O(i) <= '0';
end if;
end loop;
end if;
end process;
 
end behavioral;
-------------------------------------------------------------------------------------------------------------------
/sim/modelsim/wave_riscompatible.do
0,0 → 1,171
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Basic Signals}
add wave -noupdate -format Logic /riscompatible_tb/reset_w
add wave -noupdate -format Logic /riscompatible_tb/clk_w
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/int_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/intmask_v
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/interruptenable_w
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/intack_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/intack_v
add wave -noupdate -divider GPIO
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/outputports_o
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/inputports_i
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_gpio/outputdata_o
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/mspc_outputdata_w
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/dmem_address_w
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_gpio/outputports_o
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_gpio/inputports_i
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_gpio/address_i
add wave -noupdate -divider <NULL>
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_cy_o_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_ng_o_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_ov_o_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_zr_o_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_function_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/aps_v
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/psw_data_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/psw_wen_o
add wave -noupdate -format Literal -label PSW -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/psw1/data_o
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/phase_v
add wave -noupdate -format Literal -label PC -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/pc1/data_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/pc_data_i
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/pmem_outputdata_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/pmem_address_w
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_data_memory/outputdata_o
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/t1_t0_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/c4_c0_v
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/f1_f0_ss2_v
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/dst_v
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/ft1_v
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/ft2_v
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/condition_v
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/enable_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/write_i
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/phase_v
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/regbnk_register1_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/regbnk_register2_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/register1_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/register2_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/ft1outputdata_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/ft2outputdata_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/rda_wen_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/rua_data_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/rdb_wen_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/rub_data_o
add wave -noupdate -format Literal -label RUA -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/rua1/data_o
add wave -noupdate -format Literal -label RUB -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/rub1/data_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/pc_data_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/pc_wen_o
add wave -noupdate -divider ULA
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/source1_i
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/source2_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/function_i
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/output_o
add wave -noupdate -divider UD
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/inputdata_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/shiftamount_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/function_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/outputdata_o
add wave -noupdate -divider DMEM
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/dmem_address_w
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_data_memory/address_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_data_memory/inputdata_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_data_memory/outputdata_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_data_memory/write_i
add wave -noupdate -divider RegBank
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/register1_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/register2_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/registerw_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/inputdata_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/write_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/enable_i
add wave -noupdate -divider Debug
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/phase_v
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/pmem_address_o
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/pmem_outputdata_i
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/t1_t0_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/c4_c0_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/f1_f0_ss2_v
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/ft1_v
add wave -noupdate -format Literal -radix decimal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/kp_v
add wave -noupdate -format Literal -radix decimal /riscompatible_tb/riscompatible1/u_riscompatible_core/regbkn_ft1_outputdatai_w
add wave -noupdate -format Literal -radix decimal /riscompatible_tb/riscompatible1/u_riscompatible_core/regbkn_ft2_outputdatai_w
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_cy_o_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_ng_o_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_ov_o_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_zr_o_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/condition_v
add wave -noupdate -divider Controle
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/dmem_write_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/dmem_address_w
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/dmem_inputdata_o
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/dmem_outputdata_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/pmem_address_o
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_program_memory/outputdata_o
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/phase_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/t1_t0_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/c4_c0_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/f1_f0_ss2_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/ft1_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/ft2_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/kp_v
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/dst_v
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_function_o
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/ula_output_i
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/psw_data_o
add wave -noupdate -format Literal -label RUA.data_o -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/rua_w.data_o
add wave -noupdate -format Literal -label RUB.data_o -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/rub_w.data_o
add wave -noupdate -format Literal -label data_o -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/pc_w.data_o
add wave -noupdate -divider RegisterBank
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/register1_i
add wave -noupdate -format Literal -radix unsigned /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/register2_i
add wave -noupdate -format Literal -radix hexadecimal -expand /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/memory
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/ft1outputdata_o
add wave -noupdate -format Literal -radix hexadecimal /riscompatible_tb/riscompatible1/u_riscompatible_core/registerbank1/ft2outputdata_o
add wave -noupdate -divider {Registers & Flags}
add wave -noupdate -format Literal -expand /riscompatible_tb/riscompatible1/u_riscompatible_core/psw_w
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/rda_w
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/rdb_w
add wave -noupdate -format Literal -expand /riscompatible_tb/riscompatible1/u_riscompatible_core/rua_w
add wave -noupdate -format Literal -expand /riscompatible_tb/riscompatible1/u_riscompatible_core/rub_w
add wave -noupdate -format Literal -radix unsigned -expand /riscompatible_tb/riscompatible1/u_riscompatible_core/pc_w
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/selectandcontrol1/p_select_and_control/phase_v
add wave -noupdate -divider Memories
add wave -noupdate -format Literal -label {Program Memory} -radix hexadecimal /riscompatible_tb/riscompatible1/u_program_memory/memory
add wave -noupdate -format Literal -label {Data Memory} -radix hexadecimal -expand /riscompatible_tb/riscompatible1/u_data_memory/memory
add wave -noupdate -divider ULA
add wave -noupdate -format Literal -radix decimal /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/source1_i
add wave -noupdate -format Literal -radix decimal /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/source2_i
add wave -noupdate -format Literal -radix decimal /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/output_o
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/function_i
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/ng_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/zr_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/ov_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/cy_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/ula1/cy_i
add wave -noupdate -divider UD
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/outputdata_o
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/function_i
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/outputdata_w
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/cy_o
add wave -noupdate -format Logic /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/cy_i
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/shiftamount_i
add wave -noupdate -format Literal /riscompatible_tb/riscompatible1/u_riscompatible_core/ud1/inputdata_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{R8 = R2 and R3} {1120 ns} 1} {{Cursor 8} {1460 ns} 1} {{Cursor 3} {1534 ns} 0}
configure wave -namecolwidth 197
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1319 ns} {1721 ns}
/sim/modelsim/compila.do
0,0 → 1,17
vlib work
vcom -93 ../../rtl/riscompatible_package.vhd
vcom -93 ../../rtl/reg.vhd
vcom -93 ../../rtl/select_and_control.vhd
vcom -93 ../../rtl/ud_package.vhd
vcom -93 ../../rtl/ud.vhd
vcom -93 ../../rtl/ula.vhd
vcom -93 ../../rtl/memory.vhd
vcom -93 ../../rtl/gpio.vhd
vcom -93 ../../rtl/registerbank.vhd
vcom -93 ../../rtl/riscompatible_core.vhd
vcom -93 ../../rtl/riscompatible.vhd
vcom -93 ../../bench/riscompatible_tb.vhd
vsim riscompatible_tb
do wave_riscompatible.do
run 100 us
 

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