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https://opencores.org/ocsvn/rise/rise/trunk
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/rise/trunk/vhdl
- from Rev 148 to Rev 151
- ↔ Reverse comparison
Rev 148 → Rev 151
/dmem.vhd
File deleted
/rise_pack.vhd
16,7 → 16,6
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package RISE_PACK is |
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constant CLK_FREQ : integer := 50000000; |
constant ARCHITECTURE_WIDTH : integer := 16; |
constant REGISTER_COUNT : integer := 16; |
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/memctrl.vhd
0,0 → 1,185
-- File: dmem.vhd |
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter |
-- Created: 2006-11-29 |
-- Last updated: 2006-11-29 |
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-- Description: |
-- Entity for accessing data memory. |
------------------------------------------------------------------------------- |
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library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.numeric_std.all; |
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use WORK.RISE_PACK.all; |
use WORK.CONF_PACK.all; |
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entity memctrl is |
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port ( |
clk : in std_logic; |
reset : in std_logic; |
wr_enable : in std_logic; |
addr : in MEM_ADDR_T; |
data_in : in MEM_DATA_T; |
data_out : out MEM_DATA_T; |
uart_txd : out std_logic; |
uart_rxd : in std_logic); |
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end memctrl; |
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architecture memctrl_rtl of memctrl is |
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component dmem |
port ( |
addr : in std_logic_vector(DMEM_ADDR_WIDTH-1 downto 0); |
clk : in std_logic; |
data_in : in MEM_DATA_T; |
data_out : out MEM_DATA_T; |
wr_enable : in std_logic); |
end component; |
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component sc_uart is |
generic (ADDR_BITS : integer; |
CLK_FREQ : integer; |
BAUD_RATE : integer; |
TXF_DEPTH : integer; |
TXF_THRES : integer; |
RXF_DEPTH : integer; |
RXF_THRES : integer); |
port (CLK : in std_logic; |
RESET : in std_logic; |
ADDRESS : in std_logic_vector(addr_bits-1 downto 0); |
WR_DATA : in std_logic_vector(15 downto 0); |
RD, WR : in std_logic; |
RD_DATA : out std_logic_vector(15 downto 0); |
RDY_CNT : out unsigned(1 downto 0); |
TXD : out std_logic; |
RXD : in std_logic; |
NCTS : in std_logic; |
NRTS : out std_logic); |
end component; |
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signal uart_address : std_logic_vector(1 downto 0); |
signal uart_wr_data :std_logic_vector(15 downto 0); |
signal uart_rd : std_logic; |
signal uart_wr : std_logic; |
signal uart_rd_data : std_logic_vector(15 downto 0); |
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signal uart_txd_sig : std_logic; |
signal uart_rxd_sig : std_logic; |
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signal mem_addr : std_logic_vector (11 downto 0); |
signal mem_data_in :MEM_DATA_T; |
signal mem_data_out :MEM_DATA_T; |
signal mem_wr_enable: std_logic; |
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signal last_address_int : MEM_ADDR_T; |
signal last_address_next : MEM_ADDR_T; |
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signal rdy_cnt_sig : IEEE.NUMERIC_STD.unsigned(1 downto 0); |
begin -- dmem_rtl |
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-- Uart modul einbinden |
UART : sc_uart generic map ( |
ADDR_BITS => 2, |
CLK_FREQ => CLK_FREQ, |
BAUD_RATE => 115200, |
TXF_DEPTH => 2, |
TXF_THRES => 1, |
RXF_DEPTH => 2, |
RXF_THRES => 1 |
) |
port map( |
CLK => clk, |
RESET => reset, |
ADDRESS => uart_address(1 downto 0), |
WR_DATA => uart_wr_data, |
RD => uart_rd, |
WR => uart_wr, |
RD_DATA => uart_rd_data, |
RDY_CNT => rdy_cnt_sig, |
TXD => uart_txd_sig, |
RXD => uart_rxd_sig, |
NCTS => '0', |
NRTS => open |
); |
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DATA_MEM : dmem |
port map ( |
addr => mem_addr, |
clk => clk, |
din => mem_data_in, |
dout => mem_data_out, |
sinit => reset, |
we => mem_wr_enable); |
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uart_txd <= uart_txd_sig; |
uart_rxd_sig <= uart_rxd; |
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store_address: process (clk, reset) |
begin -- process data_out |
if reset='0' then |
last_address_int <= (others => '0'); |
elsif clk'event and clk='1' then |
last_address_int <= last_address_next; |
end if; |
end process store_address; |
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process (last_address_int, mem_data_out, uart_rd_data) |
begin |
if last_address_int = CONST_UART_STATUS_ADDRESS |
or last_address_int = CONST_UART_DATA_ADDRESS then |
data_out <= uart_rd_data; |
else |
data_out <= mem_data_out; |
end if; |
end process; |
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process (wr_enable, addr, data_in, uart_rd_data, mem_data_out) |
begin |
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mem_addr <= (others => '0'); |
mem_data_in <= (others => '0'); |
mem_wr_enable <= '0'; |
uart_address <= (others => '0'); |
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uart_wr <= '0'; |
uart_wr_data <= (others => '0'); |
uart_rd <= '0'; |
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last_address_next <= addr; |
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if addr = CONST_UART_STATUS_ADDRESS |
or addr = CONST_UART_DATA_ADDRESS then |
-- accessing UART |
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uart_address <= addr (1 downto 0); |
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if wr_enable = '1' then |
uart_wr <= '1'; |
uart_wr_data <= data_in; |
else |
uart_rd <= '1'; |
end if; |
else |
-- accessing data memory |
mem_addr <= addr(11 downto 0); |
mem_data_in <= data_in; |
mem_wr_enable <= wr_enable; |
end if; |
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end process; |
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end memctrl_rtl; |
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