URL
https://opencores.org/ocsvn/robust_axi2ahb/robust_axi2ahb/trunk
Subversion Repositories robust_axi2ahb
Compare Revisions
- This comparison shows the changes necessary to convert path
/robust_axi2ahb/trunk/src
- from Rev 2 to Rev 4
- ↔ Reverse comparison
Rev 2 → Rev 4
/base/def_axi2ahb_static.txt
1,4 → 1,6
|
SWAP MODEL_NAME AXI2AHB bridge |
|
VERIFY ((DATA_BITS==32) || (DATA_BITS==64)) |
|
GROUP AXI_A is { |
/base/axi2ahb.v
1,6 → 1,6
|
INCLUDE def_axi2ahb.txt |
OUTFILE PREFIX_axi2ahb.v |
OUTFILE PREFIX.v |
|
CHECK CONST(#FFD) |
CHECK CONST(PREFIX) |
9,7 → 9,7
CHECK CONST(ID_BITS) |
CHECK CONST(CMD_DEPTH) |
|
module PREFIX_axi2ahb (PORTS); |
module PREFIX (PORTS); |
|
input clk; |
input reset; |
43,7 → 43,7
|
|
CREATE axi2ahb_cmd.v |
PREFIX_axi2ahb_cmd PREFIX_axi2ahb_cmd( |
PREFIX_cmd PREFIX_cmd( |
.clk(clk), |
.reset(reset), |
.AWGROUP_AXI_A(AWGROUP_AXI_A), |
62,7 → 62,7
|
|
CREATE axi2ahb_ctrl.v |
PREFIX_axi2ahb_ctrl PREFIX_axi2ahb_ctrl( |
PREFIX_ctrl PREFIX_ctrl( |
.clk(clk), |
.reset(reset), |
.GROUP_AHB(GROUP_AHB), |
81,8 → 81,8
|
|
CREATE axi2ahb_wr_fifo.v |
PREFIX_axi2ahb_wr_fifo |
PREFIX_axi2ahb_wr_fifo( |
PREFIX_wr_fifo |
PREFIX_wr_fifo( |
.clk(clk), |
.reset(reset), |
.WGROUP_AXI_W(WGROUP_AXI_W), |
99,8 → 99,8
|
|
CREATE axi2ahb_rd_fifo.v |
PREFIX_axi2ahb_rd_fifo |
PREFIX_axi2ahb_rd_fifo( |
PREFIX_rd_fifo |
PREFIX_rd_fifo( |
.clk(clk), |
.reset(reset), |
.RGROUP_AXI_R(RGROUP_AXI_R), |
/base/axi2ahb_cmd.v
1,9 → 1,9
|
OUTFILE PREFIX_axi2ahb_cmd.v |
OUTFILE PREFIX_cmd.v |
|
INCLUDE def_axi2ahb.txt |
|
module PREFIX_axi2ahb_cmd (PORTS); |
module PREFIX_cmd (PORTS); |
|
input clk; |
input reset; |
/base/axi2ahb_ctrl.v
1,8 → 1,8
|
INCLUDE def_axi2ahb.txt |
OUTFILE PREFIX_axi2ahb_ctrl.v |
OUTFILE PREFIX_ctrl.v |
|
module PREFIX_axi2ahb_ctrl (PORTS); |
module PREFIX_ctrl (PORTS); |
|
|
input clk; |
/base/axi2ahb_rd_fifo.v
1,8 → 1,8
|
INCLUDE def_axi2ahb.txt |
OUTFILE PREFIX_axi2ahb_rd_fifo.v |
OUTFILE PREFIX_rd_fifo.v |
|
module PREFIX_axi2ahb_rd_fifo (PORTS); |
module PREFIX_rd_fifo (PORTS); |
|
parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst |
parameter RESP_SLVERR = 2'b10; |
/base/def_axi2ahb.txt
1,12 → 1,12
|
INCLUDE def_axi2ahb_static.txt |
|
SWAP #FFD #1 ## flip-flop delay |
SWAP #FFD #1 ## flip-flop delay |
|
SWAP PREFIX soc ## prefix for all modules and file names |
SWAP.USER PREFIX axi2ahb ##Prefix for all modules and file names |
|
SWAP CMD_DEPTH 4 ## number of AXI command FIFO |
SWAP.USER CMD_DEPTH 4 ##Number of AXI command FIFO |
|
SWAP ADDR_BITS 24 ## AXI and AHB address bits |
SWAP DATA_BITS 32 ## AXI and AHB data bits |
SWAP ID_BITS 4 ## AXI ID bits |
SWAP.USER ADDR_BITS 24 ##AXI and AHB address bits |
SWAP.USER DATA_BITS 32 ##AXI and AHB data bits |
SWAP.USER ID_BITS 4 ##AXI ID bits |
/base/axi2ahb_wr_fifo.v
1,8 → 1,8
|
INCLUDE def_axi2ahb.txt |
OUTFILE PREFIX_axi2ahb_wr_fifo.v |
OUTFILE PREFIX_wr_fifo.v |
|
module PREFIX_axi2ahb_wr_fifo (PORTS); |
module PREFIX_wr_fifo (PORTS); |
|
parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst |
parameter RESP_SLVERR = 2'b10; |