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URL https://opencores.org/ocsvn/robust_axi2apb/robust_axi2apb/trunk

Subversion Repositories robust_axi2apb

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    /robust_axi2apb
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/trunk/src/base/def_axi2apb.txt
27,7 → 27,7
//// ////
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb_static.txt
INCLUDE def_axi2apb_static.txt
 
SWAP #FFD #1 ## flip-flop delay
 
/trunk/src/base/axi2apb.v
27,7 → 27,7
//// ////
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb.v
 
ITER SX
39,18 → 39,18
port GROUP_APB_AXI;
//apb slaves
IFDEF TRUE(SLAVE_NUM==1)
port GROUP_APB3;
ELSE TRUE(SLAVE_NUM==1)
output penable;
output pwrite;
output [ADDR_BITS-1:0] paddr;
output [31:0] pwdata;
 
output pselSX;
input [31:0] prdataSX;
input preadySX;
input pslverrSX;
ENDIF TRUE(SLAVE_NUM==1)
 
 
 
113,21 → 113,6
STOMP ,
);
CREATE axi2apb_mux.v
PREFIX_axi2apb_mux PREFIX_axi2apb_mux(
.clk(clk),
.reset(reset),
.cmd_addr(cmd_addr),
.psel(psel),
.prdata(prdata),
.pready(pready),
.pslverr(pslverr),
.pselSX(pselSX),
.preadySX(preadySX),
.pslverrSX(pslverrSX),
.prdataSX(prdataSX),
STOMP ,
);
 
CREATE axi2apb_ctrl.v
144,7 → 129,25
.pwrite(pwrite),
.pready(pready)
);
 
IFDEF TRUE(SLAVE_NUM>1)
CREATE axi2apb_mux.v
PREFIX_axi2apb_mux PREFIX_axi2apb_mux(
.clk(clk),
.reset(reset),
.cmd_addr(cmd_addr),
.psel(psel),
.prdata(prdata),
.pready(pready),
.pslverr(pslverr),
.pselSX(pselSX),
.preadySX(preadySX),
.pslverrSX(pslverrSX),
.prdataSX(prdataSX),
STOMP ,
);
ENDIF TRUE(SLAVE_NUM>1)
 
endmodule
 
/trunk/src/base/axi2apb_cmd.v
51,9 → 51,15
wire cmd_push;
wire cmd_pop;
wire cmd_empty;
wire cmd_full;
reg read;
wire wreq, rreq;
wire wack, rack;
wire AERR;
assign wreq = AWVALID;
assign rreq = ARVALID;
assign wack = AWVALID & AWREADY;

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