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URL https://opencores.org/ocsvn/robust_fir/robust_fir/trunk

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    /robust_fir/trunk/src
    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/gen/bintree_adder.v File deleted \ No newline at end of file
/gen/def_bintree_adder.txt File deleted
/gen/def_delayN.txt File deleted
/gen/prgen_bintree_adder.v
0,0 → 1,100
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE prgen_bintree_adder_INPUT_NUM.v
 
STARTDEF
SWAP ADD_STAGES LOG2(INPUT_NUM)
ENDDEF
 
CHECK CONST (INPUT_NUM)
 
ITER TX INPUT_NUM
ITER SX ADD_STAGES
 
module prgen_bintree_adder_INPUT_NUM(PORTS);
 
parameter BITS = 0;
 
input clk;
input reset;
input [BITS-1:0] data_inTX;
output [BITS-1+ADD_STAGES:0] data_out;
input valid_in;
output valid_out;
LOOP EX INPUT_NUM EXPR(2^LOG2(INPUT_NUM))
wire [BITS-1:0] data_inEX = {BITS{1'b0}}; //complete power of 2 input data
ENDLOOP EX
STOMP LINE
wire [BITS-1:0] sum_stageADD_STAGES_TX;
 
LOOP TX EXPR(2^LOG2(INPUT_NUM))
assign sum_stageADD_STAGES_TX = data_inTX;
ENDLOOP TX
LOOP SX ADD_STAGES
ITER AX EXPR(2^SX)
reg [BITS-1+EXPR(ADD_STAGES-SX):0] sum_stageSX_AX;
ENDITER AX
ENDLOOP SX
wire valid_dSX;
wire valid_dADD_STAGES;
CREATE prgen_delayN.v DEFCMD(SWAP DELAY 1)
prgen_delay1 #(1) delay_validSX(clk, reset, valid_dSX, valid_dEXPR(SX+1));
assign valid_d0 = valid_in;
assign valid_out = valid_dADD_STAGES;
LOOP SX ADD_STAGES
ITER AX EXPR(2^SX)
always @(posedge clk or posedge reset)
if (reset)
begin
sum_stageSX_AX <= #FFD {BITS+EXPR(ADD_STAGES-SX){1'b0}};
end
else
STOMP NEWLINE
if (valid_dEXPR(ADD_STAGES-SX-1))
begin
sum_stageSX_AX <= #FFD sum_stageEXPR(SX+1)_EXPR(2*AX) + sum_stageEXPR(SX+1)_EXPR(2*AX+1);
end
ENDITER AX
ENDLOOP SX
assign data_out = sum_stage0_0;
endmodule
 
 
/gen/prgen_delayN.v
27,11 → 27,19
//// ////
//////////////////////////////////////////////////////////////////##>
 
ITER DX DELAY
 
OUTFILE prgen_NAME.v
INCLUDE def_delayN.txt
 
STARTDEF
IFDEF CLKEN
SWAP NAME delayDELAY_en
ELSE CLKEN
SWAP NAME delayDELAY
ENDIF CLKEN
ENDDEF
ITER DX DELAY
module prgen_NAME(PORTS);
parameter WIDTH = 1;
/base/def_fir_top.txt File deleted
/base/fir_parallel.v
71,8 → 71,8
end
 
//Pipline the output additions
CREATE bintree_adder.v DEFCMD(SWAP INPUT_NUM COEFF_NUM)
bintree_adder_COEFF_NUM #(MULT_BITS) bintree_adder(
CREATE prgen_bintree_adder.v DEFCMD(SWAP INPUT_NUM COEFF_NUM)
prgen_bintree_adder_COEFF_NUM #(MULT_BITS) prgen_bintree_adder(
.clk(clk),
.reset(reset),
.data_inCX(multCX),
/base/fir_Nserial.v
83,8 → 83,8
ENDLOOP MX
 
//Pipline the output additions
CREATE bintree_adder.v DEFCMD(SWAP INPUT_NUM MAC_NUM)
bintree_adder_MAC_NUM #(SON_DOUT) bintree_adder
CREATE prgen_bintree_adder.v DEFCMD(SWAP INPUT_NUM MAC_NUM)
prgen_bintree_adder_MAC_NUM #(SON_DOUT) prgen_bintree_adder
(
.clk(clk),
.reset(reset),
/base/fir.v
31,6 → 31,8
OUTFILE fir_NAME.v
INCLUDE def_fir.txt
 
LIST firlist_NAME.txt
 
ITER CX COEFF_NUM
 
## Expected RobustVerilog parameters:
/base/fir_top.v
0,0 → 1,11
 
STARTDEF
SWAP FIR(WW,XX,YY,ZZ) CREATE.USER fir.v DEFCMD(SWAP.USER ORDER WW) DEFCMD(SWAP.USER COEFF_BITS XX) DEFCMD(SWAP.USER DIN_BITS YY) DEFCMD(SWAP.USER MAC_NUM ZZ)
ENDDEF
 
 
##FIR(ORDER, COEFF_BITS, DIN_BITS, MAC_NUM)
FIR(3, 12, 8, 4) ##parallel
FIR(3, 16, 24, 2) ##Nserial
FIR(7, 8, 32, 1) ##Serial
 
/base/def_fir_Nserial.txt
38,7 → 38,7
SWAP SON_DOUT EXPR(MULT_BITS+SON_STAGES) ##bits of son output
SWAP ADD_DOUT EXPR(SON_DOUT+LOG2(MAC_NUM)) ##bits of adder output
 
VERIFY(EXPR(COEFF_NUM%MAC_NUM)==0) else MAC number (multiplayers) must be a division of the coefficient number (FIR order+1)
VERIFY(MAC_NUM>1) else MAC number must be larger than 1 (try using fir_serial.v)
VERIFY(MAC_NUM<COEFF_NUM) else MAC number must be smaller than coefficient number (try using fir_parallel.v)
VERIFY(EXPR(COEFF_NUM%MAC_NUM)==0) ##MAC number (multiplayers) must be a division of the coefficient number (FIR order+1)
VERIFY(MAC_NUM>1) ##MAC number must be larger than 1 (try using fir_serial.v)
VERIFY(MAC_NUM<COEFF_NUM) ##MAC number must be smaller than coefficient number (try using fir_parallel.v)
 
/base/def_fir.txt
27,12 → 27,13
//// ////
//////////////////////////////////////////////////////////////////##>
 
REQUIRE(1.3)
REQUIRE(1.4)
 
INCLUDE def_fir_basic.txt
 
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay
 
 
##check all input parameters have been given
CHECK CONST(ORDER)
CHECK CONST(COEFF_BITS)
/base/def_fir_basic.txt
27,12 → 27,15
//// ////
//////////////////////////////////////////////////////////////////##>
 
 
SWAP.GLOBAL MODEL_NAME FIR
 
##check all input parameters have been given
CHECK CONST(ORDER)
CHECK CONST(COEFF_BITS)
CHECK CONST(DIN_BITS)
 
SWAP NAME MAC_NUM_TOPO ##name of top module and file
SWAP NAME MAC_NUM_TOPO ##name of top module and file
SWAP INPUT_BITS DIN_BITS_COEFF_BITS ##input sizes
SWAP TOPO ORDER_INPUT_BITS ##topology
 

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