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URL https://opencores.org/ocsvn/rs232_interface/rs232_interface/trunk

Subversion Repositories rs232_interface

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  • This comparison shows the changes necessary to convert path 
    /rs232_interface
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/trunk/uart.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Create Date: 21:12:48 05/06/2010
-- Module Name: UART - Behavioral
-- Creation Date: 21:12:48 05/06/2010
-- Module Name: RS232/UART Interface - Behavioral
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
41,11 → 41,11
-- Signals
signal rx_fsm : state;
signal tx_fsm : state;
signal clock_en : std_logic;
signal clock_en : std_logic;
 
-- Data Temp
signal data_cnt_tx : std_logic_vector(2 downto 0) := "000";
signal data_cnt_rx : std_logic_vector(2 downto 0) := "000";
signal data_cnt_rx : std_logic_vector(2 downto 0);
signal rx_data_tmp : std_logic_vector(7 downto 0);
signal tx_data_tmp : std_logic_vector(7 downto 0);
 
57,11 → 57,11
if clk'event and clk = '1' then
-- Normal Operation
if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then
clock_en <= '1';
counter := 0;
clock_en <= '1';
counter := 0;
else
clock_en <= '0';
counter := counter + 1;
clock_en <= '0';
counter := counter + 1;
end if;
-- Reset condition
if rst = '1' then
76,8 → 76,8
if clk'event and clk = '1' then
if clock_en = '1' then
-- Default values
tx_end <= '0';
tx <= uart_idle;
tx_end <= '0';
tx <= uart_idle;
-- FSM description
case tx_fsm is
-- Wait to transfer data
84,29 → 84,29
when idle =>
-- Send Init Bit
if tx_req = '1' then
tx <= uart_start;
tx <= uart_start;
tx_data_tmp <= tx_data;
tx_fsm <= data;
tx_fsm <= data;
data_cnt_tx <= (others=>'1');
end if;
-- Data receive
when data =>
tx <= tx_data_tmp(0);
tx <= tx_data_tmp(0);
if data_cnt_tx = 0 then
tx_fsm <= stop1;
data_cnt_tx <= (others=>'1');
else
tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);
data_cnt_tx <= data_cnt_tx - 1;
data_cnt_tx <= data_cnt_tx - 1;
end if;
-- End of communication
when stop1 =>
-- Send Stop Bit
tx <= uart_idle;
tx <= uart_idle;
tx_fsm <= stop2;
when stop2 =>
-- Send Stop Bit
tx_end <= '1';
tx_end <= '1';
tx <= uart_idle;
tx_fsm <= idle;
-- Invalid States
115,7 → 115,7
-- Reset condition
if rst = '1' then
tx_fsm <= idle;
tx_data_tmp <= (others=>'0');
tx_data_tmp <= (others=>'0');
end if;
end if;
end if;
126,7 → 126,7
if clk'event and clk = '1' then
if clock_en = '1' then
-- Default values
rx_ready <= '0';
rx_ready <= '0';
-- FSM description
case rx_fsm is
-- Wait to transfer data
153,9 → 153,10
-- Reset condition
if rst = '1' then
rx_fsm <= idle;
rx_ready <= '0';
rx_data <= (others=>'0');
data_cnt_rx <= (others=>'0');
rx_ready <= '0';
rx_data <= (others=>'0');
data_cnt_rx <= (others=>'0');
rx_data_tmp <= (others=>'0');
end if;
end if;
end if;

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