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URL https://opencores.org/ocsvn/rsa_512/rsa_512/trunk

Subversion Repositories rsa_512

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  • This comparison shows the changes necessary to convert path 
    /rsa_512
    from Rev 8 to Rev 9
    ↔ Reverse comparison
  •

Rev 8 → Rev 9

/trunk/rtl/montgomery_mult.vhd
47,24 → 47,24
architecture Behavioral of montgomery_mult is
 
component montgomery_step is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
busy : out std_logic;
b_req : out std_logic;
a_out : out std_logic_vector(15 downto 0);
 
c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
stop : in std_logic
);
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
busy : out std_logic;
b_req : out std_logic;
a_out : out std_logic_vector(15 downto 0);
 
c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
stop : in std_logic
);
end component;
 
component fifo_512_bram
119,7 → 119,7
 
signal wr_fifofeed : std_logic;
 
type state_type is (rst_fifos,wait_start, process_data, dump_feed);
type state_type is (rst_fifos, wait_start, process_data, dump_feed);
signal state, next_state : state_type;
signal reg_busy : std_logic;
signal reset_fifos : std_logic;
318,21 → 318,21
end if;
 
when process_data =>
wr_fifofeed <= valid_mid(7);
wr_fifofeed <= valid_mid(7);
if(valid_in = '1') then
wr_en <= '1';
wr_en <= '1';
end if;
--Miramos si hay que volver a meter datos a la b
if(empty_feedback = '0' and reg_busy = '0') then
read_fifo_feedback <= '1';
next_state <= dump_feed;
read_fifo_feedback <= '1';
next_state <= dump_feed;
next_count_feedback <= x"0000";
end if;
 
--Si ya hemos sobrepasado el limite paramos y volvemos a la espera
if( count > x"23") then
if( count > x"23") then
next_state <= wait_start;
--y
--y
for i in 0 to 7 loop
stops(i) <= '1';
end loop;
340,30 → 340,30
end if;
 
--Vacia la fifo de feedback
when dump_feed =>
if(empty_feedback='0')
when dump_feed =>
if(empty_feedback = '0')
then
next_count_feedback <= count_feedback+1;
end if;
wr_fifofeed <= valid_mid(7);
read_fifo_feedback <= '1';
a_in <= fifo_out_feedback(48 downto 33);
n_in <= fifo_out_feedback(32 downto 17);
s_in <= fifo_out_feedback(16 downto 1);
f_valid <= fifo_out_feedback(0);
if(empty_feedback='1') then
next_state <= process_data;
wr_fifofeed <= valid_mid(7);
read_fifo_feedback <= '1';
a_in <= fifo_out_feedback(48 downto 33);
n_in <= fifo_out_feedback(32 downto 17);
s_in <= fifo_out_feedback(16 downto 1);
f_valid <= fifo_out_feedback(0);
if(empty_feedback = '1') then
next_state <= process_data;
 
end if;
if(count_feedback = x"22") then
read_fifo_feedback <= '0';
next_state <= process_data;
next_state <= process_data;
end if;
when rst_fifos =>
next_state <= wait_start;
reset_fifos <= '1';
when rst_fifos =>
next_state <= wait_start;
reset_fifos <= '1';
end case;
 
end process;
end Behavioral;
 
/trunk/rtl/pe.vhd
121,12 → 121,12
next_n_reg <= (others => '0');
next_prod_aj_bi <= (others => '0');
next_prod_nj_m <= (others => '0');
next_sum_1 <= (others =>'0');
next_sum_2 <= (others=>'0');
next_sum_1 <= (others => '0');
next_sum_2 <= (others => '0');
end if;
 
 
 
end process;
 
end Behavioral;
/trunk/rtl/pe_wrapper.vhd
111,27 → 111,27
 
process(clk, reset)
begin
if(clk='1' and clk'event) then
if(reset='1')then
m <= (others=> '0' );
if(clk = '1' and clk'event) then
 
if(reset = '1')then
m <= (others => '0' );
valid_m_reg <= '0';
else
m <= next_m;
m <= next_m;
valid_m_reg <= valid_m;
end if;
end if;
end process;
process(m_out,valid_m, valid_m_reg, m)
 
process(m_out, valid_m, valid_m_reg, m)
begin
m_val <= valid_m_reg;
if(valid_m = '1' and valid_m_reg ='0') then
m_val <= valid_m_reg;
if(valid_m = '1' and valid_m_reg = '0') then
next_m <= m_out;
else
next_m <= m;
end if;
end process;
 
end Behavioral;
 
/trunk/rtl/rsa_top.vhd
36,11 → 36,11
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
start_in : in std_logic;
x : in std_logic_vector(15 downto 0); -- estos 3 son x^y mod m
y : in std_logic_vector(15 downto 0);
m : in std_logic_vector(15 downto 0);
r_c : in std_logic_vector(15 downto 0); --constante de montgomery r^2 mod m
n_c : in std_logic_vector(15 downto 0); --constante necesaria en la multiplicacion
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic;
bit_size : in std_logic_vector(15 downto 0) --tamano bit del exponente y (log2(y))
49,21 → 49,29
 
architecture Behavioral of rsa_top is
 
component n_c_core
port (clk : in std_logic;
m_lsw : in std_logic_vector(15 downto 0);
ce : in std_logic;
n_c : out std_logic_vector(15 downto 0);
done : out std_logic
);
end component;
 
--Multiplicador de Montgomery que sera instanciado 2 veces
component montgomery_mult is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic -- es le valid out TODO : cambiar nombre
);
component montgomery_mult
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic -- es le valid out TODO : cambiar nombre
);
end component;
 
--Memoria para guardar el exponente y el modulo
110,9 → 118,22
signal bsize_reg, next_bsize_reg : std_logic_vector (15 downto 0);
signal write_b_n : std_logic_vector(0 downto 0);
 
signal n_c_o : std_logic_vector(15 downto 0);
signal n_c : std_logic_vector(15 downto 0);
signal n_c_load : std_logic;
 
begin
 
n_c1 : n_c_core
port map (
clk => clk,
m_lsw => m,
ce => start_in,
n_c => n_c_o,
done => n_c_load
);
 
 
mon_1 : montgomery_mult port map(
clk => clk,
reset => reset,
180,7 → 201,12
addr_n <= (others => '0');
bit_counter <= (others => '0');
bsize_reg <= (others => '0');
n_c <= (others => '0');
 
else
if(n_c_load = '1') then
n_c <= n_c_o;
end if;
state <= next_state;
n_c_reg <= next_n_c_reg;
w_numb <= next_w_numb;
427,69 → 453,69
end if;
if((bit_counter = x"0001") and addr_exp = "000000000")
then
next_state <= final_mult;
next_state <= final_mult;
next_count_input <= (others => '0');
next_addr_exp <= (others => '0');
next_addr_exp <= (others => '0');
end if;
end if;
when prepare_next =>
next_state <= transition;
 
when prepare_next =>
next_state <= transition;
next_count_input <= (others => '0');
fifo_1_rd <= '0';
fifo_1_rd <= '0';
 
when final_mult =>
next_count_input <= count_input+1;
 
if(count_input > 2) then
next_count_input <= (others => '0');
next_state <= prepare_final;
next_state <= prepare_final;
end if;
 
when prepare_final =>
 
if(count_input > x"0000")then
valid_in_mon_1 <= '1';
end if;
 
fifo_1_rd <= '1';
a_mon_1 <= fifo_out(15 downto 0);
 
a_mon_1 <= fifo_out(15 downto 0);
if(count_input = x"0001") then
b_mon_1 <= x"0001";
end if;
n_mon_1 <= n_out;
next_addr_n <= addr_n+1;
n_mon_1 <= n_out;
 
next_addr_n <= addr_n+1;
next_count_input <= count_input +1;
 
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = w_numb) then
next_state <= wait_final;
next_count_input <= (others =>'0');
next_state <= wait_final;
next_count_input <= (others => '0');
end if;
 
when wait_final =>
 
if(valid_out_mon_1 = '1') then
valid_out <= '1';
s <= s_out_mon_1;
next_state <= show_final;
valid_out <= '1';
s <= s_out_mon_1;
next_state <= show_final;
next_count_input <= count_input +1;
end if;
 
when show_final =>
valid_out <= '1';
s <= s_out_mon_1;
valid_out <= '1';
s <= s_out_mon_1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = x"20") then
valid_out <= '0';
next_state <= wait_start;
valid_out <= '0';
next_state <= wait_start;
end if;
 
end case;
 
end process;
 
end Behavioral;
/trunk/rtl/montgomery_step.vhd
234,22 → 234,22
 
mont_input_a <= reg_input_5(47 downto 32);
mont_input_n <= reg_input_5(31 downto 16);
mont_input_s <= reg_input_5(15 downto 0);
mont_input_s <= reg_input_5(15 downto 0);
 
if(counter = (x"22")) then
next_state <= wait_valid;
c_step <= '1';
reset_pe <= '1';
c_step <= '1';
reset_pe <= '1';
end if;
 
end case;
if(stop='1') then
 
if(stop = '1') then
next_state <= wait_valid;
--reset_fifo <= '1';
reset_pe <= '1';
reset_pe <= '1';
end if;
 
end process;
 
end Behavioral;

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