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URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

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  • This comparison shows the changes necessary to convert path 
    /rtf65002/trunk/rtl/verilog
    from Rev 20 to Rev 21
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  •

Rev 20 → Rev 21

/byte_jsl.v
37,6 → 37,16
dmiss <= `TRUE;
end
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_JSL2:
begin
radr <= {spage[31:8],sp[7:2]};
75,6 → 85,16
dmiss <= `TRUE;
end
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_JSL4:
begin
radr <= {spage[31:8],sp[7:2]};
113,6 → 133,16
dmiss <= `TRUE;
end
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_JSL6:
begin
radr <= {spage[31:8],sp[7:2]};
152,3 → 182,13
end
pc <= ir[39:8];
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/pla.v
47,3 → 47,13
res <= dat_i;
state <= IFETCH;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/byte_irq.v
25,6 → 25,7
//
BYTE_IRQ1:
if (ack_i) begin
ir <= 64'd0;
state <= BYTE_IRQ2;
retstate <= BYTE_IRQ2;
cyc_o <= 1'b0;
/byte_plp.v
55,3 → 55,13
nf <= dati[7];
state <= IFETCH;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/load.v
49,3 → 49,10
b <= dat_i;
state <= em ? BYTE_CALC : CALC;
end
else if (err_i) begin
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'd0;
state <= BUS_ERROR;
end
/byte_jsr.v
37,6 → 37,16
dmiss <= `TRUE;
end
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_JSR2:
begin
radr <= {spage[31:8],sp[7:2]};
76,6 → 86,16
dmiss <= `TRUE;
end
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
 
BYTE_JSR_INDX1:
if (ack_i) begin
117,8 → 137,9
end
BYTE_JSR_INDX3:
if (ack_i) begin
state <= BYTE_JMP_IND1;
retstate <= BYTE_JMP_IND1;
load_what <= `PC_70;
state <= LOAD_MAC1;
retstate <= LOAD_MAC1;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
136,3 → 157,13
dmiss <= `TRUE;
end
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/byte_rti.v
62,6 → 62,16
radr2LSB <= sp_inc[1:0];
state <= BYTE_RTI1;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_RTI1:
if (unCachedData) begin
cyc_o <= 1'b1;
91,6 → 101,16
pc[7:0] <= dati;
state <= BYTE_RTI3;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_RTI3:
if (unCachedData) begin
cyc_o <= 1'b1;
120,6 → 140,16
pc[15:8] <= dati;
state <= BYTE_RTI5;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_RTI5:
if (unCachedData) begin
cyc_o <= 1'b1;
149,6 → 179,16
pc[23:16] <= dati;
state <= BYTE_RTI7;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_RTI7:
if (unCachedData) begin
cyc_o <= 1'b1;
172,3 → 212,13
pc[31:24] <= dati;
state <= IFETCH;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/decode.v
75,8 → 75,8
begin
state <= IFETCH;
case(ir[23:20])
`ADD_RR: begin res <= rfoa + rfob; a <= rfoa; b <= rfob; end
`SUB_RR: begin res <= rfoa - rfob; a <= rfoa; b <= rfob; end
`ADD_RR: begin res <= rfoa + rfob + {31'b0,df&cf}; a <= rfoa; b <= rfob; end
`SUB_RR: begin res <= rfoa - rfob - {31'b0,df&~cf&|ir[19:16]}; a <= rfoa; b <= rfob; end
`AND_RR: begin res <= rfoa & rfob; a <= rfoa; b <= rfob; end // for bit flags
`OR_RR: begin res <= rfoa | rfob; a <= rfoa; b <= rfob; end
`EOR_RR: begin res <= rfoa ^ rfob; a <= rfoa; b <= rfob; end
100,8 → 100,8
`DEC_RR: begin res <= rfoa - 32'd1; pc <= pc + 32'd2; Rt <= ir[15:12]; end
`INC_RR: begin res <= rfoa + 32'd1; pc <= pc + 32'd2; Rt <= ir[15:12]; end
 
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; pc <= pc + 32'd3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; pc <= pc + 32'd3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end
109,14 → 109,14
`ASL_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pc + 32'd3; state <= CALC; end
`LSR_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pc + 32'd3; state <= CALC; end
 
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; pc <= pc + 32'd4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; pc <= pc + 32'd4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end
`ADD_IMM32: begin res <= rfoa + ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; a <= rfoa; b <= ir[47:16]; end
`SUB_IMM32: begin res <= rfoa - ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; a <= rfoa; b <= ir[47:16]; end
`ADD_IMM32: begin res <= rfoa + ir[47:16]; Rt <= ir[15:12] + {31'b0,df&cf}; pc <= pc + 32'd6; a <= rfoa; b <= ir[47:16]; end
`SUB_IMM32: begin res <= rfoa - ir[47:16]; Rt <= ir[15:12] - {31'b0,df&~cf&|ir[15:12]}; pc <= pc + 32'd6; a <= rfoa; b <= ir[47:16]; end
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end
129,7 → 129,8
begin
radr <= zpx32xy_address;
pc <= pc + 32'd3;
state <= LOAD1;
load_what <= `WORD_311;
state <= LOAD_MAC1;
end
`ORB_ZPX:
begin
138,13 → 139,15
radr <= zpx32_address[31:2];
radr2LSB <= zpx32_address[1:0];
pc <= pc + 32'd4;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`LDX_ABS,`LDY_ABS:
begin
radr <= ir[39:8];
pc <= pc + 32'd5;
state <= LOAD1;
load_what <= `WORD_311;
state <= LOAD_MAC1;
end
`ORB_ABS:
begin
153,13 → 156,15
radr <= ir[47:18];
radr2LSB <= ir[17:16];
pc <= pc + 32'd6;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`LDX_ABSY,`LDY_ABSX:
begin
radr <= absx32xy_address;
pc <= pc + 32'd6;
state <= LOAD1;
load_what <= `WORD_311;
state <= LOAD_MAC1;
end
`ORB_ABSX:
begin
168,7 → 173,8
radr <= absx32_address[31:2];
radr2LSB <= absx32_address[1:0];
pc <= pc + 32'd7;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ST_ZPX:
begin
248,13 → 254,15
Rt <= ir[19:16];
radr <= zpx32_address;
pc <= pc + 32'd4;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
begin
radr <= dp + rfoa + ir[23:12];
pc <= pc + 32'd3;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
begin
265,7 → 273,8
Rt <= ir[19:16];
pc <= pc + 32'd4;
radr <= dp + ir[31:20] + rfob;
state <= IX1;
load_what <= `IA_310;
state <= LOAD_MAC1;
end
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND,`ST_RIND:
begin
281,7 → 290,8
else begin
Rt <= ir[19:16];
pc <= pc + 32'd3;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
end
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
292,8 → 302,10
else
Rt <= ir[19:16];
pc <= pc + 32'd4;
isIY <= 1'b1;
radr <= dp + ir[31:20];
state <= IY1;
load_what <= `IA_310;
state <= LOAD_MAC1;
end
`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS:
begin
301,13 → 313,15
radr <= ir[47:16];
Rt <= ir[15:12];
pc <= pc + 32'd6;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
begin
radr <= ir[39:8];
pc <= pc + 32'd5;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX:
begin
315,13 → 329,15
radr <= ir[55:24] + rfob;
Rt <= ir[19:16];
pc <= pc + 32'd7;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
begin
radr <= ir[47:16] + rfob;
pc <= pc + 32'd6;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`CPX_IMM32:
begin
339,25 → 355,29
begin
radr <= dp + ir[23:12] + rfoa;
pc <= pc + 32'd3;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`CPY_ZPX:
begin
radr <= dp + ir[23:12] + rfoa;
pc <= pc + 32'd3;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`CPX_ABS:
begin
radr <= ir[39:8];
pc <= pc + 32'd5;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`CPY_ABS:
begin
radr <= ir[39:8];
pc <= pc + 32'd5;
state <= LOAD1;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`BRK:
begin
374,6 → 394,20
vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
state <= IRQ1;
end
`INT0,`INT1:
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc + 32'd2;
vect <= {vbr[31:9],ir[15:7],2'b00};
state <= IRQ1;
end
`JMP:
begin
pc[15:0] <= ir[23:8];
387,12 → 421,14
`JMP_IND:
begin
radr <= ir[39:8];
state <= JMP_IND1;
load_what <= `PC_310;
state <= LOAD_MAC1;
end
`JMP_INDX:
begin
radr <= ir[39:8] + x;
state <= JMP_IND1;
load_what <= `PC_310;
state <= LOAD_MAC1;
end
`JMP_RIND:
begin
487,11 → 523,13
`RTS,`RTL:
begin
radr <= isp;
state <= RTS1;
load_what <= `PC_310;
state <= LOAD_MAC1;
end
`RTI: begin
radr <= isp;
state <= RTI1;
load_what <= `SR_310;
state <= LOAD_MAC1;
end
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
begin
645,14 → 683,16
`PLP:
begin
radr <= isp;
state <= PLP1;
pc <= pc + 32'd1;
load_what <= `SR_310;
state <= LOAD_MAC1;
end
`PLA,`PLX,`PLY:
begin
radr <= isp;
isp <= isp_inc;
state <= PLA1;
load_what <= `WORD_311;
state <= LOAD_MAC1;
pc <= pc + 32'd1;
end
`POP:
660,10 → 700,23
Rt <= ir[15:12];
radr <= isp;
isp <= isp_inc;
state <= PLA1;
load_what <= `WORD_311;
state <= LOAD_MAC1;
pc <= pc + 32'd2;
end
default: // unimplemented opcode
pc <= pc + 32'd1;
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc + 32'd1;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc + 32'd1;
vect <= {vbr[31:9],9'd495,2'b00};
state <= IRQ1;
end
endcase
end
/php.v
41,4 → 41,14
dmiss <= `TRUE;
end
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/plp.v
61,3 → 61,13
radr <= isp_inc;
state <= IFETCH;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/byte_rts.v
51,6 → 51,16
pc[7:0] <= dati;
state <= BYTE_RTS3;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_RTS3:
if (unCachedData) begin
cyc_o <= 1'b1;
84,6 → 94,16
end
state <= BYTE_RTS5;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_RTS5:
if (ir[7:0]!=`RTL) begin
pc <= pc + 32'd1;
119,6 → 139,16
sp <= sp_inc;
state <= BYTE_RTS7;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_RTS7:
if (unCachedData) begin
cyc_o <= 1'b1;
142,8 → 172,19
pc[31:24] <= dati;
state <= BYTE_RTS9;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_RTS9:
begin
pc <= pc + 32'd1;
state <= IFETCH;
end
 
/rtf65002d.v
32,6 → 32,7
`define IRQ_VECT 34'h3FFFFFFF0
`define BRK_VECTNO 9'd0
`define SLP_VECTNO 9'd1
`define BYTE_RST_VECT 34'h00000FFFC
`define BYTE_NMI_VECT 34'h00000FFFA
`define BYTE_IRQ_VECT 34'h00000FFFE
 
373,7 → 374,25
`define BAZ 8'hC1
`define BXZ 8'hD1
`define BEQ_RR 8'hE2
`define INT0 8'hDC
`define INT1 8'hDD
 
`define NOTHING 4'd0
`define SR_70 4'd1
`define SR_310 4'd2
`define BYTE_70 4'd3
`define WORD_310 4'd4
`define PC_70 4'd5
`define PC_158 4'd6
`define PC_2316 4'd7
`define PC_3124 4'd8
`define PC_310 4'd9
`define WORD_311 4'd10
`define IA_310 4'd11
`define IA_70 4'd12
`define IA_158 4'd13
`define BYTE_71 4'd14
 
module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
input wclk;
input wr;
381,7 → 400,7
input [31:0] dat;
input rclk;
input [31:0] pc;
output reg [55:0] insn;
output reg [63:0] insn;
 
wire [63:0] insn0;
wire [63:0] insn1;
462,14 → 481,14
 
always @(rpc or insn0 or insn1)
case(rpc[2:0])
3'd0: insn <= insn0[55:0];
3'd1: insn <= insn0[63:8];
3'd2: insn <= {insn1[7:0],insn0[63:16]};
3'd3: insn <= {insn1[15:0],insn0[63:24]};
3'd4: insn <= {insn1[23:0],insn0[63:32]};
3'd5: insn <= {insn1[31:0],insn0[63:40]};
3'd6: insn <= {insn1[39:0],insn0[63:48]};
3'd7: insn <= {insn1[47:0],insn0[63:56]};
3'd0: insn <= insn0[63:0];
3'd1: insn <= {insn1[7:0],insn0[63:8]};
3'd2: insn <= {insn1[15:0],insn0[63:16]};
3'd3: insn <= {insn1[23:0],insn0[63:24]};
3'd4: insn <= {insn1[31:0],insn0[63:32]};
3'd5: insn <= {insn1[39:0],insn0[63:40]};
3'd6: insn <= {insn1[47:0],insn0[63:48]};
3'd7: insn <= {insn1[55:0],insn0[63:56]};
endcase
endmodule
 
613,7 → 632,7
endmodule
 
 
module rtf65002d(rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o);
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
parameter IDLE = 3'd0;
parameter LOAD_DCACHE = 3'd1;
parameter LOAD_ICACHE = 3'd2;
723,7 → 742,12
parameter MULDIV2 = 7'd102;
parameter BYTE_DECODE = 7'd103;
parameter BYTE_CALC = 7'd104;
parameter BUS_ERROR = 7'd105;
parameter INSN_BUS_ERROR = 7'd106;
parameter LOAD_MAC1 = 7'd107;
parameter LOAD_MAC2 = 7'd108;
 
input rst_md; // reset mode, 1=emulation mode, 0=native mode
input rst_i;
input clk_i;
input nmi_i;
736,6 → 760,7
output reg cyc_o;
output reg stb_o;
input ack_i;
input err_i;
output reg we_o;
output reg [3:0] sel_o;
output reg [33:0] adr_o;
745,8 → 770,8
reg [6:0] state;
reg [6:0] retstate;
reg [2:0] cstate;
wire [55:0] insn;
reg [55:0] ibuf;
wire [63:0] insn;
reg [63:0] ibuf;
reg [31:0] bufadr;
 
reg cf,nf,zf,vf,bf,im,df,em;
785,7 → 810,7
reg [31:0] vbr; // vector table base register
wire bhit=pc==bufadr;
reg [31:0] regfile [15:0];
reg [55:0] ir;
reg [63:0] ir;
wire [3:0] Ra = ir[11:8];
wire [3:0] Rb = ir[15:12];
reg [31:0] rfoa;
849,6 → 874,8
reg [1:0] wadr2LSB;
reg [31:0] wdat;
wire [31:0] rdat;
reg [3:0] load_what;
reg [3:0] store_what;
reg imiss;
reg dmiss;
reg icacheOn,dcacheOn;
877,10 → 904,13
wire isRMW = em ? isRMW8 : isRMW32;
wire isOrb = ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
wire isStb = ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
 
wire isRTI = ir[7:0]==`RTI;
wire isRTL = ir[7:0]==`RTL;
wire isRTS = ir[7:0]==`RTS;
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
wire md_done;
wire clk;
reg isIY;
 
mult_div umd1
(
1049,7 → 1079,6
wai <= 1'b0;
first_ifetch <= `TRUE;
wr <= 1'b0;
em <= 1'b0;
cf <= 1'b0;
ir <= 56'hEAEAEAEAEAEAEA;
imiss <= `FALSE;
1060,8 → 1089,16
nmoi <= 1'b1;
state <= RESET1;
cstate <= IDLE;
vect <= `RST_VECT;
pc <= 32'hFFFFFFF0;
if (rst_md) begin
pc <= 32'h0000FFF0; // set high-order pc to zero
vect <= `BYTE_RST_VECT;
em <= 1'b1;
end
else begin
vect <= `RST_VECT;
em <= 1'b0;
pc <= 32'hFFFFFFF0;
end
spage <= 32'h00000100;
bufadr <= 32'd0;
dp <= 32'd0;
1071,6 → 1108,7
isCacheReset <= `TRUE;
gie <= 1'b0;
tick <= 32'd0;
isIY <= 1'b0;
end
else begin
tick <= tick + 32'd1;
1090,9 → 1128,10
end
RESET2:
begin
vect <= `RST_VECT;
radr <= vect[31:2];
state <= JMP_IND1;
radr2LSB <= vect[1:0];
load_what <= em ? `PC_70 : `PC_310;
state <= LOAD_MAC1;
end
 
`include "ifetch.v"
1099,7 → 1138,7
`include "decode.v"
`include "byte_decode.v"
 
`include "load.v"
`include "load_mac.v"
`include "store.v"
 
WAIT_DHIT:
1106,80 → 1145,6
if (dhit)
state <= retstate;
 
`include "byte_ix.v"
`include "byte_iy.v"
 
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
IX1:
if (unCachedData) begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hf;
adr_o <= {radr,2'b00};
state <= IX2;
end
else if (dhit) begin
radr <= rdat;
wadr <= rdat;
wdat <= a;
if (ir[7:0]==`ST_IX)
state <= STORE1;
else
state <= LOAD1;
end
else
dmiss <= `TRUE;
IX2:
if (ack_i) begin
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
radr <= dat_i;
wadr <= dat_i; // for stores
wdat <= a;
if (ir[7:0]==`ST_IX)
state <= STORE1;
else
state <= LOAD1;
end
 
 
// Indirect Y addressing mode eg. LDA ($12),y
IY1:
if (unCachedData) begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hf;
adr_o <= {radr,2'b00};
state <= IY2;
end
else if (dhit) begin
radr <= rdat;
state <= IY3;
end
else
dmiss <= `TRUE;
IY2:
if (ack_i) begin
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
radr <= dat_i;
state <= IY3;
end
IY3:
begin
radr <= radr + y;
wadr <= radr + y;
wdat <= a;
if (ir[7:0]==`ST_IY)
state <= STORE1;
else
state <= LOAD1;
end
 
`include "byte_calc.v"
`include "calc.v"
`include "byte_jsr.v"
1209,8 → 1174,9
 
JSR_INDX1:
if (ack_i) begin
state <= JMP_IND1;
retstate <= JMP_IND1;
load_what <= `PC_310;
state <= LOAD_MAC1;
retstate <= LOAD_MAC1;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
1249,21 → 1215,12
end
end
 
`include "byte_plp.v"
`include "byte_rts.v"
`include "byte_rti.v"
`include "rti.v"
`include "rts.v"
 
`include "php.v"
`include "plp.v"
`include "pla.v"
 
`include "byte_irq.v"
`include "byte_jmp_ind.v"
 
IRQ1:
if (ack_i) begin
ir <= 64'd0; // Force instruction decoder to BRK
state <= IRQ2;
retstate <= IRQ2;
cyc_o <= 1'b0;
1295,8 → 1252,9
end
IRQ3:
if (ack_i) begin
state <= JMP_IND1;
retstate <= JMP_IND1;
load_what <= `PC_310;
state <= LOAD_MAC1;
retstate <= LOAD_MAC1;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
1315,29 → 1273,7
im <= 1'b1;
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
end
JMP_IND1:
if (unCachedData) begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {radr,2'b00};
state <= JMP_IND2;
end
else if (dhit) begin
pc <= rdat;
state <= IFETCH;
end
else
dmiss <= `TRUE;
JMP_IND2:
if (ack_i) begin
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'd0;
pc <= dat_i;
state <= IFETCH;
end
 
MULDIV1:
state <= MULDIV2;
MULDIV2:
1353,6 → 1289,35
endcase
end
 
BUS_ERROR:
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc;
vect <= {vbr[31:9],9'd508,2'b00};
state <= IRQ1;
end
INSN_BUS_ERROR:
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc;
vect <= {vbr[31:9],9'd509,2'b00};
state <= IRQ1;
end
 
endcase
 
`include "cache_controller.v"
/store.v
66,4 → 66,15
retstate <= IFETCH;
end
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
 
/rti.v
60,6 → 60,16
radr <= isp_inc;
state <= RTI3;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
RTI3:
if (unCachedData) begin
cyc_o <= 1'b1;
87,3 → 97,13
pc <= dat_i;
state <= IFETCH;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/load_mac.v
0,0 → 1,380
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
LOAD_MAC1:
if (unCachedData) begin
if (isRMW)
lock_o <= 1'b1;
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {radr,2'b00};
state <= LOAD_MAC2;
end
else if (dhit) begin
case(load_what)
`WORD_310:
begin
b <= rdat;
b8 <= rdat8; // for the orb instruction
state <= CALC;
end
`WORD_311: // For pla/plx/ply/pop
begin
res <= rdat;
state <= IFETCH;
end
`BYTE_70:
begin
b8 <= rdat8;
state <= BYTE_CALC;
end
`BYTE_71:
begin
res8 <= rdat8;
state <= IFETCH;
end
`SR_310:
begin
cf <= rdat[0];
zf <= rdat[1];
im <= rdat[2];
df <= rdat[3];
bf <= rdat[4];
em <= rdat[29];
vf <= rdat[30];
nf <= rdat[31];
isp <= isp_inc;
radr <= isp_inc;
if (isRTI)
load_what <= `PC_310;
else // PLP
state <= IFETCH;
end
`SR_70:
begin
cf <= rdat8[0];
zf <= rdat8[1];
im <= rdat8[2];
df <= rdat8[3];
bf <= rdat8[4];
vf <= rdat8[6];
nf <= rdat8[7];
if (isRTI) begin
load_what <= `PC_70;
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
end
else // PLP
state <= IFETCH;
end
`PC_70:
begin
pc[7:0] <= rdat8;
if (isRTI | isRTS | isRTL) begin
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
end
else begin // JMP (abs)
radr <= radr34p1[33:2];
radr2LSB <= radr34p1[1:0];
end
load_what <= `PC_158;
end
`PC_158:
begin
pc[15:8] <= rdat8;
if (isRTI|isRTL) begin
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
load_what <= `PC_2316;
end
else if (isRTS) // rts instruction
state <= RTS1;
else // jmp (abs)
state <= IFETCH;
end
`PC_2316:
begin
pc[23:16] <= rdat8;
if (isRTI|isRTL) begin
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
end
load_what <= `PC_3124;
end
`PC_3124:
begin
pc[31:24] <= rdat8;
load_what <= `NOTHING;
if (isRTL)
state <= RTS1;
else
state <= IFETCH;
end
`PC_310:
begin
pc <= rdat;
if (isRTI|isRTS|isRTL)
isp <= isp_inc;
load_what <= `NOTHING;
state <= IFETCH;
end
`IA_310:
begin
radr <= rdat;
wadr <= rdat;
wdat <= a;
if (isIY)
state <= IY3;
else if (ir[7:0]==`ST_IX)
state <= STORE1;
else begin
load_what <= `WORD_310;
end
end
`IA_70:
begin
radr <= radr34p1[33:2];
radr2LSB <= radr34p1[1:0];
ia[7:0] <= rdat8;
load_what <= `IA_158;
end
`IA_158:
begin
ia[15:8] <= rdat8;
ia[31:16] <= 16'h0000;
state <= isIY ? BYTE_IY5 : BYTE_IX5;
end
endcase
end
else
dmiss <= `TRUE;
LOAD_MAC2:
if (ack_i) begin
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
case(load_what)
`WORD_310:
begin
b <= dat_i;
b8 <= dati; // for the orb instruction
state <= CALC;
end
`WORD_311: // For pla/plx/ply/pop/ldx/ldy
begin
res <= dat_i;
state <= IFETCH;
end
`BYTE_70:
begin
b8 <= dati;
state <= BYTE_CALC;
end
`BYTE_71:
begin
res8 <= dati;
state <= IFETCH;
end
`SR_310: begin
cf <= dat_i[0];
zf <= dat_i[1];
im <= dat_i[2];
df <= dat_i[3];
bf <= dat_i[4];
em <= dat_i[29];
vf <= dat_i[30];
nf <= dat_i[31];
isp <= isp_inc;
radr <= isp_inc;
if (isRTI) begin
load_what <= `PC_310;
state <= LOAD_MAC1;
end
else // PLP
state <= IFETCH;
end
`SR_70: begin
cf <= dati[0];
zf <= dati[1];
im <= dati[2];
df <= dati[3];
bf <= dati[4];
vf <= dati[6];
nf <= dati[7];
if (isRTI) begin
load_what <= `PC_70;
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
state <= LOAD_MAC1;
end
else // PLP
state <= IFETCH;
end
`PC_70: begin
pc[7:0] <= dati;
load_what <= `PC_158;
if (isRTI|isRTS|isRTL) begin
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
end
else begin // JMP (abs)
radr <= radr34p1[33:2];
radr2LSB <= radr34p1[1:0];
end
state <= LOAD_MAC1;
end
`PC_158: begin
pc[15:8] <= dati;
if (isRTI|isRTL) begin
load_what <= `PC_2316;
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
state <= LOAD_MAC1;
end
else if (isRTS) // rts instruction
state <= RTS1;
else // jmp (abs)
state <= IFETCH;
end
`PC_2316: begin
pc[23:16] <= dati;
load_what <= `PC_3124;
if (isRTI|isRTL) begin
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
end
state <= LOAD_MAC1;
end
`PC_3124: begin
pc[31:24] <= dati;
load_what <= `NOTHING;
if (isRTL)
state <= RTS1;
else
state <= IFETCH;
end
`PC_310: begin
pc <= dat_i;
load_what <= `NOTHING;
if (isRTI | isRTL | isRTS)
isp <= isp_inc;
state <= IFETCH;
end
`IA_310:
begin
radr <= dat_i;
wadr <= dat_i;
wdat <= a;
if (isIY)
state <= IY3;
else if (ir[7:0]==`ST_IX)
state <= STORE1;
else begin
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
end
`IA_70:
begin
radr <= radr34p1[33:2];
radr2LSB <= radr34p1[1:0];
ia[7:0] <= rdat8;
load_what <= `IA_158;
state <= LOAD_MAC1;
end
`IA_158:
begin
ia[15:8] <= rdat8;
ia[31:16] <= 16'h0000;
state <= isIY ? BYTE_IY5 : BYTE_IX5;
end
endcase
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
RTS1:
begin
pc <= pc + 32'd1;
state <= IFETCH;
end
IY3:
begin
radr <= radr + y;
wadr <= radr + y;
wdat <= a;
if (ir[7:0]==`ST_IY)
state <= STORE1;
else begin
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
isIY <= 1'b0;
end
BYTE_IX5:
begin
radr <= ia[31:2];
radr2LSB <= ia[1:0];
load_what <= `BYTE_70;
state <= LOAD_MAC1;
if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
wadr <= ia[31:2];
wadr2LSB <= ia[1:0];
wdat <= {4{acc8}};
state <= STORE1;
end
end
BYTE_IY5:
begin
isIY <= `FALSE;
radr <= iapy8[31:2];
radr2LSB <= iapy8[1:0];
$display("IY addr: %h", iapy8);
if (ir[7:0]==`STA_IY) begin
wadr <= iapy8[31:2];
wadr2LSB <= iapy8[1:0];
wdat <= {4{acc8}};
state <= STORE1;
end
else begin
load_what <= `BYTE_70;
state <= LOAD_MAC1;
end
end
/calc.v
37,8 → 37,8
`ASL_RRR: res <= shlo;
`LSR_RRR: res <= shro;
endcase
`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: begin res <= a + b; end
`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: begin res <= a - b; end // Also CMP
`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: begin res <= a + b + {31'b0,df&cf}; end
`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: begin res <= a - b - {31'b0,df&~cf&|Rt}; end // Also CMP
`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: begin res <= a & b; end // Also BIT
`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: begin res <= a | b; end // Also LD
`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: begin res <= a ^ b; end
/byte_jmp_ind.v
47,6 → 47,16
pc[7:0] <= dati;
state <= BYTE_JMP_IND3;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_JMP_IND3:
if (unCachedData) begin
cyc_o <= 1'b1;
70,3 → 80,13
pc[15:8] <= dati;
state <= IFETCH;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/byte_ix.v
48,6 → 48,16
radr2LSB <= radr34p1[1:0];
state <= BYTE_IX3;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_IX3:
if (unCachedData) begin
cyc_o <= 1'b1;
73,6 → 83,16
ia[31:16] <= 16'h0000;
state <= BYTE_IX5;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_IX5:
begin
radr <= ia[31:2];
/byte_iy.v
48,6 → 48,16
radr2LSB <= radr34p1[1:0];
state <= BYTE_IY3;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_IY3:
if (unCachedData) begin
cyc_o <= 1'b1;
77,6 → 87,16
radr2LSB <= radr34p1[1:0];
state <= BYTE_IY5;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
BYTE_IY5:
begin
radr <= iapy8[31:2];
/cache_controller.v
89,6 → 89,24
end
adr_o <= adr_o + 34'd4;
end
// What to do here
else if (err_i) begin
if (adr_o[3:2]==2'b11) begin
dmiss <= `FALSE;
isDataCacheLoad <= `FALSE;
cti_o <= 3'b000;
bl_o <= 6'd0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
cstate <= IDLE;
// The state machine will be waiting for a dhit.
// Override the next state and send the processor to the bus error state.
state <= BUS_ERROR;
end
adr_o <= adr_o + 34'd4;
end
LOAD_ICACHE:
if (ack_i) begin
if (adr_o[3:2]==2'b11) begin
104,8 → 122,23
end
adr_o <= adr_o + 34'd4;
end
else if (err_i) begin
if (adr_o[3:2]==2'b11) begin
imiss <= `FALSE;
isInsnCacheLoad <= `FALSE;
cti_o <= 3'b000;
bl_o <= 6'd0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'd0;
state <= INSN_BUS_ERROR;
cstate <= IDLE;
end
adr_o <= adr_o + 34'd4;
end
LOAD_IBUF1:
if (ack_i) begin
if (ack_i|err_i) begin
case(pc[1:0])
2'd0: ibuf <= dat_i;
2'd1: ibuf <= dat_i[31:8];
116,7 → 149,7
adr_o <= adr_o + 34'd4;
end
LOAD_IBUF2:
if (ack_i) begin
if (ack_i|err_i) begin
case(pc[1:0])
2'd0: ibuf[55:32] <= dat_i[23:0];
2'd1: ibuf[55:24] <= dat_i;
144,4 → 177,23
imiss <= `FALSE;
bufadr <= pc; // clears the miss
end
else if (err_i) begin
case(pc[1:0])
2'd0: ;
2'd1: ;
2'd2: ibuf[55:48] <= dat_i[7:0];
2'd3: ibuf[55:40] <= dat_i[15:0];
endcase
cti_o <= 3'd0;
bl_o <= 6'd0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'd0;
cstate <= IDLE;
state <= INSN_BUS_ERROR;
imiss <= `FALSE;
bufadr <= pc; // clears the miss
end
 
endcase
/byte_decode.v
103,14 → 103,23
res8 <= y8 - ir[15:8];
end
// Handle zp mode
`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,`LDA_ZP,
`LDX_ZP,`LDY_ZP,`BIT_ZP,`CPX_ZP,`CPY_ZP,
`LDX_ZP,`LDY_ZP,`LDA_ZP:
begin
pc <= pc + 32'd2;
radr <= zp_address[31:2];
radr2LSB <= zp_address[1:0];
load_what <= `BYTE_71;
state <= LOAD_MAC1;
end
`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
`BIT_ZP,`CPX_ZP,`CPY_ZP,
`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
begin
pc <= pc + 32'd2;
radr <= zp_address[31:2];
radr2LSB <= zp_address[1:0];
state <= LOAD1;
load_what <= `BYTE_70;
state <= LOAD_MAC1;
end
`STA_ZP:
begin
145,14 → 154,23
state <= STORE1;
end
// Handle zp,x mode
`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,`LDA_ZPX,
`LDY_ZPX,`BIT_ZPX,
`LDY_ZPX,`LDA_ZPX:
begin
pc <= pc + 32'd2;
radr <= zpx_address[31:2];
radr2LSB <= zpx_address[1:0];
load_what <= `BYTE_71;
state <= LOAD_MAC1;
end
`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
`BIT_ZPX,
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
begin
pc <= pc + 32'd2;
radr <= zpx_address[31:2];
radr2LSB <= zpx_address[1:0];
state <= LOAD1;
load_what <= `BYTE_70;
state <= LOAD_MAC1;
end
`STA_ZPX:
begin
184,7 → 202,8
pc <= pc + 32'd2;
radr <= zpy_address[31:2];
radr2LSB <= zpy_address[1:0];
state <= LOAD1;
load_what <= `BYTE_71;
state <= LOAD_MAC1;
end
`STX_ZPY:
begin
200,7 → 219,8
pc <= pc + 32'd2;
radr <= zpx_address[31:2];
radr2LSB <= zpx_address[1:0];
state <= BYTE_IX1;
load_what <= `IA_70;
state <= LOAD_MAC1;
end
// Handle (zp),y
`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
208,12 → 228,21
pc <= pc + 32'd2;
radr <= zp_address[31:2];
radr2LSB <= zp_address[1:0];
state <= BYTE_IY1;
isIY <= `TRUE;
load_what <= `IA_70;
state <= LOAD_MAC1;
end
// Handle abs
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,`LDA_ABS,
`LDA_ABS,`LDX_ABS,`LDY_ABS:
begin
pc <= pc + 32'd3;
radr <= abs_address[31:2];
radr2LSB <= abs_address[1:0];
load_what <= `BYTE_71;
state <= LOAD_MAC1;
end
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
`LDX_ABS,`LDY_ABS,
`CPX_ABS,`CPY_ABS,
`BIT_ABS:
begin
220,7 → 249,8
pc <= pc + 32'd3;
radr <= abs_address[31:2];
radr2LSB <= abs_address[1:0];
state <= LOAD1;
load_what <= `BYTE_70;
state <= LOAD_MAC1;
end
`STA_ABS:
begin
262,7 → 292,8
pc <= pc + 32'd3;
radr <= absx_address[31:2];
radr2LSB <= absx_address[1:0];
state <= LOAD1;
load_what <= `BYTE_70;
state <= LOAD_MAC1;
end
`STA_ABSX:
begin
287,7 → 318,8
pc <= pc + 32'd3;
radr <= absy_address[31:2];
radr2LSB <= absy_address[1:0];
state <= LOAD1;
load_what <= `BYTE_70;
state <= LOAD_MAC1;
end
`STA_ABSY:
begin
303,7 → 335,8
pc <= pc + 32'd2;
radr <= zp_address[31:2];
radr2LSB <= zp_address[1:0];
state <= BYTE_IX1;
load_what <= `IA_70;
state <= LOAD_MAC1;
end
`BRK:
begin
340,13 → 373,15
begin
radr <= abs_address[31:2];
radr2LSB <= abs_address[1:0];
state <= BYTE_JMP_IND1;
load_what <= `PC_70;
state <= LOAD_MAC1;
end
`JMP_INDX:
begin
radr <= absx_address[31:2];
radr2LSB <= absx_address[1:0];
state <= BYTE_JMP_IND1;
load_what <= `PC_70;
state <= LOAD_MAC1;
end
`JSR:
begin
416,13 → 451,15
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
state <= BYTE_RTS1;
load_what <= `PC_70;
state <= LOAD_MAC1;
end
`RTI: begin
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
state <= BYTE_RTI9;
load_what <= `SR_70;
state <= LOAD_MAC1;
end
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
begin
549,7 → 586,8
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
state <= BYTE_PLP1;
load_what <= `SR_70;
state <= LOAD_MAC1;
pc <= pc + 32'd1;
end
`PLA,`PLX,`PLY:
557,7 → 595,8
radr <= {spage[31:8],sp_inc[7:2]};
radr2LSB <= sp_inc[1:0];
sp <= sp_inc;
state <= PLA1;
load_what <= `BYTE_71;
state <= LOAD_MAC1;
pc <= pc + 32'd1;
end
default: // unimplemented opcode
/rts.v
45,3 → 45,13
pc <= dat_i;
state <= IFETCH;
end
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end

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