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URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

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    /rtf65002/trunk
    from Rev 35 to Rev 36
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Rev 35 → Rev 36

/rtl/verilog/rtf65002_defines.v
448,6 → 448,15
`define HOFF 9'h158
`define CMPS 9'h144
 
`define LEA_ZPX 9'h1D5
`define LEA_IX 9'h1C1
`define LEA_IY 9'h1D1
`define LEA_ABS 9'h1CD
`define LEA_ABSX 9'h1DD
`define LEA_RIND 9'h1D2
`define LEA_I 9'h1D2
`define LEA_DSP 9'h1C3
 
`define NOTHING 5'd0
`define SR_70 5'd1
`define SR_310 5'd2
/rtl/verilog/rtf65002_alu.v
211,6 → 211,8
`BMC_ZPX,`BMC_ABS,`BMC_ABSX: res <= b & (~(32'b1 << acc[4:0]));
`BMF_ZPX,`BMF_ABS,`BMF_ABSX: res <= b ^ (32'b1 << acc[4:0]);
`BMT_ZPX,`BMT_ABS,`BMT_ABSX: res <= b & (32'b1 << acc[4:0]);
`TRB_ZPX,`TRB_ABS: res <= ~a & b;
`TSB_ZPX,`TSB_ABS: res <= a | b;
default: res <= 33'd0;
endcase
endmodule
/rtl/verilog/rtf65002d.v
105,6 → 105,7
wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
reg nmi1,nmi_edge;
reg wai;
reg wrrf; // write register file
reg [31:0] acc;
reg [31:0] x;
reg [31:0] y;
655,8 → 656,10
pg2 <= `FALSE;
tf <= `FALSE;
km <= `TRUE;
wrrf <= 1'b0;
end
else begin
wrrf <= 1'b0;
tick <= tick + 32'd1;
ilfsr <= {ilfsr,ilfsr_fb};
if (nmi_i & !nmi1)
749,7 → 752,20
`include "cache_controller.v"
 
endcase
 
if (wrrf || state==IFETCH || state==LOAD_MAC3) begin
regfile[Rt] <= res[31:0];
case(Rt)
4'h1: acc <= res[31:0];
4'h2: x <= res[31:0];
4'h3: y <= res[31:0];
default: ;
endcase
end
 
end
 
 
`include "decode.v"
`include "calc.v"
`include "load_tsk.v"
762,4 → 778,44
end
endtask
 
function [127:0] fnStateName;
input [5:0] state;
case(state)
RESET1: fnStateName = "RESET1 ";
RESET2: fnStateName = "RESET2 ";
IFETCH: fnStateName = "IFETCH ";
DECODE: fnStateName = "DECODE ";
STORE1: fnStateName = "STORE1 ";
STORE2: fnStateName = "STORE2 ";
CALC: fnStateName = "CALC ";
RTS1: fnStateName = "RTS1 ";
IY3: fnStateName = "IY3 ";
BYTE_IX5: fnStateName = "BYTE_IX5 ";
BYTE_IY5: fnStateName = "BYTE_IY5 ";
WAIT_DHIT: fnStateName = "WAIT_DHIT ";
MULDIV1: fnStateName = "MULDIV1 ";
MULDIV2: fnStateName = "MULDIV2 ";
BYTE_DECODE: fnStateName = "BYTE_DECODE";
BYTE_CALC: fnStateName = "BYTE_CALC ";
BUS_ERROR: fnStateName = "BUS_ERROR ";
LOAD_MAC1: fnStateName = "LOAD_MAC1 ";
LOAD_MAC2: fnStateName = "LOAD_MAC2 ";
LOAD_MAC3: fnStateName = "LOAD_MAC3 ";
MVN3: fnStateName = "MVN3 ";
PUSHA1: fnStateName = "PUSHA1 ";
POPA1: fnStateName = "POPA1 ";
BYTE_IFETCH: fnStateName = "BYTE_IFETCH";
LOAD_DCACHE: fnStateName = "LOAD_DCACHE";
LOAD_ICACHE: fnStateName = "LOAD_ICACHE";
LOAD_IBUF1: fnStateName = "LOAD_IBUF1 ";
LOAD_IBUF2: fnStateName = "LOAD_IBUF2 ";
LOAD_IBUF3: fnStateName = "LOAD_IBUF3 ";
ICACHE1: fnStateName = "ICACHE1 ";
IBUF1: fnStateName = "IBUF1 ";
DCACHE1: fnStateName = "DCACHE1 ";
CMPS1: fnStateName = "CMPS1 ";
default: fnStateName = "UNKNOWN ";
endcase
endfunction
 
endmodule
/rtl/verilog/store.v
57,6 → 57,8
`ifdef SUPPORT_DCACHE
radr <= wadr; // Do a cache read to test the hit
`endif
if (ir9==`PUSH)
Rt <= 4'h0;
state <= STORE2;
end
/rtl/verilog/load_tsk.v
33,6 → 33,8
end
`WORD_311: // For pla/plx/ply/pop/ldx/ldy
begin
if (ir9==`POP)
Rt <= ir[15:12];
res <= dat;
state <= isPopa ? LOAD_MAC3 : IFETCH;
end
177,6 → 179,10
state <= IY3;
else if (ir9==`ST_IX)
state <= STORE1;
else if (ir9==`LEA_IX) begin
res <= dat;
next_state(IFETCH);
end
else begin
load_what <= `WORD_310;
state <= LOAD_MAC1;
/rtl/verilog/calc.v
37,7 → 37,7
`ROR_ZPX,`ROR_ABS,`ROR_ABSX,
`INC_ZPX,`INC_ABS,`INC_ABSX,
`DEC_ZPX,`DEC_ABS,`DEC_ABSX:
state <= STORE1;
state <= STORE1;
endcase
end
endtask
/rtl/verilog/rtf65002_tb.v
18,6 → 18,14
wire [7:0] udo;
wire btrm_ack;
wire [31:0] btrm_dato;
wire bas_ack;
wire [31:0] bas_dato;
wire tc_ack;
wire [31:0] tc_dato;
wire sema_ack;
wire [31:0] sema_dat;
wire ga_ack;
wire [31:0] ga_dat;
 
initial begin
clk = 1;
25,7 → 33,7
nmi = 0;
#100 rst = 1;
#100 rst = 0;
#500 nmi = 1;
#500 nmi = 0;
#10 nmi = 0;
end
 
50,10 → 58,14
.dat_o(dato)
);
 
wire uartcs = cyc && stb && a[33:8]==26'h00000CF;
wire romcs = ~(cyc && stb && a[33:28]==6'h0F);
wire ramcs = ~(cyc && stb && (a[33:15]==19'h00 || (a[33:28]!=6'hF && a[33:28]!=6'h0)));
wire romcs1 = ~(cyc && stb && a[33:13]==21'h07); // E000
wire uartcs = cyc && stb && a[33:8]==26'h00000BF;
wire romcs = ~(cyc && stb && a[33:20]==14'h0FFF);
wire ramcs = ~(cyc && stb && (a[33:14]==20'h00 || (a[33:28]!=6'h3F && a[33:28]!=6'h0 && a[33:28]!=6'h0F)));
wire romcs1 = 1'b1;//~(cyc && stb && a[33:13]==21'h07); // E000
wire bas_cs = (cyc && stb && a[33:14]==20'h03);
wire tc_cs = (cyc && stb && (a[33:18]==16'hFFD0 || a[33:18]==16'hFFDA ||a[33:18]==16'hFFD1 || a[33:18]==16'hFFD2));
wire leds_cs = (cyc && stb && a[33:2]==32'hFFDC0600);
wire configrec_cs = (cyc && stb && a[33:6]==28'hFFDCFFF);
 
assign d = wr ? dato : 32'bz;
assign dati = ~romcs ? btrm_dato : 32'bz;
60,8 → 72,19
assign dati = ~ramcs ? d : 32'bz;
assign dati = uartcs ? {4{udo}} : 32'bz;
assign dati = ~romcs1 ? d : 32'bz;
assign dati = bas_cs ? bas_dato : 32'bz;
assign dati = tc_cs ? tc_dato : 32'bz;
assign dati = configrec_cs ? 32'h00000FDF : 32'bz;
assign dati = sema_ack ? sema_dat : 32'bz;
assign dati = ga_ack ? ga_dat : 32'bz;
 
assign ack =
configrec_cs |
leds_cs |
tc_ack |
sema_ack |
ga_ack |
bas_ack |
btrm_ack |
~ramcs |
~romcs1 |
73,7 → 96,64
ram8Kx32 ram0 (.clk(clk), .ce(ramcs), .oe(wr), .we(~wr), .sel(sel), .addr(a[14:2]), .d(d));
uart uart0(.clk(clk), .cs(uartcs), .wr(wr), .a(a[2:0]), .di(dato[7:0]), .do(udo));
bootrom ubr1 (.rst_i(rst), .clk_i(clk), .cti_i(cti), .cyc_i(cyc), .stb_i(stb), .ack_o(btrm_ack), .adr_i(a), .dat_o(btrm_dato), .perr());
basic_rom ubas1(.rst_i(rst), .clk_i(clk), .cti_i(cti), .cyc_i(cyc), .stb_i(stb), .ack_o(bas_ack), .adr_i(a), .dat_o(bas_dato), .perr());
rtfTextController tc1 (
.rst_i(rst),
.clk_i(clk),
.cyc_i(cyc),
.stb_i(stb),
.ack_o(tc_ack),
.we_i(wr),
.adr_i(a),
.dat_i(dato),
.dat_o(tc_dato),
.lp(),
.curpos(),
.vclk(1'b0),
.hsync(1'b0),
.vsync(1'b0),
.blank(1'b0),
.border(1'b0),
.rgbIn(),
.rgbOut()
);
 
sema_mem usm1
(
.rst_i(rst),
.clk_i(clk),
.cyc_i(cyc),
.stb_i(stb),
.ack_o(sema_ack),
.we_i(wr),
.adr_i(a),
.dat_i(dato),
.dat_o(sema_dat)
);
 
rtfGraphicsAccelerator uga1 (
.rst_i(rst),
.clk_i(clk),
 
.s_cyc_i(cyc),
.s_stb_i(stb),
.s_we_i(wr),
.s_ack_o(ga_ack),
.s_sel_i(sel),
.s_adr_i(a),
.s_dat_i(dato),
.s_dat_o(ga_dat),
 
.m_cyc_o(),
.m_stb_o(),
.m_we_o(),
.m_ack_i(1'b1),
.m_sel_o(),
.m_adr_o(),
.m_dat_i(),
.m_dat_o()
);
 
always @(posedge clk) begin
if (rst)
n = 0;
81,10 → 161,10
n = n + 1;
if ((n & 7)==0)
$display("t n cti cyc we addr din adnx do re vma wr ird sync vma nmi irq PC IR A X Y SP nvmdizcb\n");
$display("%d %d %b %b %b %h %h %h %h %h %h %h %h %h %h %h %h %b%b%b%b%b%b%b%b %d %b %b %b %b %b %b",
$time, n, cpu0.cti_o, cpu0.cyc_o, cpu0.we_o, cpu0.adr_o, cpu0.dat_i, cpu0.dat_o, cpu0.res, cpu0.res8, cpu0.pc, cpu0.ir,
$display("%d %d %b %b%b %c %h %h %h %h %h pc=%h ir=%h acc=%h x=%h y=%h sp=%h sp8=%h %b%b%b%b%b%b%b%b %s %b %b %b %b %b %b",
$time, n, cpu0.cti_o, cpu0.cyc_o, cpu0.ack_i, cpu0.we_o?"W":" ", cpu0.adr_o, cpu0.dat_i, cpu0.dat_o, cpu0.res, cpu0.res8, cpu0.pc, cpu0.ir,
cpu0.acc, cpu0.x, cpu0.y, cpu0.isp, cpu0.sp,
cpu0.nf, cpu0.vf, cpu0.df, cpu0.im, cpu0.zf, cpu0.cf, cpu0.bf, cpu0.em, cpu0.state, cpu0.imiss, cpu0.ihit,cpu0.hit0,cpu0.hit1,cpu0.imiss,ubr1.cs);
cpu0.nf, cpu0.vf, cpu0.df, cpu0.im, cpu0.zf, cpu0.cf, cpu0.bf, cpu0.em, cpu0.fnStateName(cpu0.state), cpu0.imiss, cpu0.ihit,cpu0.hit0,cpu0.hit1,cpu0.imiss,ubr1.cs);
end
endmodule
143,7 → 223,7
output [31:0] d; // tri-state data I/O
tri [31:0] d;
 
reg [31:0] mem [0:8191];
reg [31:0] mem [0:65535];
integer nn;
 
initial begin
/rtl/verilog/decode.v
346,7 → 346,7
store_what <= `STW_Y;
state <= STORE1;
end
`ADD_ZPX,`SUB_ZPX,`AND_ZPX:
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`TRB_ZPX:
begin
Rt <= ir[19:16];
radr <= zpx32_address;
353,8 → 353,14
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`LEA_ZPX:
begin
Rt <= ir[19:16];
res <= zpx32_address;
state <= IFETCH;
end
// Trim a clock cycle off of loads by testing for Ra = 0.
`OR_ZPX,`EOR_ZPX:
`OR_ZPX,`EOR_ZPX,`TSB_ZPX:
begin
Rt <= ir[19:16];
radr <= zpx32_address;
373,6 → 379,12
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`LEA_DSP:
begin
Rt <= ir[15:12];
res <= {{24{ir[23]}},ir[23:16]} + isp;
state <= IFETCH;
end
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
begin
Rt <= ir[15:12];
380,7 → 392,7
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
begin
if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0
Rt <= ir[19:16];
389,6 → 401,12
store_what <= `STW_A;
state <= LOAD_MAC1;
end
`LEA_RIND:
begin
Rt <= ir[19:16];
res <= rfob;
state <= IFETCH;
end
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
begin
radr <= rfob;
402,7 → 420,7
store_what <= `STW_RFA;
state <= STORE1;
end
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY,`LEA_IY:
begin
if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0
Rt <= ir[19:16];
412,14 → 430,20
store_what <= `STW_A;
state <= LOAD_MAC1;
end
`OR_ABS,`EOR_ABS:
`LEA_ABS:
begin
res <= ir[47:16];
Rt <= ir[15:12];
state <= IFETCH;
end
`OR_ABS,`EOR_ABS,`TSB_ABS:
begin
radr <= ir[47:16];
Rt <= ir[15:12];
load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
state <= LOAD_MAC1;
end
`ADD_ABS,`SUB_ABS,`AND_ABS:
`ADD_ABS,`SUB_ABS,`AND_ABS,`TRB_ABS:
begin
radr <= ir[47:16];
Rt <= ir[15:12];
438,6 → 462,12
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`LEA_ABSX:
begin
res <= absx32_address;
Rt <= ir[19:16];
state <= IFETCH;
end
`ADD_ABSX,`SUB_ABSX,`AND_ABSX:
begin
radr <= absx32_address;
670,11 → 700,20
end
`PUSH:
begin
radr <= isp_dec;
wadr <= isp_dec;
if (ir[15:12]==4'h0) begin
radr <= isp_dec;
wadr <= isp_dec;
isp <= isp_dec;
end
else begin
radr <= rfob-32'd1;
wadr <= rfob-32'd1;
wrrf <= 1'b1;
Rt <= ir[15:12];
res <= rfob-32'd1;
end
store_what <= `STW_A;
state <= STORE1;
isp <= isp_dec;
end
`PUSHA:
begin
718,9 → 757,16
end
`POP:
begin
Rt <= ir[15:12];
radr <= isp;
isp <= isp_inc;
if (ir[11:8]!=4'h0) begin
Rt <= ir[11:8];
res <= rfoa+32'd1;
wrrf <= 1'b1;
radr <= rfoa;
end
else begin
radr <= isp;
isp <= isp_inc;
end
load_what <= `WORD_311;
state <= LOAD_MAC1;
end
/rtl/verilog/load_mac.v
57,13 → 57,6
`endif
LOAD_MAC3:
begin
regfile[Rt] <= res[31:0];
case(Rt)
4'h1: acc <= res[31:0];
4'h2: x <= res[31:0];
4'h3: y <= res[31:0];
default: ;
endcase
// Rt will be zero by the time the IFETCH stage is entered because of
// the decrement below.
if (Rt==4'd1)
89,6 → 82,10
store_what <= `STW_A;
state <= STORE1;
end
else if (ir9==`LEA_IY) begin
res <= radr + y;
next_state(IFETCH);
end
else begin
load_what <= `WORD_310;
state <= LOAD_MAC1;
/rtl/verilog/ifetch.v
125,13 → 125,6
history_ndx <= history_ndx+7'd1;
end
`endif
regfile[Rt] <= res[31:0];
case(Rt)
4'h1: acc <= res[31:0];
4'h2: x <= res[31:0];
4'h3: y <= res[31:0];
default: ;
endcase
case(ir9)
`TAS,`TXS: begin isp <= res[31:0]; gie <= 1'b1; end
`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res[31:0];
220,5 → 213,9
`TSA,`TYA,`TXA,`INA,`DEA,
`LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA: begin nf <= resn32; zf <= resz32; end
`POP: begin nf <= resn32; zf <= resz32; end
`TRB_ZPX,`TRB_ABS,`TSB_ZPX,`TSB_ABS:
begin zf <= resz32; end
`BMT_ZPX,`BMT_ABS,`BMT_ABSX:
begin zf <= resz32; nf <= resn32; end
endcase
end
/rtl/verilog/rtf65002_pcinc.v
59,13 → 59,13
`ADD_IMM32,`SUB_IMM32,`AND_IMM32,`OR_IMM32,`EOR_IMM32: inc <= 4'd6;
`MUL_IMM32,`DIV_IMM32,`MOD_IMM32: inc <= 4'd6;
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32,`SUB_SP32,`CPX_IMM32,`CPY_IMM32: inc <= 4'd5;
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`OR_ZPX,`EOR_ZPX: inc <= 4'd4;
`ADD_IX,`SUB_IX,`AND_IX,`OR_IX,`EOR_IX: inc <= 4'd4;
`ADD_IY,`SUB_IY,`AND_IY,`OR_IY,`EOR_IY: inc <= 4'd4;
`ADD_ABS,`SUB_ABS,`AND_ABS,`OR_ABS,`EOR_ABS: inc <= 4'd6;
`ADD_ABSX,`SUB_ABSX,`AND_ABSX,`OR_ABSX,`EOR_ABSX: inc <= 4'd7;
`ADD_RIND,`SUB_RIND,`AND_RIND,`OR_RIND,`EOR_RIND: inc <= 4'd3;
`ADD_DSP,`SUB_DSP,`AND_DSP,`OR_DSP,`EOR_DSP: inc <= 4'd3;
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`OR_ZPX,`EOR_ZPX,`LEA_ZPX: inc <= 4'd4;
`ADD_IX,`SUB_IX,`AND_IX,`OR_IX,`EOR_IX,`LEA_IX: inc <= 4'd4;
`ADD_IY,`SUB_IY,`AND_IY,`OR_IY,`EOR_IY,`LEA_IY: inc <= 4'd4;
`ADD_ABS,`SUB_ABS,`AND_ABS,`OR_ABS,`EOR_ABS,`LEA_ABS: inc <= 4'd6;
`ADD_ABSX,`SUB_ABSX,`AND_ABSX,`OR_ABSX,`EOR_ABSX,`LEA_ABSX: inc <= 4'd7;
`ADD_RIND,`SUB_RIND,`AND_RIND,`OR_RIND,`EOR_RIND,`LEA_RIND: inc <= 4'd3;
`ADD_DSP,`SUB_DSP,`AND_DSP,`OR_DSP,`EOR_DSP,`LEA_DSP: inc <= 4'd3;
`ASL_ACC,`LSR_ACC,`ROR_ACC,`ROL_ACC: inc <= 4'd1;
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,`INC_RR,`DEC_RR: inc <= 4'd2;
`ST_RIND: inc <= 4'd2;

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