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URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

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    /rtf65002
    from Rev 9 to Rev 10
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Rev 9 → Rev 10

/trunk/rtl/verilog/byte_jsl.v
1,5 → 1,29
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
BYTE_JSL1:
if (ack_i) begin
state <= BYTE_JSL2;
retstate <= BYTE_JSL2;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
8,7 → 32,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_JSL2;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_JSL2:
begin
33,6 → 60,8
end
BYTE_JSL3:
if (ack_i) begin
state <= BYTE_JSL4;
retstate <= BYTE_JSL4;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
41,7 → 70,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_JSL4;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_JSL4:
begin
66,6 → 98,8
end
BYTE_JSL5:
if (ack_i) begin
state <= BYTE_JSL6;
retstate <= BYTE_JSL6;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
74,7 → 108,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_JSL6;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_JSL6:
begin
99,6 → 136,8
end
BYTE_JSL7:
if (ack_i) begin
state <= IFETCH;
retstate <= IFETCH;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
107,6 → 146,9
wrsel <= sel_o;
wr <= 1'b1;
end
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
pc <= ir[39:8];
state <= IFETCH;
end
/trunk/rtl/verilog/pla.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// Works for both eight bit and 32 bit modes
//
PLA1:
/trunk/rtl/verilog/byte_irq.v
1,8 → 1,32
// IRQ processing states
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// IRQ processing states for 65C02 emulation mode
// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.
//
BYTE_IRQ1:
if (ack_i) begin
state <= BYTE_IRQ2;
retstate <= BYTE_IRQ2;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
12,7 → 36,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_IRQ2;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_IRQ2:
begin
36,6 → 63,8
end
BYTE_IRQ3:
if (ack_i) begin
state <= BYTE_IRQ4;
retstate <= BYTE_IRQ4;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
45,7 → 74,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_IRQ4;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_IRQ4:
begin
69,6 → 101,8
end
BYTE_IRQ5:
if (ack_i) begin
state <= BYTE_IRQ6;
retstate <= BYTE_IRQ6;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
78,7 → 112,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_IRQ6;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_IRQ6:
begin
102,6 → 139,8
end
BYTE_IRQ7:
if (ack_i) begin
state <= BYTE_IRQ8;
retstate <= BYTE_IRQ8;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
111,7 → 150,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_IRQ8;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_IRQ8:
begin
135,6 → 177,8
end
BYTE_IRQ9:
if (ack_i) begin
state <= BYTE_JMP_IND1;
retstate <= BYTE_JMP_IND1;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
144,9 → 188,12
wrsel <= sel_o;
wr <= 1'b1;
end
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
pc[31:16] <= 16'h0000;
radr <= vect[31:2];
radr2LSB <= vect[1:0];
state <= BYTE_JMP_IND1;
end
/trunk/rtl/verilog/byte_plp.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
BYTE_PLP1:
if (unCachedData) begin
cyc_o <= 1'b1;
/trunk/rtl/verilog/byte_jsr.v
1,5 → 1,29
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
BYTE_JSR1:
if (ack_i) begin
state <= BYTE_JSR2;
retstate <= BYTE_JSR2;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
8,7 → 32,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_JSR2;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_JSR2:
begin
33,6 → 60,8
end
BYTE_JSR3:
if (ack_i) begin
state <= IFETCH;
retstate <= IFETCH;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
42,5 → 71,8
wrsel <= sel_o;
wr <= 1'b1;
end
state <= IFETCH;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
/trunk/rtl/verilog/byte_rti.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// RTI processing states for eight bit mode
//
BYTE_RTI9:
/trunk/rtl/verilog/RTF65002PIC.v
0,0 → 1,180
`timescale 1ns / 1ps
//=============================================================================
// (C) 2013 Robert Finch
// All rights reserved.
// robfinch@Opencores.org
//
// RTF65002PIC.v
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// Encodes discrete interrupt request signals into four
// bit code using a priority encoder.
//
// reg
// 0 - encoded request number (read only)
// This register contains the number identifying
// the current requester.
// the actual number is shifted left three times
// before being placed into this register so it may
// be used directly as an index in OS software. The
// index may be a mailbox id or index into a jump
// table as desired by the OS. If there is no
// active request, then this number will be
// zero.
// 1 - request enable (read / write)
// this register contains request enable bits
// for each request line. 1 = request
// enabled, 0 = request disabled. On reset this
// register is set to zero (disable all ints).
// bit zero is specially reserved for nmi
//
// 2 - write only
// this register disables the interrupt indicated
// by the low order four bits of the input data
//
// 3 - write only
// this register enables the interrupt indicated
// by the low order four bits of the input data
//
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |WISHBONE Datasheet
// |WISHBONE SoC Architecture Specification, Revision B.3
// |
// |Description: Specifications:
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |General Description: simple programmable interrupt controller
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Supported Cycles: SLAVE,READ/WRITE
// | SLAVE,BLOCK READ/WRITE
// | SLAVE,RMW
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Data port, size: 16 bit
// |Data port, granularity: 16 bit
// |Data port, maximum operand size: 16 bit
// |Data transfer ordering: Undefined
// |Data transfer sequencing: Undefined
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Clock frequency constraints: none
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Supported signal list and Signal Name WISHBONE equiv.
// |cross reference to equivalent ack_o ACK_O
// |WISHBONE signals adr_i(2:1) ADR_I()
// | clk_i CLK_I
// | dat_i(15:0) DAT_I()
// | dat_o(15:0) DAT_O()
// | cyc_i CYC_I
// | stb_i STB_I
// | we_i WE_I
// |
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Special requirements:
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
// Spartan3-4
// 105 LUTs / 58 slices / 163MHz
//=============================================================================
 
module RTF65002PIC
(
input rst_i, // reset
input clk_i, // system clock
input cyc_i, // cycle valid
input stb_i, // strobe
output ack_o, // transfer acknowledge
input we_i, // write
input [33:0] adr_i, // address
input [31:0] dat_i,
output reg [31:0] dat_o,
output vol_o, // volatile register selected
input i1, i2, i3, i4, i5, i6, i7,
i8, i9, i10, i11, i12, i13, i14, i15,
output irqo, // normally connected to the processor irq
input nmii, // nmi input connected to nmi requester
output nmio, // normally connected to the nmi of cpu
output [8:0] vecno
);
parameter pVECNO = 9'd448;
parameter pIOAddress = 32'hFFDC_0FF0;
 
reg [15:0] ie; // interrupt enable register
reg ack1;
reg [3:0] irqenc;
 
wire cs = cyc_i && stb_i && adr_i[33:6]==pIOAddress[31:4];
assign vol_o = cs;
 
always @(posedge clk_i)
ack1 <= cs;
assign ack_o = cs ? (we_i ? 1'b1 : ack1) : 1'b0;
 
// write registers
always @(posedge clk_i)
if (rst_i)
ie <= 16'h0;
else if (cs & we_i)
case (adr_i[3:2])
2'd0,2'd1:
begin
ie[15:0] <= dat_i[15:0];
end
2'd2,2'd3:
ie[dat_i[3:0]] <= adr_i[2];
endcase
 
// read registers
always @(posedge clk_i)
begin
if (irqenc!=4'd0)
$display("PIC: %d",irqenc);
if (cs)
case (adr_i[3:2])
2'd0: dat_o <= {28'b0,irqenc};
default: dat_o <= ie;
endcase
else
dat_o <= 32'h0000;
end
 
assign irqo = irqenc != 4'h0;
assign nmio = nmii & ie[0];
 
// irq requests are latched on every clock edge to prevent
// misreads
// nmi is not encoded
always @(posedge clk_i)
case (1'b1)
i1&ie[1]: irqenc <= 4'd1;
i2&ie[2]: irqenc <= 4'd2;
i3&ie[3]: irqenc <= 4'd3;
i4&ie[4]: irqenc <= 4'd4;
i5&ie[5]: irqenc <= 4'd5;
i6&ie[6]: irqenc <= 4'd6;
i7&ie[7]: irqenc <= 4'd7;
i8&ie[8]: irqenc <= 4'd8;
i9&ie[9]: irqenc <= 4'd9;
i10&ie[10]: irqenc <= 4'd10;
i11&ie[11]: irqenc <= 4'd11;
i12&ie[12]: irqenc <= 4'd12;
i13&ie[13]: irqenc <= 4'd13;
i14&ie[14]: irqenc <= 4'd14;
i15&ie[15]: irqenc <= 4'd15;
default: irqenc <= 4'd0;
endcase
 
assign vecno = pVECNO|irqenc;
 
endmodule
/trunk/rtl/verilog/byte_rts.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// Eight bit mode RTS/RTL states
//
BYTE_RTS1:
/trunk/rtl/verilog/plp.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
PLP1:
if (unCachedData) begin
cyc_o <= 1'b1;
/trunk/rtl/verilog/rtf65002d.v
1,3 → 1,31
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// rtf65002.v
// - 32 bit CPU
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// 9000 LUT's / 850 ff's / 56 MHz
// 15 Block RAMs
// ============================================================================
//
`define TRUE 1'b1
`define FALSE 1'b0
 
332,6 → 360,10
`define TSB_ZPX 8'h04
`define TSB_ABS 8'h0C
 
`define BAZ 8'hC1
`define BXZ 8'hD1
`define BEQ_RR 8'hE2
 
module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
input wclk;
input wr;
350,7 → 382,7
rpc <= pc;
 
// memL and memH combined allow a 64 bit read
syncRam1kx32_1rw1r ramL0
syncRam2kx32_1rw1r ramL0
(
.wrst(1'b0),
.wclk(wclk),
357,17 → 389,17
.wce(~adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[12:3]),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[12:3]),
.radr(pc[13:3]),
.o(insn0[31:0])
);
 
syncRam1kx32_1rw1r ramH0
syncRam2kx32_1rw1r ramH0
(
.wrst(1'b0),
.wclk(wclk),
374,17 → 406,17
.wce(adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[12:3]),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[12:3]),
.radr(pc[13:3]),
.o(insn0[63:32])
);
 
syncRam1kx32_1rw1r ramL1
syncRam2kx32_1rw1r ramL1
(
.wrst(1'b0),
.wclk(wclk),
391,17 → 423,17
.wce(~adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[12:3]),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[12:3]),
.radr(pcp8[13:3]),
.o(insn1[31:0])
);
 
syncRam1kx32_1rw1r ramH1
syncRam2kx32_1rw1r ramH1
(
.wrst(1'b0),
.wclk(wclk),
408,13 → 440,13
.wce(adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[12:3]),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[12:3]),
.radr(pcp8[13:3]),
.o(insn1[63:32])
);
 
451,30 → 483,42
always @(posedge rclk)
rpcp8 <= pcp8;
 
syncRam512x32_1rw2r ram0 (
syncRam1kx32_1rw1r ram0 (
.wrst(1'b0),
.wclk(wclk),
.wce(adr[3:2]==2'b11),
.we(wr),
.wadr(adr[12:4]),
.wsel(4'hF),
.wadr(adr[13:4]),
.i(adr[31:0]),
.wo(),
 
.rrsta(1'b0),
.rclka(rclk),
.rcea(1'b1),
.radra(pc[12:4]),
.roa(tag0),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[13:4]),
.o(tag0)
);
 
.rrstb(1'b0),
.rclkb(rclk),
.rceb(1'b1),
.radrb(pcp8[12:4]),
.rob(tag1)
syncRam1kx32_1rw1r ram1 (
.wrst(1'b0),
.wclk(wclk),
.wce(adr[3:2]==2'b11),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:4]),
.i(adr[31:0]),
.wo(),
 
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[13:4]),
.o(tag1)
);
 
assign hit0 = tag0[31:13]==rpc[31:13];
assign hit1 = tag1[31:13]==rpcp8[31:13];
assign hit0 = tag0[31:14]==rpc[31:14] && tag0[0];
assign hit1 = tag1[31:14]==rpcp8[31:14] && tag1[0];
 
endmodule
 
565,7 → 609,7
parameter LOAD_IBUF1 = 3'd3;
parameter LOAD_IBUF2 = 3'd4;
parameter LOAD_IBUF3 = 3'd5;
parameter RESET = 7'd0;
parameter RESET1 = 7'd0;
parameter IFETCH = 7'd1;
parameter JMP_IND1 = 7'd2;
parameter JMP_IND2 = 7'd3;
662,6 → 706,8
parameter BYTE_PLP2 = 7'd96;
parameter BYTE_PLA1 = 7'd97;
parameter BYTE_PLA2 = 7'd98;
parameter WAIT_DHIT = 7'd99;
parameter RESET2 = 7'd100;
 
input rst_i;
input clk_i;
681,6 → 727,7
output reg [31:0] dat_o;
 
reg [6:0] state;
reg [6:0] retstate;
reg [2:0] cstate;
wire [55:0] insn;
reg [55:0] ibuf;
688,6 → 735,7
 
reg cf,nf,zf,vf,bf,im,df,em;
reg em1;
reg gie;
reg nmoi; // native mode on interrupt
wire [31:0] sr = {nf,vf,em,24'b0,bf,df,im,zf,cf};
wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
760,8 → 808,10
wire [31:0] iapy8 = ia + y[7:0];
reg isInsnCacheLoad;
reg isDataCacheLoad;
reg isCacheReset;
wire hit0,hit1;
wire dhit;
reg write_allocate;
reg wr;
reg [3:0] wrsel;
reg [31:0] radr;
813,8 → 863,8
 
tagmem tgm0 (
.wclk(clk_i),
.wr(ack_i & isInsnCacheLoad),
.adr(adr_o),
.wr((ack_i & isInsnCacheLoad)|isCacheReset),
.adr({adr_o[31:1],!isCacheReset}),
.rclk(~clk_i),
.pc(pc),
.hit0(hit0),
900,6 → 950,8
`BVC: takb <= !vf;
`BRA: takb <= 1'b1;
`BRL: takb <= 1'b1;
//`BAZ: takb <= acc8==8'h00;
//`BXZ: takb <= x8==8'h00;
default: takb <= 1'b0;
endcase
 
906,6 → 958,7
wire [31:0] zpx_address = dp + ir[15:8] + x8;
wire [31:0] zpy_address = dp + ir[15:8] + y8;
wire [31:0] zp_address = dp + ir[15:8];
wire [31:0] abs_address = {16'h0,ir[23:8]};
wire [31:0] absx_address = {16'h0,ir[23:8] + {8'h0,x8}};
wire [31:0] absy_address = {16'h0,ir[23:8] + {8'h0,y8}};
wire [31:0] zpx32xy_address = dp + ir[23:12] + rfoa;
959,8 → 1012,9
dmiss <= `FALSE;
dcacheOn <= 1'b0;
icacheOn <= 1'b1;
write_allocate <= 1'b0;
nmoi <= 1'b1;
state <= RESET;
state <= RESET1;
cstate <= IDLE;
vect <= `RST_VECT;
pc <= 32'hFFFFFFF0;
967,6 → 1021,8
bufadr <= 32'd0;
dp <= 32'd0;
clk_en <= 1'b1;
isCacheReset <= `TRUE;
gie <= 1'b0;
end
else begin
wr <= 1'b0;
975,8 → 1031,16
if (nmi_i|nmi1)
clk_en <= 1'b1;
case(state)
RESET:
RESET1:
begin
adr_o <= adr_o + 32'd4;
if (adr_o[13:4]==10'h3FF) begin
state <= RESET2;
isCacheReset <= `FALSE;
end
end
RESET2:
begin
vect <= `RST_VECT;
radr <= vect[31:2];
state <= JMP_IND1;
983,7 → 1047,7
end
IFETCH:
begin
if (nmi_edge & !imiss) begin // imiss indicates cache controller is active and this state is in a waiting loop
if (nmi_edge & !imiss & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop
nmi_edge <= 1'b0;
wai <= 1'b0;
bf <= 1'b0;
1022,7 → 1086,7
state <= IRQ1;
end
end
else if (irq_i && !imiss) begin
else if (irq_i && !imiss & gie) begin
if (im) begin
wai <= 1'b0;
if (unCachedInsn) begin
1107,7 → 1171,7
`TAY,`TXY,`DEY,`INY: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
`TAX,`TYX,`TSX,`DEX,`INX: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
`TSA,`TYA,`TXA,`INA,`DEA: begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
`TAS,`TXS: sp <= res8[7:0];
`TAS,`TXS: begin sp <= res8[7:0]; end
`ADC_IMM:
begin
acc[7:0] <= df ? bcaio : res8;
1183,7 → 1247,7
`EMM: em <= 1'b1;
`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
`TAS,`TXS: isp <= res;
`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
`TRS:
begin
1192,12 → 1256,30
$display("res=%h",res);
icacheOn <= res[0];
dcacheOn <= res[1];
write_allocate <= res[2];
end
4'h1: dp <= res;
4'hE: sp <= res[7:0];
4'hF: isp <= res;
4'hE: begin sp <= res[7:0]; end
4'hF: begin isp <= res; gie <= 1'b1; end
endcase
end
`RR:
case(ir[23:20])
`ADD_RR: begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
`SUB_RR:
if (Rt==4'h0) // CMP doesn't set overflow
begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
else
begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
`AND_RR:
if (Rt==4'h0) // BIT sets overflow
begin nf <= resn32; vf <= res[30]; zf <= resz32; end
else
begin nf <= resn32; zf <= resz32; end
`OR_RR: begin nf <= resn32; zf <= resz32; end
`EOR_RR: begin nf <= resn32; zf <= resz32; end
`MUL_RR: begin nf <= resn32; zf <= resz32; end
endcase
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR: begin cf <= resc32; nf <= resn32; zf <= resz32; end
`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
1244,7 → 1326,6
if (em) begin
state <= IFETCH;
case(ir[7:0])
// `XCE: begin pc <= pc + 32'd1; state <= IFETCH; end
`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end
`NAT: pc <= pc + 32'd1;
`NOP: pc <= pc + 32'd1;
1445,15 → 1526,15
`BIT_ABS:
begin
pc <= pc + 32'd3;
radr <= ir[23:10];
radr2LSB <= ir[9:8];
radr <= abs_address[31:2];
radr2LSB <= abs_address[1:0];
state <= LOAD1;
end
`STA_ABS:
begin
pc <= pc + 32'd3;
wadr <= ir[23:10];
wadr2LSB <= ir[9:8];
wadr <= abs_address[31:2];
wadr2LSB <= abs_address[1:0];
wdat <= {4{acc8}};
state <= STORE1;
end
1460,8 → 1541,8
`STX_ABS:
begin
pc <= pc + 32'd3;
wadr <= ir[23:10];
wadr2LSB <= ir[9:8];
wadr <= abs_address[31:2];
wadr2LSB <= abs_address[1:0];
wdat <= {4{x8}};
state <= STORE1;
end // Handle abs,x
1468,8 → 1549,8
`STY_ABS:
begin
pc <= pc + 32'd3;
wadr <= ir[23:10];
wadr2LSB <= ir[9:8];
wadr <= abs_address[31:2];
wadr2LSB <= abs_address[1:0];
wdat <= {4{y8}};
state <= STORE1;
end
1476,8 → 1557,8
`STZ_ABS:
begin
pc <= pc + 32'd3;
wadr <= ir[23:10];
wadr2LSB <= ir[9:8];
wadr <= abs_address[31:2];
wadr2LSB <= abs_address[1:0];
wdat <= {4{8'h00}};
state <= STORE1;
end
1556,7 → 1637,7
end
`JMP:
begin
pc[15:0] <= ir[23:8];
pc[15:0] <= abs_address[15:0];
state <= IFETCH;
end
`JML:
1566,13 → 1647,13
end
`JMP_IND:
begin
radr <= ir[23:10];
radr2LSB <= ir[9:8];
radr <= abs_address[31:2];
radr2LSB <= abs_address[1:0];
state <= BYTE_JMP_IND1;
end
`JMP_INDX:
begin
radr <= absx_address[15:2];
radr <= absx_address[31:2];
radr2LSB <= absx_address[1:0];
state <= BYTE_JMP_IND1;
end
1818,12 → 1899,11
`TAX,`TAY,`TAS: begin res <= acc; pc <= pc + 32'd1; end
`TYA,`TYX: begin res <= y; pc <= pc + 32'd1; end
`TRS: begin
$display("Ra=%h,set res=%h", Ra, rfoa);
res <= rfoa; pc <= pc + 32'd2; end
`TSR: begin
Rt <= ir[15:12];
case(ir[11:8])
4'h0: res <= {dcacheOn,icacheOn};
4'h0: res <= {write_allocate,dcacheOn,icacheOn};
4'h1: res <= dp;
4'h2: res <= prod[31:0];
4'h3: res <= prod[63:32];
1839,69 → 1919,46
 
`RR:
begin
a <= rfoa;
b <= rfob;
case(ir[23:20])
`ADD_RR: res <= rfoa + rfob;
`SUB_RR: res <= rfoa - rfob;
`AND_RR: res <= rfoa & rfob;
`OR_RR: res <= rfoa | rfob;
`EOR_RR: res <= rfoa ^ rfob;
`MUL_RR: begin res <= rfoa * rfob; prod <= rfoa * rfob; end
endcase
Rt <= ir[19:16];
pc <= pc + 32'd3;
state <= CALC;
end
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR:
begin
a <= rfoa;
Rt <= ir[15:12];
pc <= pc + 32'd2;
state <= CALC;
end
`ADD_IMM8:
begin
res <= rfoa + {{24{ir[23]}},ir[23:16]};
Rt <= ir[15:12];
pc <= pc + 32'd3;
state <= IFETCH;
end
`SUB_IMM8,`OR_IMM8,`AND_IMM8,`EOR_IMM8:
begin
a <= rfoa;
b <= {{24{ir[23]}},ir[23:16]};
Rt <= ir[15:12];
pc <= pc + 32'd3;
state <= CALC;
end
`ADD_IMM16,`SUB_IMM16,`OR_IMM16,`AND_IMM16,`EOR_IMM16:
begin
a <= rfoa;
b <= {{16{ir[31]}},ir[31:16]};
Rt <= ir[15:12];
pc <= pc + 32'd4;
state <= CALC;
end
`ADD_IMM32,`SUB_IMM32,`OR_IMM32,`AND_IMM32,`EOR_IMM32,`CMP_IMM32:
begin
a <= rfoa;
b <= ir[47:16];
Rt <= ir[15:12];
pc <= pc + 32'd6;
state <= CALC;
end
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32:
begin
res <= ir[39:8];
pc <= pc + 32'd5;
state <= IFETCH;
end
`LDX_IMM16,`LDA_IMM16:
begin
res <= {{16{ir[23]}},ir[23:8]};
pc <= pc + 32'd3;
state <= IFETCH;
end
`LDX_IMM8,`LDA_IMM8:
begin
res <= {{24{ir[15]}},ir[15:8]};
$display("set res=%h",{{24{ir[15]}},ir[15:8]});
pc <= pc + 32'd2;
state <= IFETCH;
end
`ASL_RR: begin res <= {rfoa,1'b0}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
`ROL_RR: begin res <= {rfoa,cf}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
 
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
 
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
`ADD_IMM32: begin res <= rfoa + ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
`SUB_IMM32: begin res <= rfoa - ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
 
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: begin res <= ir[39:8]; pc <= pc + 32'd5; end
`LDX_IMM16,`LDA_IMM16: begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pc + 32'd3; end
`LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end
 
`LDX_ZPX,`LDY_ZPX:
begin
radr <= zpx32xy_address;
2046,17 → 2103,20
end
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND,`ST_RIND:
begin
radr <= rfob;
wadr <= rfob; // for store
wdat <= rfoa;
a <= rfoa;
if (ir[7:0]==`ST_RIND) begin
res <= rfoa; // for ST_IX, Rt=0
pc <= pc + 32'd2;
state <= STORE1;
end
else begin
Rt <= ir[19:16];
pc <= pc + 32'd3;
state <= LOAD1;
end
radr <= rfob;
state <= IX1;
end
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
begin
2296,6 → 2356,35
pc <= pc + 32'd2;
end
end
/* `BEQ_RR:
begin
state <= IFETCH;
if (ir[23:16]==8'h00) begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc + 32'd2;
vect <= `SLP_VECT;
state <= IRQ1;
end
else if (ir[23:16]==8'h1) begin
if (rfoa==rfob)
pc <= pc + {{16{ir[39]}},ir[39:24]};
else
pc <= pc + 32'd5;
end
else begin
if (takb)
pc <= pc + {{24{ir[23]}},ir[23:16]};
else
pc <= pc + 32'd3;
end
end*/
`BRL:
begin
if (ir[23:8]==16'h0000) begin
2440,6 → 2529,7
// Clear any previously set lock status
STORE2:
if (ack_i) begin
state <= IFETCH;
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
2451,8 → 2541,15
wrsel <= sel_o;
wr <= 1'b1;
end
state <= IFETCH;
else if (write_allocate) begin
dmiss <= `TRUE;
state <= WAIT_DHIT;
retstate <= IFETCH;
end
end
WAIT_DHIT:
if (dhit)
state <= retstate;
 
`include "byte_ix.v"
`include "byte_iy.v"
2580,6 → 2677,8
 
JSR1:
if (ack_i) begin
state <= IFETCH;
retstate <= IFETCH;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
2592,13 → 2691,19
wrsel <= sel_o;
wr <= 1'b1;
end
state <= IFETCH;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
 
`include "byte_jsr.v"
`include "byte_jsl.v"
 
JSR_INDX1:
if (ack_i) begin
state <= JMP_IND1;
retstate <= JMP_IND1;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
2611,10 → 2716,15
wrsel <= sel_o;
wr <= 1'b1;
end
state <= JMP_IND1;
else if (write_allocate) begin
dmiss <= `TRUE;
state <= WAIT_DHIT;
end
end
BYTE_JSR_INDX1:
if (ack_i) begin
state <= BYTE_JSR_INDX2;
retstate <= BYTE_JSR_INDX2;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
2623,7 → 2733,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_JSR_INDX2;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
BYTE_JSR_INDX2:
begin
2648,6 → 2761,8
end
BYTE_JSR_INDX3:
if (ack_i) begin
state <= BYTE_JMP_IND1;
retstate <= BYTE_JMP_IND1;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
2660,10 → 2775,15
wrsel <= sel_o;
wr <= 1'b1;
end
state <= BYTE_JMP_IND1;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
JSR161:
if (ack_i) begin
state <= IFETCH;
retstate <= IFETCH;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
2674,7 → 2794,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= IFETCH;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
 
`include "byte_plp.v"
2685,6 → 2808,8
 
PHP1:
if (ack_i) begin
state <= IFETCH;
retstate <= IFETCH;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
2696,7 → 2821,10
wr <= 1'b1;
wrsel <= sel_o;
end
state <= IFETCH;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
`include "plp.v"
`include "pla.v"
2706,6 → 2834,8
 
IRQ1:
if (ack_i) begin
state <= IRQ2;
retstate <= IRQ2;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
2715,7 → 2845,10
wrsel <= sel_o;
wr <= 1'b1;
end
state <= IRQ2;
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
IRQ2:
begin
2732,6 → 2865,8
end
IRQ3:
if (ack_i) begin
state <= JMP_IND1;
retstate <= JMP_IND1;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
2741,8 → 2876,11
wrsel <= sel_o;
wr <= 1'b1;
end
else if (write_allocate) begin
dmiss <= `TRUE;
state <= WAIT_DHIT;
end
radr <= vect[31:2];
state <= JMP_IND1;
if (!bf)
im <= 1'b1;
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
/trunk/rtl/verilog/rti.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
RTI1:
if (unCachedData) begin
cyc_o <= 1'b1;
/trunk/rtl/verilog/calc.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
CALC:
begin
state <= IFETCH;
27,6 → 49,7
end
else begin
case(ir[7:0])
/* The following handled in the DECODE stage which reduces the CPI at a cost of clock frequency.
`RR:
case(ir[23:20])
`ADD_RR: res <= a + b;
34,11 → 57,11
`AND_RR: res <= a & b; // Also BIT
`OR_RR: res <= a | b;
`EOR_RR: res <= a ^ b;
// `MUL_RR: prod <= a * b; // slows the whole core down
endcase
`MUL_RR: prod <= a * b; // slows the whole core down
endcase*/
`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: begin res <= a + b; end
`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: begin res <= a - b; end // Also CMP
`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: begin res <= a & b; $display("AND_ABS: %h", a & b); end // Also BIT
`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: begin res <= a & b; end // Also BIT
`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: begin res <= a | b; end // Also LD
`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: begin res <= a ^ b; end
`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin res <= b; end
/trunk/rtl/verilog/byte_ix.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
BYTE_IX1:
if (unCachedData) begin
/trunk/rtl/verilog/byte_jmp_ind.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
BYTE_JMP_IND1:
if (unCachedData) begin
cyc_o <= 1'b1;
/trunk/rtl/verilog/byte_iy.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// Indirect Y addressing mode eg. LDA ($12),y
BYTE_IY1:
if (unCachedData) begin
/trunk/rtl/verilog/cache_controller.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// Cache controller
// Also takes care of loading the instruction buffer for non-cached access
//
/trunk/rtl/verilog/rts.v
1,3 → 1,25
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
RTS1:
if (unCachedData) begin
cyc_o <= 1'b1;

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