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/trunk/rtl/verilog/VT151.v
0,0 → 1,56
// ============================================================================
// 2007 Robert Finch
// robfinch@<remove>sympatico.ca
//
// 74LS151 mux
// 8-to-1 mux with enable
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module VT151(e_n, s, i0, i1, i2, i3, i4, i5, i6, i7, z, z_n);
parameter WID=1;
input e_n;
input [2:0] s;
input [WID:1] i0;
input [WID:1] i1;
input [WID:1] i2;
input [WID:1] i3;
input [WID:1] i4;
input [WID:1] i5;
input [WID:1] i6;
input [WID:1] i7;
output [WID:1] z;
output [WID:1] z_n;
 
reg [WID:1] z;
 
always @(e_n or s or i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7)
case({e_n,s})
4'b0000: z <= i0;
4'b0001: z <= i1;
4'b0010: z <= i2;
4'b0011: z <= i3;
4'b0100: z <= i4;
4'b0101: z <= i5;
4'b0110: z <= i6;
4'b0111: z <= i7;
default: z <= {WID{1'b0}};
endcase
 
assign z_n = ~z;
 
endmodule
/trunk/rtl/verilog/change_det.v
0,0 → 1,41
// ============================================================================
// 2006 Robert Finch
// robfinch@<remove>sympatico.ca
//
// change_det.v
// - detects a change in a value
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module change_det(rst, clk, ce, i, cd);
parameter WID=32;
input rst; // reset
input clk; // clock
input ce; // clock enable
input [WID:1] i; // input signal
output cd; // change detected
 
reg [WID:1] hold;
 
always @(posedge clk)
if (rst)
hold <= i;
else if (ce)
hold <= i;
 
assign cd = i != hold;
 
endmodule
/trunk/rtl/verilog/mux4to1.v
0,0 → 1,32
// (C) 2007 Robert T Finch
// All Rights Reserved.
//
// Verilog 1995
//
// Webpack 9.1i xc3s1000-4ft256
// slices / LUTs / MHz
 
module mux4to1(e, s, i0, i1, i2, i3, z);
parameter WID=4;
input e;
input [1:0] s;
input [WID:1] i0;
input [WID:1] i1;
input [WID:1] i2;
input [WID:1] i3;
output [WID:1] z;
reg [WID:1] z;
 
always @(e or s or i0 or i1 or i2 or i3)
if (!e)
z <= {WID{1'b0}};
else begin
case(s)
2'b00: z <= i0;
2'b01: z <= i1;
2'b10: z <= i2;
2'b11: z <= i3;
endcase
end
 
endmodule
/trunk/rtl/verilog/WXGASyncGen1680x1050_60Hz.v
0,0 → 1,92
// ============================================================================
// 2011 Robert Finch
//
// WXGASyncGen1680x1050_60Hz.v
// WXGA sync generator
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// WXGA video sync generator.
//
// Input clock: 73.529 MHz (50 MHz * 25/17)
// Horizontal freq: 65.186 kHz (generated)
// Vertical freq: 59.968 Hz (generated)
//
// This module generates the basic sync timing signals required for a
// WXGA display.
//
// Note to self
// Webpack 13.1i xc3s1200e-4fg320
// 26 FF's / 53 slices / 97 LUTs / 152.532 MHz (speed Spartan3e-4)
// ============================================================================
 
module WXGASyncGen1680x1050_60Hz(rst, clk, hSync, vSync, blank, border, eol, eof);
// 147.136320 MHz
// 73.56816 Mhz
// 73.529412 MHz actual 50 * 25/17
parameter phSyncOn = 48; // 48 front porch
parameter phSyncOff = 136; // 92 sync
parameter phBlankOff = 280; // 144 back porch
parameter phBorderOff = 284; // 4 border
parameter phBorderOn = 1124; // 840 display
parameter phBlankOn = 1128; // 4 border
parameter phTotal = 1128; // 1128 total clocks
// 65220 = 60 * 1088 kHz
parameter pvSyncOn = 1; // 1 front porch
parameter pvSyncOff = 4; // 3 vertical sync
parameter pvBlankOff = 34; // 30 back porch
parameter pvBorderOff = 36; // 2 border
parameter pvBorderOn = 1086; // 1050 display
parameter pvBlankOn = 1087; // 1 border
parameter pvTotal = 1087; // 1087 total scan lines
// 60 Hz
// 840x1050
input rst; // reset
input clk; // video clock
output hSync, vSync; // sync outputs
output blank; // blanking output
output border;
output eol; // end of line
output eof; // end of frame
 
//---------------------------------------------------------------------
//---------------------------------------------------------------------
 
wire [11:0] hCtr; // count from 1 to 2256
wire [11:0] vCtr; // count from 1 to 1087
 
wire vBlank, hBlank;
reg blank;
reg border;
reg hSync,vSync;
 
assign eol = hCtr == phTotal;
assign eof = vCtr == pvTotal && eol;
always @(posedge clk) vSync <= vCtr >= pvSyncOn && vCtr < pvSyncOff;
always @(posedge clk) hSync <= !(hCtr >= phSyncOn && hCtr < phSyncOff);
assign vBlank = vCtr >= pvBlankOn || vCtr < pvBlankOff;
assign hBlank = hCtr >= phBlankOn || hCtr < phBlankOff;
assign vBorder = vCtr >= pvBorderOn || vCtr < pvBorderOff;
assign hBorder = hCtr >= phBorderOn || hCtr < phBorderOff;
 
counter #(12) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(eol), .d(12'd1), .q(hCtr) );
counter #(12) u2 (.rst(rst), .clk(clk), .ce(eol), .ld(eof), .d(12'd1), .q(vCtr) );
 
always @(posedge clk) blank <= hBlank|vBlank;
always @(posedge clk) border <= hBorder|vBorder;
 
endmodule
 
/trunk/rtl/verilog/rtf68kSys.v
0,0 → 1,913
// ============================================================================
// rtf68kSys.v
// - 68k Test System
//
//
// 2010-2011 Robert Finch
// robfinch<remove>@FPGAfield.ca
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
// ============================================================================
 
module rtf68kSys
(
xclk,
// ifclk,
gclk1,
btn,
swt,
kclk, kd,
an, ssg,
led,
ram_a, ram_d, ram_oe, ram_we, ram_lb, ram_ub, ram_clk, ram_adv, ram_ce, ram_cre, ram_wait,
flash_ce, flash_st, flash_rp,
hSync,vSync,red,green,blue,
dac_sclk, dac_sync, dac_d,
rst1626,clk1626,dq1626,
eppAstb, eppDstb, eppWr, eppRst, eppDB, eppWait,
rxd, txd
);
input xclk;
//input ifclk;
input gclk1;
input [3:0] btn;
input [7:0] swt;
inout kclk;
tri kclk;
inout kd;
tri kd;
output [3:0] an;
output [7:0] ssg;
output [7:0] led;
 
output tri [23:1] ram_a;
inout tri [15:0] ram_d;
output tri ram_lb;
output tri ram_ub;
output tri ram_clk;
output tri ram_adv;
output tri ram_cre;
input ram_wait;
output tri ram_oe;
output tri ram_ce;
output tri ram_we;
output tri flash_ce;
input flash_st;
output tri flash_rp;
 
output tri hSync;
output tri vSync;
output [2:0] red;
output [2:0] green;
output [1:0] blue;
 
output dac_sclk;
output dac_sync;
output dac_d;
 
output rst1626;
output clk1626;
inout dq1626;
 
input eppAstb;
input eppDstb;
input eppWr;
input eppRst;
inout [7:0] eppDB;
output eppWait;
 
input rxd;
output txd;
 
reg [31:0] adr;
reg [15:0] dbi;
wire [15:0] dbo;
wire as,uds,lds;
wire rw;
wire ulds = uds&lds;
wire sys_cyc = !as;
wire sys_stb = !ulds;
wire sys_we = !rw;
wire [1:0] sys_sel = ~{uds,lds};
wire [31:0] cpu_adr;
reg [15:0] valreg;
wire clk50;
wire video_clk;
wire vclk5x;
wire [2:0] vcti;
wire vcyc_o;
wire vstb_o;
wire vack_i;
wire [43:0] vadr_o;
wire [15:0] vdat_i;
wire [23:0] rgbo;
 
//assign red = rgbo[7:5];
//assign green = rgbo[4:2];
//assign blue = rgbo[1:0];
 
wire rom_dtack;
wire vec_dtack;
wire dtack;
 
wire pulse1000Hz;
wire blank,eol,eof;
 
wire [7:0] busEppOut;
reg [7:0] busEppIn;
wire ctlEppDwrOut;
wire ctlEppRdCycleOut;
wire [7:0] regEppAdrOut;
wire HandShakeReqIn,HandShakeReqIn2;
wire ctlEppStartOut;
wire ctlEppDoneIn,ctlEppDoneIn2;
 
wire [7:0] busMemDB,busMemDB2;
wire csMemctrl;
 
wire [15:0] mcDB;
wire [23:1] mcAD;
wire mcRamCS;
wire mcFlashCS;
wire mcMemWr;
wire mcMemOe;
wire mcMemUb;
wire mcMemLb;
wire mcMemCRE;
wire mcRamAdv;
wire mcRamClk;
wire mcRamWait;
wire mcFlashRp;
wire mcFlashStSts;
wire mcMemCtrlEnabled;
 
wire ffRamCRE;
wire ffRamAdv;
wire ffRamClk;
wire [15:0] ffRamDB;
wire [23:1] ffRamAD;
wire ffRamWe;
wire ffRamWeh;
wire ffRamCe;
wire ffRamOe;
wire ffRamUb;
wire ffRamLb;
wire ffFlashCe;
wire ffFlashRp;
wire ram_dtack;
wire ram_ack;
wire [15:0] ram_dat;
 
wire mysa;
wire [47:0] startAddress;
wire [7:0] mysaout;
wire saTrigger;
 
wire kbd_ack;
wire [15:0] kbd_dbo;
wire kbd_irq;
wire kbd_rst;
 
wire tc_ack;
wire [15:0] tc_dbo;
 
wire [15:0] dsc_rgbo;
wire dsc_ack;
wire [15:0] dsc_dbo;
 
wire [7:0] bm_rgbo;
wire [23:0] tx_rgbo;
wire bmc_ack;
wire [15:0] bmc_dbo;
 
wire sc_ack;
wire [15:0] sc_dat_o;
wire [23:0] sc_rgbo;
 
wire psg_ack;
wire [15:0] psg_dbo;
wire [11:0] psg_o;
wire psg_cyc;
wire psg_stb;
wire psg_we;
wire [1:0] psg_sel;
 
wire [7:0] uart_dbo;
wire uart_ack;
 
wire [15:0] rnd_dbo;
wire rnd_ack;
 
wire [15:0] tmp_dbo;
wire tmp_ack;
 
wire gra_ack;
wire gr_cyc_o;
wire gr_stb_o;
wire gr_we_o;
wire gr_ack_i;
wire [1:0] gr_sel_o;
wire [31:0] gr_adr_o;
wire [15:0] gr_dat_i;
wire [15:0] gr_dat_o;
 
wire sp_cyc_o;
wire sp_stb_o;
wire sp_we_o;
wire sp_ack_i;
wire [1:0] sp_sel_o;
wire [31:0] sp_adr_o;
wire [15:0] sp_dat_i;
wire [15:0] sp_dat_o;
 
// system clock generator
rtf68kSysClkgen u1
(
.xreset(btn[0]), // external reset
.xclk(xclk), // external clock source (100MHz)
.rst(rst), // system reset
.clk50(clk50), // system clock - 60.000 MHz
.clk25(clk25), // system clock - 10.000 MHz
.vclk(video_clk), // video clock - 73.529 MHz
.vclk5(vclk5x),
.pulse1000Hz(pulse1000Hz) // 1000 Hz timing pulse
);
 
assign red = rgbo[23:21];
assign green = rgbo[15:13];
assign blue = rgbo[7:6];
 
// XGA Timing generator
WXGASyncGen1680x1050_60Hz u2
(
.rst(rst),
.clk(video_clk),
.hSync(hSync),
.vSync(vSync),
.blank(blank),
.border(),
.eol(eol),
.eof(eof)
);
 
FF_PS2KbdToAscii kbd1
(
.rst_i(rst),
.clk_i(clk25),
.cyc_i(sys_cyc),
.stb_i(sys_stb),
.ack_o(kbd_ack),
.adr_i({12'hFFF,cpu_adr}), // FFF_FFDC_000x
.dat_o(kbd_dbo),
// .vol_o(),
.kclk(kclk),
.kd(kd),
.irq(kbd_irq),
.rst_o(kbd_rst)
);
 
rtfSimpleUart #(16666667) uuart
(
// WISHBONE Slave interface
.rst_i(rst), // reset
.clk_i(clk25), // eg 100.7MHz
.cyc_i(sys_cyc), // cycle valid
.stb_i(sys_stb), // strobe
.we_i(sys_we), // 1 = write
.adr_i(cpu_adr), // register address
.dat_i(dbo[7:0]), // data input bus
.dat_o(uart_dbo), // data output bus
.ack_o(uart_ack), // transfer acknowledge
.vol_o(), // volatile register selected
.irq_o(), // interrupt request
//----------------
.cts_ni(1'b0), // clear to send - active low - (flow control)
.rts_no(), // request to send - active low - (flow control)
.dsr_ni(1'b0), // data set ready - active low
.dcd_ni(1'b0), // data carrier detect - active low
.dtr_no(), // data terminal ready - active low
.rxd_i(rxd), // serial data in
.txd_o(txd), // serial data out
.data_present_o()
);
 
//reg [7:0] led;
assign led = eppDB; // Have to set it to something....
 
// Epp interface circuit courtesy Diligent
//
EppCtrl ueppctrl (
.clk(clk25),
.EppAstb(eppAstb),
.EppDstb(eppDstb),
.EppWr(eppWr),
.EppRst(!rst),
.EppDB(eppDB),
.EppWait(eppWait),
.busEppOut(busEppOut),
.busEppIn(busEppIn),
.ctlEppDwrOut(ctlEppDwrOut),
.ctlEppRdCycleOut(ctlEppRdCycleOut),
.regEppAdrOut(regEppAdrOut),
.HandShakeReqIn(HandShakeReqIn|HandShakeReqIn2),
.ctlEppStartOut(ctlEppStartOut),
.ctlEppDoneIn(ctlEppDoneIn|ctlEppDoneIn2)
);
always @(regEppAdrOut or busMemDB or busMemDB2 or mysaout)
casex(regEppAdrOut)
8'b00000xxx: busEppIn <= busMemDB;
8'b00001xxx: busEppIn <= busMemDB2;
8'b10000xxx: busEppIn <= mysaout;
default: busEppIn <= 8'hFF;
endcase
 
 
CompSel ucs1
(
.regEppAdrIn(regEppAdrOut),
.CS0_7(csMemctrl)
);
 
// Responds to epp register address range 0x80-0x86
//
/*
EppStartAddress usa1
(
.rst(rst),
.clk(clk25),
.wr(ctlEppDwrOut),
.ad(regEppAdrOut),
.dbi(busEppOut),
.dbo(mysaout),
.myad(mysa),
.trigger(saTrigger),
.startAddress(startAddress)
);
*/
wire ackLoadedBit = sys_cyc && sys_stb && (cpu_adr[31:8]==24'hFFDD_00);
 
 
// Epp source memory controller - courtesy Diligent
//
NexysOnBoardMemCtrl umemctrl1
(
.clk(clk25),
.HandShakeReqOut(HandShakeReqIn),
.ctlMsmStartIn(ctlEppStartOut),
.ctlMsmDoneOut(ctlEppDoneIn),
.ctlMsmDwrIn(ctlEppDwrOut),
.ctlEppRdCycleIn(ctlEppRdCycleOut),
.EppRdDataOut(busMemDB),
.EppWrDataIn(busEppOut),
.regEppAdrIn(regEppAdrOut),
.ComponentSelect(csMemctrl),
 
.MemDB(mcDB),
.MemAdr(mcAD),
.FlashByte(mcFB),
.RamCS(mcRamCS),
.FlashCS(mcFlashCS),
.MemWR(mcMemWr),
.MemOE(mcMemOe),
.RamUB(mcMemUb),
.RamLB(mcMemLb),
.RamCRE(mcMemCRE),
.RamAdv(mcRamAdv),
.RamClk(mcRamClk),
.RamWait(mcRamWait),
.FlashRp(mcFlashRp),
.FlashStSts(mcFlashStSts),
.MemCtrlEnabled(mcMemCtrlEnabled)
);
 
 
reg bm_owns;
reg [3:0] tcnt;
reg [15:0] cdat_i;
 
wire cs_vec = !as && ((cpu_adr[31:0] < 32'h00000008) || (cpu_adr[31:4]==28'hFFFFFFF));
wire cs_ram = !as && (cpu_adr[31:0] >= 32'h00000008 && cpu_adr[31:16] < 16'hFFD0);
wire cs_rom = !as && (cpu_adr[31:16]==16'hFFFF);
wire cs_stk = !as && (cpu_adr[31:12]==20'hFFFE_0);
wire csThreadNdx = !ulds && (cpu_adr[31:0]==32'hFFDD_0008);
 
//input ram_wait;
 
assign ram_cre = mcMemCtrlEnabled ? mcMemCRE : ffRamCRE;
assign ram_adv = mcMemCtrlEnabled ? mcRamAdv : ffRamAdv;
assign ram_clk = mcMemCtrlEnabled ? mcRamClk : ffRamClk;
assign ram_d = mcMemCtrlEnabled ? (!mcMemWr ? mcDB : 16'hZZZZ) : (!ffRamWeh ? ffRamDB : 16'hZZZZ);
assign mcDB = !mcMemWr ? 16'hZZZZ : ram_d;
assign ffRamDB = !ffRamWe ? 16'hZZZZ : ram_d;
assign ram_a = mcMemCtrlEnabled ? mcAD : ffRamAD;
assign ram_we = mcMemCtrlEnabled ? mcMemWr : ffRamWe;
assign ram_oe = mcMemCtrlEnabled ? mcMemOe : ffRamOe;
assign ram_ce = mcMemCtrlEnabled ? mcRamCS : ffRamCe;
assign ram_lb = mcMemCtrlEnabled ? mcMemLb : ffRamLb;
assign ram_ub = mcMemCtrlEnabled ? mcMemUb : ffRamUb;
assign flash_ce = mcMemCtrlEnabled ? mcFlashCS : ffFlashCe;
assign flash_rp = mcMemCtrlEnabled ? mcFlashRp : ffFlashRp;
assign mcFlashStSts = flash_st;
 
// Responds to epp register address range 0x08-0x0F
//
rtf68kSysRAMCtrl #(16666667) u20
(
.rst_i(rst),
.clk_i(clk25),
.gblen(!mcMemCtrlEnabled),
 
// CPU port
.as(!cs_ram),
.dtack(ram_dtack),
.rw(rw),
.uds(uds),
.lds(lds),
.adr({12'h000,adr}),
.dat_i(dbo),
.dat_o(ram_dat),
 
// Graphics Accelerator
.gr_cyc_i(gr_cyc_o),
.gr_stb_i(gr_stb_o),
.gr_ack_o(gr_ack_i),
.gr_we_i(gr_we_o),
.gr_sel_i(gr_sel_o),
.gr_adr_i(gr_adr_o),
.gr_dat_i(gr_dat_o),
.gr_dat_o(gr_dat_i),
 
// Sprite
.sp_cyc_i(sp_cyc_o),
.sp_stb_i(sp_stb_o),
.sp_ack_o(sp_ack_i),
.sp_we_i(sp_we_o),
.sp_sel_i(sp_sel_o),
.sp_adr_i(sp_adr_o),
.sp_dat_i(sp_dat_o),
.sp_dat_o(sp_dat_i),
 
// Epp Port
.eppRd(ctlEppEdCycleOut),
.eppWr(ctlEppDwrOut),
.eppAdr(regEppAdrOut),
.eppDati(busEppOut),
.eppDato(busMemDB2),
.eppHSreq(HandShakeReqIn2),
.eppStart(ctlEppStartOut),
.eppDone(ctlEppDoneIn2),
 
// Video Port
.vcti_i(vcti),
.vcyc_i(vcyc_o),
.vack_o(vack_i),
.vadr_i(vadr_o),
.vdat_o(vdat_i),
 
// Audio Port
.ar_cyc_i(),
.ar_stb_i(),
.ar_ack_o(),
.ar_we_i(),
.ar_sel_i(),
.ar_adr_i(),
.ar_dat_i(),
.ar_dat_o(),
 
// Audio Port
.ap_cyc_i(psg_cyc),
.ap_stb_i(psg_stb),
.ap_ack_o(),
.ap_we_i(psg_we),
.ap_sel_i(psg_sel),
.ap_adr_i(),
.ap_dat_i(),
.ap_dat_o(),
// PSRam connections
.ram_clk(ffRamClk),
.ram_adv(ffRamAdv),
.ram_cre(ffRamCRE),
.ram_ce(ffRamCe),
.ram_we(ffRamWe),
.ram_oe(ffRamOe),
.ram_lb(ffRamLb),
.ram_ub(ffRamUb),
.ram_a(ffRamAD),
.ram_d(ffRamDB),
.ram_weh(ffRamWeh),
// Flash connections
.flash_ce(ffFlashCe),
.flash_rp(ffFlashRp),
.flash_st(flash_st)
);
 
// Bitmap controller
// 416 x 262 - 8bpp
//
// Responds to address range:
// FFF_FFDA_B0xx
// Uses memory in the range
// 000_0002_0000 to 000_0003_FFFF
// for the bitmap display
//
 
rtfBitmapController u4
(
.rst_i(rst),
.clk_i(clk25),
 
.bte_o(),
.cti_o(vcti),
.cyc_o(vcyc_o),
.stb_o(vstb_o),
.ack_i(vack_i),
.adr_o(vadr_o),
.dat_i(vdat_i),
 
.vclk(video_clk),
.eol(eol),
.eof(eof),
.blank(blank),
.rgbo(bm_rgbo),
.page(1'b0)
);
 
// Text controller overlays bitmap controller output
 
rtfTextController tc1
(
.rst_i(rst),
.clk_i(clk25),
 
.cyc_i(sys_cyc),
.stb_i(sys_stb),
.ack_o(tc_ack),
.we_i(sys_we),
.sel_i(sys_sel),
.adr_i({12'hFFF,cpu_adr}),
.dat_i(dbo),
.dat_o(tc_dbo),
 
.lp(),
.curpos(),
.vclk(video_clk),
.eol(eol),
.eof(eof),
.blank(blank),
.border(),
.rgbIn({bm_rgbo[7:5],5'd0,bm_rgbo[4:2],5'd0,bm_rgbo[1:0],6'b0}),
.rgbOut(tx_rgbo)
);
 
rtfSpriteController sc1
(
// Bus Slave interface
//------------------------------
// Slave signals
.rst_i(rst),
.clk_i(clk25),
.s_cyc_i(sys_cyc),
.s_stb_i(sys_stb),
.s_ack_o(sc_ack),
.s_we_i(sys_we),
.s_sel_i(sys_sel),
.s_adr_i({12'hFFF,adr}),
.s_dat_i(dbo),
.s_dat_o(sc_dat_o),
.vol_o(), // volatile register
//------------------------------
// Bus Master Signals
.m_soc_o(), // start of cycle
.m_cyc_o(sp_cyc_o), // cycle is valid
.m_stb_o(sp_stb_o), // strobe output
.m_ack_i(sp_ack_i), // input data is ready
.m_we_o(sp_we_o), // write (always inactive)
.m_sel_o(sp_sel_o), // byte select
.m_adr_o(sp_adr_o), // DMA address
.m_dat_i(sp_dat_i), // data input
.m_dat_o(sp_dat_o), // data output (always zero)
//--------------------------
.vclk(video_clk),
.hSync(eol),
.vSync(eof),
.blank(blank),
.rgbIn(tx_rgbo),
.rgbOut(sc_rgbo),
.irq()
);
 
assign rgbo =
swt[0] ? {dsc_rgbo[14:10],3'b100,dsc_rgbo[9:5],3'b100,dsc_rgbo[4:0],3'b100} :
swt[1] ? {tx_rgbo[23:0]} :
swt[2] ? {sc_rgbo[23:0]} :
{bm_rgbo[7:5],5'd0,bm_rgbo[4:2],5'd0,bm_rgbo[1:0],6'b0};
 
wire [7:0] ds1307dbo;
 
wire cs_ds1307 = sys_cyc && sys_stb && (cpu_adr==24'hFFD8_03);
wire ds1307ack;
 
reg [3:0] dp;
// Seven segment LED driver
seven_seg #(16666667) ssd0
(
.rst(rst), // reset
.clk(clk25), // clock
.dp(dp),
.val(valreg),
// .val(ssval),
.ssLedAnode(an),
.ssLedSeg(ssg)
);
 
// ADSR Sound generator
//
PSG16 #(17) upsg1
(
.rst_i(rst),
.clk_i(clk25),
.cyc_i(sys_cyc),
.stb_i(sys_stb),
.ack_o(psg_ack),
.we_i(sys_we),
.sel_i(sys_sel),
.adr_i({12'hFFF,cpu_adr}),
.dat_i(dbo),
.dat_o(psg_dbo),
.vol_o(),
 
.bg(),
.m_cyc_o(psg_cyc),
.m_stb_o(psg_stb),
.m_ack_i(),
.m_we_o(psg_we),
.m_sel_o(psg_sel),
.m_adr_o(),
.m_dat_i(),
.o(psg_o)
);
 
dac121s101 udac1
(
.rst_i(rst),
.clk_i(clk25),
.cyc_i(1'b1),
.stb_i(1'b1),
.ack_o(),
.we_i(1'b1),
.dat_i(psg_o),
.sclk(dac_sclk),
.sync(dac_sync),
.d(dac_d)
);
 
 
rtfRandom u13
(
.rst_i(rst),
.clk_i(clk25),
.cyc_i(sys_cyc),
.stb_i(sys_stb),
.ack_o(rnd_ack),
.we_i(sys_we),
.adr_i({12'hFFF,cpu_adr}),
.dat_i(dbo),
.dat_o(rnd_dbo),
.vol_o()
);
 
rtfGraphicsAccelerator u14
(
.rst_i(rst),
.clk_i(clk25),
.s_cyc_i(sys_cyc),
.s_stb_i(sys_stb),
.s_we_i(sys_we),
.s_ack_o(gra_ack),
.s_sel_i(sys_sel),
.s_adr_i(cpu_adr),
.s_dat_i(dbo),
.s_dat_o(),
.m_cyc_o(gr_cyc_o),
.m_stb_o(gr_stb_o),
.m_we_o(gr_we_o),
.m_ack_i(gr_ack_i),
.m_sel_o(gr_sel_o),
.m_adr_o(gr_adr_o),
.m_dat_i(gr_dat_i),
.m_dat_o(gr_dat_o)
);
 
// dtack
// for high whenever address strobe goes inactive
//
reg [4:0] stkdt;
always @(posedge clk25)
if (rst) begin
stkdt <= 5'b00000;
end
else begin
if (cs_stk & !ulds)
stkdt <= {stkdt,1'b1};
else
stkdt <= 5'd0;
end
wire stk_dtack = !stkdt[3] | ulds;
 
assign rom_dtack = !cs_rom;
assign vec_dtack = !cs_vec;
 
assign dtack = ulds | (
rom_dtack
& vec_dtack
& ram_dtack
& !tc_ack
& !ackLoadedBit
// & !dsc_ack
& !kbd_ack
& !uart_ack
& !psg_ack
& !rnd_ack
// & !tmp_ack
& !gra_ack
& !sc_ack
& stk_dtack
// & !ds1307ack
);
 
reg pulse1000HzB;
always @(posedge clk25)
if (rst) begin
pulse1000HzB <= 1'b0;
end
else begin
if (pulse1000Hz)
pulse1000HzB <= 1'b1;
else begin
if (cpu_adr==32'hFFFF0000)
pulse1000HzB <= 1'b0;
end
end
 
wire [2:0] ipl;
 
VT148 u11
(
.en(1'b0),
.i0(1'b1),
.i1(1'b1),
.i2(1'b1),
.i3(1'b1),
.i4(1'b1),
.i5(1'b1),
.i6(!pulse1000HzB),
.i7(!kbd_rst),
.o(ipl),
.gs(),
.eo()
);
 
 
reg [7:0] ThreadNdx;
always @(posedge clk25)
if (rst)
ThreadNdx <= 8'h00;
else begin
if (csThreadNdx && !rw)
ThreadNdx <= dbi[7:0];
end
always @(cpu_adr)
if (cpu_adr[31:8]==24'h000100)
adr <= {16'h0001,ThreadNdx,cpu_adr[7:0]};
else
adr <= cpu_adr;
 
//always @(cpu_adr) adr <= cpu_adr;
 
TG68 u10
(
.clk(clk25),
.reset(!rst),
.clkena_in(1'b1),
.IPL(ipl),
.dtack(dtack),
.addr(cpu_adr),
.data_in(dbi),
.data_out(dbo),
.as(as),
.uds(uds),
.lds(lds),
.rw(rw),
.drive_data()
);
 
wire [15:0] bootromo;
wire [15:0] sysstko;
 
bootrom ubootrom
(
.clk(clk25),
.adr(adr),
.romo(bootromo)
);
 
RAMB16_S18 SYSSTACK0
(
.CLK(clk25),
.ADDR(adr[10:1]),
.DI(dbo),
.DIP(2'b11),
.DO(sysstko),
.EN(cs_stk & !ulds),
.WE(!rw),
.SSR(1'b0)
);
 
always @(adr or kbd_dbo or tc_dbo or cdat_i or
cs_rom or cs_vec or uart_dbo or rnd_dbo or tc_dbo or psg_dbo or
bootromo or ram_dat or bmc_dbo or saTrigger or startAddress)
if (cs_rom) begin
casex(adr[15:0])
16'b0001_xxxx_xxxx_xxxx: dbi <= bootromo;
16'b0010_xxxx_xxxx_xxxx: dbi <= bootromo;
16'b0011_xxxx_xxxx_xxxx: dbi <= bootromo;
default: dbi <= 16'h4e71;
endcase
end
else if (cs_vec) begin
case(adr[15:0])
16'h0000: dbi <= 16'hFFFE; // Reset SSP
16'h0002: dbi <= 16'h07FC;
16'h0004: dbi <= 16'hFFFF; // Reset PC
16'h0006: dbi <= 16'h1100;
// vectors
16'hFFF0: dbi <= 16'd31;
16'hFFF2: dbi <= 16'd30;
16'hFFF4: dbi <= 16'd29;
16'hFFF6: dbi <= 16'd28;
16'hFFF8: dbi <= 16'd28;
16'hFFFA: dbi <= 16'd29;
16'hFFFC: dbi <= 16'd30;
16'hFFFE: dbi <= 16'd31;
default: dbi <= 16'h3000;
endcase
end
else begin
casex(adr & 32'hFFFFFFFE)
32'h00xx_xxxx: dbi <= ram_dat;
32'hFFDC_000x: dbi <= kbd_dbo;
32'hFFDC_0A0x: dbi <= {2{uart_dbo}};
32'hFFDC_0C0x: dbi <= rnd_dbo;
32'hFFD0_xxxx: dbi <= tc_dbo;
32'hFFD1_xxxx: dbi <= tc_dbo;
32'hFFD2_xxxx: dbi <= tc_dbo;
// 32'hFFD8_xxxx: dbi <= sc_dat_o;
32'hFFDA_00xx: dbi <= tc_dbo;
32'hFFD4_00xx: dbi <= psg_dbo;
32'hFFDD_0000: dbi <= {16{saTrigger}};
32'hFFDD_0004: dbi <= startAddress[31:16];
32'hFFDD_0006: dbi <= startAddress[15:0];
32'hFFDD_0008: dbi <= {2{ThreadNdx}};
32'hFFFE_0xxx: dbi <= sysstko;
default: dbi <= 16'h4e71;
endcase
end
 
always @(posedge clk25 or posedge rst)
if (rst) valreg <= 16'h8765;
else begin
if (1'b1) begin
dp <= {cs_rom,cs_vec};
valreg <= btn[1] ? adr[31:16] : adr[15:0];
end
end
 
endmodule
/trunk/rtl/verilog/PSGBusArb.v
0,0 → 1,189
/* ===============================================================
(C) 2007 Robert Finch
All rights reserved.
 
PSGBusArb.v
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
Arbitrates access to the system bus among up to eight
wave table channels for the bcSid. This arbitrator is part
of a tree that ends up looking like a single arbitration
request to the system.
 
Spartan3
19 LUTs / 11 slices
=============================================================== */
 
module PSGBusArb(rst, clk, ce, ack,
req0, req1, req2, req3, req4, req5, req6, req7,
sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, seln);
input rst; // reset
input clk; // clock (eg 100MHz)
input ce; // clock enable (eg 25MHz)
input ack; // bus transfer completed
input req0; // requester 0 wants the bus
input req1; // requester 1 wants the bus
input req2; // ...
input req3;
input req4;
input req5;
input req6;
input req7;
output sel0; // requester 0 granted the bus
reg sel0;
output sel1;
reg sel1;
output sel2;
reg sel2;
output sel3;
reg sel3;
output sel4;
reg sel4;
output sel5;
reg sel5;
output sel6;
reg sel6;
output sel7;
reg sel7;
output [2:0] seln; // who has the bus
reg [2:0] seln;
 
always @(posedge clk) begin
if (rst) begin
sel0 <= 1'b0;
sel1 <= 1'b0;
sel2 <= 1'b0;
sel3 <= 1'b0;
sel4 <= 1'b0;
sel5 <= 1'b0;
sel6 <= 1'b0;
sel7 <= 1'b0;
seln <= 3'd0;
end
else begin
if (ce&ack) begin
if (req0) begin
sel0 <= 1'b1;
sel1 <= 1'b0;
sel2 <= 1'b0;
sel3 <= 1'b0;
sel4 <= 1'b0;
sel5 <= 1'b0;
sel6 <= 1'b0;
sel7 <= 1'b0;
seln <= 3'd0;
end
else if (req1) begin
sel1 <= 1'b1;
sel0 <= 1'b0;
sel2 <= 1'b0;
sel3 <= 1'b0;
sel4 <= 1'b0;
sel5 <= 1'b0;
sel6 <= 1'b0;
sel7 <= 1'b0;
seln <= 3'd1;
end
else if (req2) begin
sel2 <= 1'b1;
sel0 <= 1'b0;
sel1 <= 1'b0;
sel3 <= 1'b0;
sel4 <= 1'b0;
sel5 <= 1'b0;
sel6 <= 1'b0;
sel7 <= 1'b0;
seln <= 3'd2;
end
else if (req3) begin
sel3 <= 1'b1;
sel0 <= 1'b0;
sel1 <= 1'b0;
sel2 <= 1'b0;
sel4 <= 1'b0;
sel5 <= 1'b0;
sel6 <= 1'b0;
sel7 <= 1'b0;
seln <= 3'd3;
end
else if (req4) begin
sel4 <= 1'b1;
sel0 <= 1'b0;
sel1 <= 1'b0;
sel2 <= 1'b0;
sel3 <= 1'b0;
sel5 <= 1'b0;
sel6 <= 1'b0;
sel7 <= 1'b0;
seln <= 3'd4;
end
else if (req5) begin
sel5 <= 1'b1;
sel0 <= 1'b0;
sel1 <= 1'b0;
sel2 <= 1'b0;
sel3 <= 1'b0;
sel4 <= 1'b0;
sel6 <= 1'b0;
sel7 <= 1'b0;
seln <= 3'd5;
end
else if (req6) begin
sel6 <= 1'b1;
sel0 <= 1'b0;
sel1 <= 1'b0;
sel2 <= 1'b0;
sel3 <= 1'b0;
sel4 <= 1'b0;
sel5 <= 1'b0;
sel7 <= 1'b0;
seln <= 3'd6;
end
else if (req7) begin
sel7 <= 1'b1;
sel0 <= 1'b0;
sel1 <= 1'b0;
sel2 <= 1'b0;
sel3 <= 1'b0;
sel4 <= 1'b0;
sel5 <= 1'b0;
sel6 <= 1'b0;
seln <= 3'd7;
end
// otherwise, hold onto last owner
else begin
sel0 <= sel0;
sel1 <= sel1;
sel2 <= sel2;
sel3 <= sel3;
sel4 <= sel4;
sel5 <= sel5;
sel6 <= sel6;
sel7 <= sel7;
seln <= seln;
end
end
end
end
 
endmodule
/trunk/rtl/verilog/syncRam4kx9_1rw1r.v
0,0 → 1,147
// ============================================================================
// 2008,2011 Robert Finch
// robfinch@<remove>sympatico.ca
//
// syncRam4kx9_1rw1r.v
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// ============================================================================
//
`define SYNTHESIS
`define VENDOR_XILINX
`define SPARTAN3
 
module syncRam4kx9_1rw1r(
input wrst,
input wclk,
input wce,
input we,
input [11:0] wadr,
input [8:0] i,
output [8:0] wo,
input rrst,
input rclk,
input rce,
input [11:0] radr,
output [8:0] o
);
 
`ifdef SYNTHESIS
`ifdef VENDOR_XILINX
 
`ifdef SPARTAN3
wire [8:0] o0;
wire [8:0] o1;
wire [8:0] wo0;
wire [8:0] wo1;
wire rrst0 = radr[11];
wire rrst1 = ~radr[11];
wire wrst0 = wadr[11];
wire wrst1 = ~wadr[11];
wire we0 = we & ~wadr[11];
wire we1 = we & wadr[11];
 
RAMB16_S9_S9 ram0(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[7:0]), .DIPA(i[8]), .DOA(wo0[7:0]), .DOPA(wo0[8]), .ENA(wce), .WEA(we0), .SSRA(wrst0),
.CLKB(rclk), .ADDRB(radr), .DIB(8'hFF), .DIPB(1'b1), .DOB(o0[7:0]), .DOPB(o0[8]), .ENB(rce), .WEB(1'b0), .SSRB(rrst0) );
RAMB16_S9_S9 ram1(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[7:0]), .DIPA(i[8]), .DOA(wo1[7:0]), .DOPA(wo1[8]), .ENA(wce), .WEA(we1), .SSRA(wrst1),
.CLKB(rclk), .ADDRB(radr), .DIB(8'hFF), .DIPB(1'b1), .DOB(o1[7:0]), .DOPB(o1[8]), .ENB(rce), .WEB(1'b0), .SSRB(rrst1) );
 
assign o = o0|o1;
assign wo = wo0|wo1;
 
`endif
 
`ifdef SPARTAN2
RAMB4_S1_S1 ram0(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[0]), .DOA(wo[0]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[0]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
RAMB4_S1_S1 ram1(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[1]), .DOA(wo[1]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[1]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
RAMB4_S1_S1 ram2(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[2]), .DOA(wo[2]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[2]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
RAMB4_S1_S1 ram3(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[3]), .DOA(wo[3]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[3]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
RAMB4_S1_S1 ram4(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[4]), .DOA(wo[4]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[4]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
RAMB4_S1_S1 ram5(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[5]), .DOA(wo[5]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[5]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
RAMB4_S1_S1 ram6(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[6]), .DOA(wo[6]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[6]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
RAMB4_S1_S1 ram7(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[7]), .DOA(wo[7]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[7]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
RAMB4_S1_S1 ram8(
.CLKA(wclk), .ADDRA(wadr), .DIA(i[8]), .DOA(wo[8]), .ENA(wce), .WEA(we), .RSTA(wrst),
.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[8]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
`endif
 
`endif
 
`ifdef VENDOR_ALTERA
 
reg [8:0] mem [4095:0];
reg [10:0] rradr;
reg [10:0] rwadr;
 
// register read addresses
always @(posedge rclk)
if (rce) rradr <= radr;
 
assign o = mem[rradr];
 
// write side
always @(posedge wclk)
if (wce) rwadr <= wadr;
 
always @(posedge wclk)
if (wce) mem[wadr] <= i;
 
assign wo = mem[rwadr];
 
`endif
 
`else
 
reg [8:0] mem [4095:0];
reg [10:0] rradr;
reg [10:0] rwadr;
 
// register read addresses
always @(posedge rclk)
if (rce) rradr <= radr;
 
assign o = mem[rradr];
 
// write side
always @(posedge wclk)
if (wce) rwadr <= wadr;
 
always @(posedge wclk)
if (wce) mem[wadr] <= i;
 
assign wo = mem[rwadr];
 
`endif
 
endmodule
/trunk/rtl/verilog/rtfBitmapController.v
0,0 → 1,239
// ============================================================================
// Bitmap Controller (416h x 262v x 8bpp):
// - Displays a bitmap from memory.
// - the video mode timing to be 1680x1050
//
//
// (C) 2008,2010,2011 Robert Finch
// robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// The default base screen address is:
// $20000 - the second 128 kb of RAM
//
//
// Verilog 1995
// Webpack 9.2i xc3s1200-4fg320
// 64 slices / 118 LUTs / 175.009 MHz
// 72 ff's / 2 BRAM (2048x16)
//
// ============================================================================
 
module rtfBitmapController(
rst_i, clk_i, bte_o, cti_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o,
vclk, eol, eof, blank, rgbo, page
);
parameter BM_BASE_ADDR1 = 44'h000_0002_0000;
parameter BM_BASE_ADDR2 = 44'h000_0004_0000;
 
// SYSCON
input rst_i; // system reset
input clk_i; // system bus interface clock
 
// Video Master Port
// Used to read memory via burst access
output [1:0] bte_o;
output [2:0] cti_o;
output cyc_o; // video burst request
output stb_o;
input ack_i; // vid_acknowledge from memory
output we_o;
output [ 1:0] sel_o;
output [43:0] adr_o; // address for memory access
input [15:0] dat_i; // memory data input
output [15:0] dat_o;
 
// Video
input vclk; // Video clock 73.529 MHz
input eol; // end of scan line
input eof; // end of frame
input blank; // blank the output
output [7:0] rgbo; // 8-bit RGB output
reg [7:0] rgbo;
 
input page; // which page to display
 
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// IO registers
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [1:0] bte_o;
reg [2:0] cti_o;
reg cyc_o;
reg stb_o;
reg we_o;
reg [1:0] sel_o;
reg [43:0] adr_o;
reg [15:0] dat_o;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
wire [11:0] hctr; // horizontal reference counter
wire [11:0] vctr; // vertical reference counter
wire [11:0] vctr1 = vctr + 12'd4;
reg [43:0] baseAddr; // base address register
wire [7:0] rgbo1;
reg [11:0] pixelRow;
reg [11:0] pixelCol;
 
always @(page)
baseAddr = page ? BM_BASE_ADDR2 : BM_BASE_ADDR1;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Horizontal and Vertical timing reference counters
// - The memory fetch address is determined from these counters.
// - The counters are setup with negative values so that the zero
// point coincides with the top left of the display.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
counter #(12) u1 (.rst(1'b0), .clk(vclk), .ce(1'b1), .ld(eol), .d(12'hEE4), .q(hctr));
counter #(12) u2 (.rst(1'b0), .clk(vclk), .ce(eol), .ld(eof), .d(12'hFDC), .q(vctr));
 
 
// Pixel row and column are derived from the horizontal and vertical counts.
 
always @(vctr1)
pixelRow = vctr1[11:2];
always @(hctr)
pixelCol = hctr[11:1];
 
wire vFetch = (vctr < 12'd1050) || (vctr > 12'hFF8);
 
// Video Request Block
// 416x262
// - Issue a request for access to memory every 160 clock cycles
// - Reset the request flag once an access has been initiated.
// - 128 bytes (pixels) are read per scan line
// - It takes about 18 clock cycles @ 25 MHz to access 32 bytes of data
// through the memory contoller, or about 53 video clocks
// 83 video clocks with a 16 MHZ memory controller.
 
reg [2:0] vreq;
 
// Must be vclk. vid_req will be active for numerous clock cycles as
// a burst type fetch is used. The ftch and vFetch may only be
// active for a single video clock cycle. vclk must be used so these
// signals are not missed due to a clock domain crossing. We luck
// out here because of the length of time vid_req is active.
//
always @(posedge vclk)
begin
if (vFetch) begin
if (vctr1[1:0]!=2'd3) begin // we only need 13 memory accesses
if (hctr==12'd16) vreq <= 3'b100;
if (hctr==12'd176) vreq <= 3'b101;
if (hctr==12'd336) vreq <= 3'b110;
if (hctr==12'd496) vreq <= 3'b111;
end
else
if (hctr==12'd16) vreq <= 3'b100;
end
if (cyc_o) vreq <= 3'b000;
end
// Cross the clock domain with the request signal
reg do_cyc;
always @(posedge clk_i)
do_cyc <= vreq[2];
 
wire[19:0] rowOffset = pixelRow * 10'd416;
reg [8:0] fetchCol;
 
// - read from assigned video memory address, using burst mode reads
// - 32 pixels at a time are read
// - video data is fetched one pixel row in advance
//
reg [3:0] bcnt;
always @(posedge clk_i)
if (rst_i) begin
bte_o <= 2'b00; // linear burst
cti_o <= 3'b000; // classic cycle
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 2'b00;
we_o <= 1'b0;
adr_o <= 44'h000_0000_0000;
dat_o <= 16'h0000;
fetchCol <= 9'd0;
bcnt <= 4'd0;
end
else begin
if (do_cyc & !cyc_o) begin
cti_o <= 3'b010; // incrementing burst cycle
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 2'b11;
bcnt <= 4'd0;
fetchCol <= {vctr1[1:0],vreq[1:0],5'h00};
// This works out to be an even multiple of 32 bytes
adr_o <= baseAddr + rowOffset + 10'd416 + {vctr1[1:0],vreq[1:0],5'h00};
end
if (cyc_o & ack_i) begin
adr_o <= adr_o + 32'd2;
fetchCol <= fetchCol + 9'd2;
bcnt <= bcnt + 4'd1;
if (bcnt==4'd14)
cti_o <= 3'b111; // end of burst
if (bcnt==4'd15) begin
cti_o <= 3'b000; // classic cycles again
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 2'b00;
adr_o <= 44'h000_0000_0000;
end
end
end
 
 
always @(posedge vclk)
rgbo <= rgbo1;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Video Line Buffer
// - gets written in bursts, but read continuously
// - buffer is used as two halves - one half is displayed (read) while
// the other is fetched (write).
// - only the lower eleven bits of the address are used as an index,
// these bits will match with the addresses generated by the burst
// controller above.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
// Storage for 2048x8 bit pixels (2048x8 data)
 
RAMB16_S9_S18 ram0
(
.CLKA(vclk),
.ADDRA({pixelRow[0],pixelCol[8:1],~pixelCol[0]}), // <- pixelCol[0] nonsense, we need the highest pixel first
.DIA(8'hFF),
.DIPA(1'b1),
.DOA(rgbo1),
.ENA(1'b1),
.WEA(1'b0),
.SSRA(blank),
 
.CLKB(clk_i),
.ADDRB({~pixelRow[0],fetchCol[8:1]}),
.DIB(dat_i),
.DIPB(2'b11),
.DOB(),
.ENB(cyc_o),
.WEB(ack_i),
.SSRB(1'b0)
);
 
endmodule
/trunk/rtl/verilog/ParallelToSerial.v
0,0 → 1,47
// ============================================================================
// 2006,2007,2011 Robert Finch
// robfinch@<remove>sympatico.ca
//
// ParallelToSerial.v
// Parallel to serial data converter (shift register).
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module ParallelToSerial(rst, clk, ce, ld, qin, d, qh);
parameter WID=8;
input rst; // reset
input clk; // clock
input ce; // clock enable
input ld; // load
input qin; // serial shifting input
input [WID:1] d; // data to load
output qh; // serial output
 
reg [WID:1] q;
 
always @(posedge clk)
if (rst)
q <= 0;
else if (ce) begin
if (ld)
q <= d;
else
q <= {q[WID-1:1],qin};
end
 
assign qh = q[WID];
 
endmodule
/trunk/rtl/verilog/edge_det.v
0,0 → 1,60
/* ============================================================================
2007 Robert Finch
rob@birdcomputer.ca
 
edge_det.v
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
Notes:
 
Edge detector
This little core detects an edge (positive, negative, and
either) in the input signal.
 
Verilog 1995
Webpack 9.2 xc3S1000-4ft256
3 LUTs / 2 slices / 9.1ns
============================================================================ */
 
module edge_det(rst, clk, ce, i, pe, ne, ee);
input rst; // reset
input clk; // clock
input ce; // clock enable
input i; // input signal
output pe; // positive transition detected
output ne; // negative transition detected
output ee; // either edge (positive or negative) transition detected
 
reg ed;
always @(posedge clk)
if (rst)
ed <= 1'b0;
else if (ce)
ed <= i;
 
assign pe = ~ed & i; // positive: was low and is now high
assign ne = ed & ~i; // negative: was high and is now low
assign ee = ed ^ i; // either: signal is now opposite to what it was
endmodule
/trunk/rtl/verilog/FF_PS2kbd.v
0,0 → 1,420
// ============================================================================
// FF_PS2kbd.v - PS2 compatibla keyboard interface
//
// 2005.2010 Robert Finch
// robfinch<remove>@FPGAfield.ca
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// PS2 compatible keyboard / mouse interface
//
// This core provides a raw interface to the a PS2
// keyboard or mouse. The interface is raw in the sense
// that it doesn't do any scan code processing, it
// just supplies it to the system. The core uses a
// WISHBONE compatible bus interface.
// Both transmit and recieve are
// supported. It is possible to build the core without
// the transmitter to reduce the size of the core; however
// then it would not be possible to control the leds on
// the keyboard. (The transmitter is required for a mouse
// interface).
// There is a 5us debounce circuit on the incoming
// clock.
// The transmitter does not have a watchdog timer, so
// it may cause the keyboard to stop responding if there
// was a problem with the transmit. It relys on the system
// to reset the transmitter after 30ms or so of no
// reponse. Resetting the transmitter should allow the
// keyboard to respond again.
// Note: keyboard clock must be at least three times slower
// than the clk_i input to work reliably.
// A typical keyboard clock is <30kHz so this should be ok
// for most systems.
// * There must be pullup resistors on the keyboard clock
// and data lines, and the keyboard clock and data lines
// are assumed to be open collector.
// To read the keyboard, wait for bit 7 of the status
// register to be set, then read the transmit / recieve
// register. Reading the transmit / recieve register clears
// the keyboard reciever, and allows the next character to
// be recieved.
//
// Reg
// 0 keyboard transmit/receive register
// 1 status reg. itk xxxx p
// i = interrupt status
// t = transmit complete
// k = transmit acknowledge receipt (from keyboard)
// p = parity error
// A write to the status register clears the transmitter
// state
//
//
//
// Webpack 9.1i xc3s1000-4ft256
// LUTs / slices / MHz
// block rams
// multiplier
//
// ============================================================================
// A good source of info:
// http://panda.stb_i.ndsu.nodak.edu/~achapwes/PICmicro/PS2/ps2.htm
// http://www.beyondlogic.org/keyboard/keybrd.htm
//
// From the keyboard
// 1 start bit
// 8 data bits
// 1 parity bit
// 1 stop bit
//
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |WISHBONE Datasheet
// |WISHBONE SoC Architecture Specification, Revision B.3
// |
// |Description: Specifications:
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |General Description: PS2 keyboard / mouse interface
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Supported Cycles: SLAVE,READ/WRITE
// | SLAVE,BLOCK READ/WRITE
// | SLAVE,RMW
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Data port, size: 8 bit
// |Data port, granularity: 8 bit
// |Data port, maximum operand size: 8 bit
// |Data transfer ordering: Undefined
// |Data transfer sequencing: Undefined
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Clock frequency constraints: none
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Supported signal list and Signal Name WISHBONE equiv.
// |cross reference to equivalent ack_o ACK_O
// |WISHBONE signals adr_i ADR_I()
// | clk_i CLK_I
// | cyc_i CYC_I
// | dat_i(7:0) DAT_I()
// | dat_o(7:0) DAT_O()
// | stb_i STB_I
// | we_i WE_I
// |
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Special requirements:
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
// Note to self:
// 117LUTs / 66 slices / 95MHz
// 57LUTs / 32 slices / 107MHz - no transmitter
//==================================================================
 
`define KBD_TX // include transmitter
 
`define S_KBDRX_WAIT_CLK 0
`define S_KBDRX_CHK_CLK_LOW 1
`define S_KBDRX_CAPTURE_BIT 2
 
module FF_PS2kbd(
// WISHBONE/SoC bus interface
input rst_i,
input clk_i, // system clock
input cyc_i,
input stb_i, // core select (active high)
output ack_o, // bus transfer acknowledged
input we_i, // I/O write taking place (active high)
input [43:0] adr_i, // address
input [15:0] dat_i, // data in
output reg [15:0] dat_o, // data out
output vol_o, // volatile register selected
//-------------
output irq, // interrupt request (active high)
inout tri kclk, // keyboard clock from keyboard
inout tri kd // keyboard data
);
parameter pClkFreq = 28636360;
parameter p5us = pClkFreq / 200000; // number of clocks for 5us
parameter p100us = pClkFreq / 10000; // number of clocks for 100us
 
reg [11:0] os; // one shot
wire os_5us_done = os==p5us;
wire os_100us_done = os==p100us;
reg [10:0] q; // receive register
reg tc; // transmit complete indicator
reg [1:0] s_rx; // keyboard receive state
reg [1:0] kq;
reg [1:0] kqc;
wire kqcne; // negative edge on kqc
wire kqcpe; // positive edge on kqc
assign irq = ~q[0];
reg kack; // keyboard acknowledge bit
`ifdef KBD_TX
reg [16:0] tx_state; // transmitter states
reg klow; // force clock line low
reg [10:0] t; // transmit register
wire rx_inh = ~tc; // inhibit receive while transmit occuring
reg [3:0] bitcnt;
wire shift_done = bitcnt==0;
reg tx_oe; // transmitter output enable / shift enable
`else
wire rx_inh = 0;
`endif
 
wire cs = cyc_i && stb_i && (adr_i[43:8]==36'hFFF_FFDC_00);
assign vol_o = cs;
assign ack_o = cs;
 
// register read path
always @(adr_i or q or tc or kack or cs) begin
if (cs)
case(adr_i[1:0])
2'd0: dat_o <= q[8:1];
2'd2: dat_o <= {~q[0],tc,~kack,4'b0,~^q[9:1]};
default: dat_o <= 16'd0;
endcase
else
dat_o <= 16'h0000;
end
 
// Prohibit keyboard device from further transmits until
// this character has been processed.
// Holding the clock line low does this.
assign kclk = irq ? 1'b0 : 1'bz;
`ifdef KBD_TX
// Force clock and data low during transmits
assign kclk = klow ? 1'b0 : 1'bz;
assign kd = tx_oe & ~t[0] ? 1'b0 : 1'bz;
`endif
 
// stabilize clock and data
always @(posedge clk_i) begin
kq <= {kq[0],kd};
kqc <= {kqc[0],kclk};
end
 
edge_det ed0 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(kqc[1]), .pe(kqcpe), .ne(kqcne) );
 
 
// The debounce one-shot and 100us timer
always @(posedge clk_i)
if (rst_i)
os <= 0;
else begin
if ((s_rx==`S_KBDRX_WAIT_CLK && kqcne && ~rx_inh)||
(s_rx==`S_KBDRX_CHK_CLK_LOW && rx_inh)
`ifdef KBD_TX
||tx_state[0]||tx_state[2]||tx_state[5]||tx_state[7]||tx_state[9]||tx_state[11]||tx_state[14]
`endif
)
os <= 0;
else
os <= os + 1;
end
 
 
// Receive state machine
always @(posedge clk_i) begin
if (rst_i) begin
q <= 11'h7FF;
s_rx <= `S_KBDRX_WAIT_CLK;
end
else begin
 
// clear rx on read
if (ack_o & ~we_i & ~adr_i[0])
q <= 11'h7FF;
 
// Receive state machine
case (s_rx) // synopsys full_case parallel_case
// negedge on kclk ?
// then set debounce one-shot
`S_KBDRX_WAIT_CLK:
if (kqcne && ~rx_inh)
s_rx <= `S_KBDRX_CHK_CLK_LOW;
 
// wait 5us
// check if clock low
`S_KBDRX_CHK_CLK_LOW:
if (rx_inh)
s_rx <= `S_KBDRX_WAIT_CLK;
else if (os_5us_done) begin
// clock low ?
if (~kqc[1])
s_rx <= `S_KBDRX_CAPTURE_BIT;
else
s_rx <= `S_KBDRX_WAIT_CLK; // no - spurious
end
 
// capture keyboard bit
// keyboard transmits LSB first
`S_KBDRX_CAPTURE_BIT:
begin
q <= {kq,q[10:1]};
s_rx <= `S_KBDRX_WAIT_CLK;
end
 
default:
s_rx <= `S_KBDRX_WAIT_CLK;
endcase
end
end
 
 
`ifdef KBD_TX
 
// Transmit state machine
// a shift register / ring counter is used
reg adv_tx_state; // advance transmitter state
reg start_tx; // start the transmitter
reg clear_tx; // clear the transmit state
always @(posedge clk_i)
if (rst_i)
tx_state <= 0;
else begin
if (clear_tx)
tx_state <= 0;
else if (start_tx)
tx_state[0] <= 1;
else if (adv_tx_state) begin
tx_state[6:0] <= {tx_state[5:0],1'b0};
tx_state[7] <= (tx_state[8] && !shift_done) || tx_state[6];
tx_state[8] <= tx_state[7];
tx_state[9] <= tx_state[8] && shift_done;
tx_state[16:10] <= tx_state[15:9];
end
end
 
 
// detect when to advance the transmit state
always @(tx_state or kqcne or kqcpe or kqc or os_100us_done or os_5us_done)
case (1'b1) // synopsys parallel_case
tx_state[0]: adv_tx_state <= 1;
tx_state[1]: adv_tx_state <= os_100us_done;
tx_state[2]: adv_tx_state <= 1;
tx_state[3]: adv_tx_state <= os_5us_done;
tx_state[4]: adv_tx_state <= 1;
tx_state[5]: adv_tx_state <= kqcne;
tx_state[6]: adv_tx_state <= os_5us_done;
tx_state[7]: adv_tx_state <= kqcpe;
tx_state[8]: adv_tx_state <= os_5us_done;
tx_state[9]: adv_tx_state <= kqcpe;
tx_state[10]: adv_tx_state <= os_5us_done;
tx_state[11]: adv_tx_state <= kqcne;
tx_state[12]: adv_tx_state <= os_5us_done;
tx_state[13]: adv_tx_state <= 1;
tx_state[14]: adv_tx_state <= kqcpe;
tx_state[15]: adv_tx_state <= os_5us_done;
default: adv_tx_state <= 0;
endcase
 
wire load_tx = ack_o & we_i & ~adr_i[1];
wire shift_tx = (tx_state[7] & kqcpe)|tx_state[4];
 
// It can take up to 20ms for the keyboard to accept data
// from the host.
always @(posedge clk_i) begin
if (rst_i) begin
klow <= 0;
tc <= 1;
start_tx <= 0;
tx_oe <= 0;
end
else begin
 
clear_tx <= 0;
start_tx <= 0;
 
// write to keyboard register triggers whole thing
if (load_tx) begin
start_tx <= 1;
tc <= 0;
end
// write to status register clears transmit state
else if (ack_o & we_i & adr_i[1]) begin
tc <= 1;
tx_oe <= 0;
klow <= 1'b0;
clear_tx <= 1;
end
else begin
 
case (1'b1) // synopsys parallel_case
 
tx_state[0]: klow <= 1'b1; // First step: pull the clock low
tx_state[1]: ; // wait 100 us (hold clock low)
tx_state[2]: tx_oe <= 1; // bring data low / enable shift
tx_state[3]: ; // wait 5us
// at this point the clock should go high
// and shift out the start bit
tx_state[4]: klow <= 0; // release clock line
tx_state[5]: ; // wait for clock to go low
tx_state[6]: ; // wait 5us
// state7, 8 shift the data out
tx_state[7]: ; // wait for clock to go high
tx_state[8]: ; // wait 5us, go back to state 7
tx_state[9]: tx_oe <= 0; // wait for clock to go high // disable transmit output / shift
tx_state[10]: ; // wait 5us
tx_state[11]: ; // wait for clock to go low
tx_state[12]: ; // wait 5us
tx_state[13]: kack <= kq[1]; // capture the ack_o bit from the keyboard
tx_state[14]: ; // wait for clock to go high
tx_state[15]: ; // wait 5us
tx_state[16]:
begin
tc <= 1; // transmit is now complete
clear_tx <= 1;
end
 
default: ;
 
endcase
end
end
end
 
 
// transmitter shift register
always @(posedge clk_i)
if (rst_i)
t <= 11'd0;
else begin
if (load_tx)
t <= {~(^dat_i),dat_i,2'b0};
else if (shift_tx)
t <= {1'b1,t[10:1]};
end
 
 
// transmitter bit counter
always @(posedge clk_i)
if (rst_i)
bitcnt <= 4'd0;
else begin
if (load_tx)
bitcnt <= 4'd11;
else if (shift_tx)
bitcnt <= bitcnt - 4'd1;
end
 
`endif
 
endmodule
/trunk/rtl/verilog/rtfSimpleUart.v
0,0 → 1,410
/* ============================================================================
2007,2011 Robert Finch
robfinch@<remove>sympatico.ca
 
rtfSimpleUart.v
Basic uart with baud rate generator based on a harmonic
frequency synthesizer.
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
To use:
Set the pClkFreq parameter to the frequency of the system
clock (clk_i). This can be done when the core is instanced.
1) set the baud rate value in the clock multiplier
registers (CM1,2,3). A default multiplier value may
be specified using the pClkMul parameter, so it
doesn't have to be programmed at run time. (Note the
pBaud parameter may also be set, but it doesn't work
in all cases due to arithmetic limitations).
2) enable communication by activating the rts, and
dtr signals in the modem control register. These
signals are defaulted to be active on reset, so they
may not need to be set. The pRts and pDtr parameters
may be used to change the default setting.
3) use interrupts or poll the status register to
determine when to transmit or receive a byte of data
4) read / write the transmit / recieve data buffer
for communication.
 
Notes:
This core only supports a single transmission /
reception format: 1 start, 8 data, and 1 stop bit (no
parity).
The baud rate generator uses a 24 bit harmonic
frequency synthesizer. Compute the multiplier value
as if a 32 bit value was needed, then take the upper
24 bits of the value. (The number of significant bits
in the value determine the minimum frequency
resolution or the precision of the value).
 
baud rate * 16
value = -----------------------
(clock frequency / 2^32)
eg 38400 * 16
value = -----------------------
(28.63636MHz / 2^32)
= 92149557.65
= 057E1736 (hex)
taking the upper 24 bits
top 24 = 057E17
= 359959
so the value needed to be programmed into the register
for 38.4k baud is 57E17 (hex)
eg CM0 = 0 (not used)
CM1 = 17 hex
CM2 = 7E hex
CM3 = 05 hex
 
 
Register Description
 
reg
0 read / write (RW)
TRB - transmit / receive buffer
transmit / receive buffer
write - write to transmit buffer
read - read from receive buffer
 
1 read only (RO)
LS - line status register
bit 0 = receiver not empty, this bit is set if there is
any data available in the receiver fifo
bit 1 = overrun, this bit is set if receiver overrun occurs
bit 3 = framing error, this bit is set if there was a
framing error with the current byte in the receiver
buffer.
bit 5 = transmitter not full, this bit is set if the transmitter
can accept more data
bit 6 = transmitter empty, this bit is set if the transmitter is
completely empty
 
2 MS - modem status register (RO)
writing to the modem status register clears the change
indicators, which should clear a modem status interrupt
bit 3 = change on dcd signal
bit 4 = cts signal level
bit 5 = dsr signal level
bit 6 = ri signal level
bit 7 = dcd signal level
 
3 IS - interrupt status register (RO)
bit 0-4 = mailbox number
bit 0,1 = 00
bit 2-4 = encoded interrupt value
bit 5-6 = not used, reserved
bit 7 = 1 = interrupt pending, 0 = no interrupt
 
4 IE - interrupt enable register (RW)
bit 0 = receive interrupt (data present)
bit 1 = transmit interrupt (data empty)
bit 3 = modem status (dcd) register change
bit 5-7 = unused, reserved
 
5 FF - frame format register (RW)
this register doesn't do anything in the simpleUart
but is reserved for compatiblity with the more
advanced uart
 
6 MC - modem control register (RW)
bit 0 = dtr signal level output
bit 1 = rts signal level output
 
7 - control register
bit 0 = hardware flow control,
when this bit is set, the transmitter output is
controlled by the cts signal line automatically
 
 
* Clock multiplier steps the 16xbaud clock frequency
in increments of 1/2^32 of the clk_i input using a
harmonic frequency synthesizer
eg. to get a 9600 baud 16x clock (153.6 kHz) with a
27.175 MHz clock input,
value = upper24(9600 * 16 / (27.175MHz / 2^32))
Higher frequency baud rates will exhibit more jitter
on the 16x clock, but this will mostly be masked by the
16x clock factor.
 
8 CM0 - Clock Multiplier byte 0 (RW)
this is the least significant byte
of the clock multiplier value
this register is not used unless the clock
multiplier is set to contain 32 bit values
 
9 CM1 - Clock Multiplier byte 1 (RW)
this is the third most significant byte
of the clock multiplier value
this register is not used unless the clock
multiplier is set to contain 24 or 32 bit values
 
10 CM2 - Clock Multiplier byte 2 (RW)
this is the second most significant byte of the clock
multiplier value
 
11 CM3 - Clock Multiplier byte 3 (RW)
this is the most significant byte of the multiplier value
 
12 FC - Fifo control register (RW)
this register doesnt' do anything in the simpleUart
but is reserved for compatibility with the more
advanced uart
13-14 reserved registers
 
15 SPR - scratch pad register (RW)
 
 
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|WISHBONE Datasheet
|WISHBONE SoC Architecture Specification, Revision B.3
|
|Description: Specifications:
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|General Description: simple UART core
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Supported Cycles: SLAVE,READ/WRITE
| SLAVE,BLOCK READ/WRITE
| SLAVE,RMW
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Data port, size: 8 bit
|Data port, granularity: 8 bit
|Data port, maximum operand size: 8 bit
|Data transfer ordering: Undefined
|Data transfer sequencing: Undefined
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Clock frequency constraints: none
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Supported signal list and Signal Name WISHBONE equiv.
|cross reference to equivalent ack_o ACK_O
|WISHBONE signals adr_i[3:0] ADR_I()
| clk_i CLK_I
| rst_i RST_I()
| dat_i(7:0) DAT_I()
| dat_o(7:0) DAT_O()
| cyc_i CYC_I
| stb_i STB_I
| we_i WE_I
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Special requirements:
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
 
Ref. Spartan3 -4
117 LUTs / 87 slices / 133 MHz
============================================================================ */
 
`define UART_TRB 4'd0 // transmit/receive buffer
`define UART_LS 4'd1 // line status register
`define UART_MS 4'd2 // modem status register
`define UART_IS 4'd3 // interrupt status register
`define UART_IER 4'd4 // interrupt enable
`define UART_FF 4'd5 // frame format register
`define UART_MC 4'd6 // modem control register
`define UART_CTRL 4'd7 // control register
`define UART_CLKM0 4'd8 // clock multiplier byte 0
`define UART_CLKM1 4'd9 // clock multiplier byte 1
`define UART_CLKM2 4'd10 // clock multiplier byte 2
`define UART_CLKM3 4'd11 // clock multiplier byte 3
`define UART_FC 4'd12 // fifo control register
 
module rtfSimpleUart(
// WISHBONE Slave interface
input rst_i, // reset
input clk_i, // eg 100.7MHz
input cyc_i, // cycle valid
input stb_i, // strobe
input we_i, // 1 = write
input [31:0] adr_i, // register address
input [7:0] dat_i, // data input bus
output reg [7:0] dat_o, // data output bus
output ack_o, // transfer acknowledge
output vol_o, // volatile register selected
output irq_o, // interrupt request
//----------------
input cts_ni, // clear to send - active low - (flow control)
output reg rts_no, // request to send - active low - (flow control)
input dsr_ni, // data set ready - active low
input dcd_ni, // data carrier detect - active low
output reg dtr_no, // data terminal ready - active low
input rxd_i, // serial data in
output txd_o, // serial data out
output data_present_o
);
parameter pClkFreq = 20000000; // clock frequency in MHz
parameter pBaud = 19200;
parameter pClkMul = (4096 * pBaud) / (pClkFreq / 65536);
parameter pRts = 1; // default to active
parameter pDtr = 1;
 
wire cs = cyc_i && stb_i && (adr_i[31:4]==28'hFFDC_0A0);
assign ack_o = cs;
assign vol_o = cs && adr_i[3:2]==2'b00;
 
//-------------------------------------------
// variables
reg [23:0] c; // current count
reg [23:0] ck_mul; // baud rate clock multiplier
wire tx_empty;
wire baud16; // edge detector (active one cycle only!)
reg rx_present_ie;
reg tx_empty_ie;
reg dcd_ie;
reg hwfc; // hardware flow control enable
wire clear = cyc_i && stb_i && we_i && adr_i==4'd13;
wire frame_err; // receiver char framing error
wire over_run; // receiver over run
reg [1:0] ctsx; // cts_ni sampling
reg [1:0] dcdx;
reg [1:0] dsrx;
wire dcd_chg = dcdx[1]^dcdx[0];
 
 
wire rxIRQ = data_present_o & rx_present_ie;
wire txIRQ = tx_empty & tx_empty_ie;
wire msIRQ = dcd_chg & dcd_ie;
 
assign irq_o =
rxIRQ
| txIRQ
| msIRQ
;
 
wire [2:0] irqenc =
rxIRQ ? 1 :
txIRQ ? 3 :
msIRQ ? 4 :
0;
 
wire [7:0] rx_do;
wire txrx = cs && adr_i[3:0]==4'd0;
 
rtfSimpleUartRx uart_rx0(
.rst_i(rst_i),
.clk_i(clk_i),
.cyc_i(cyc_i),
.stb_i(stb_i),
.cs_i(txrx),
.we_i(we_i),
.dat_o(rx_do),
.baud16x_ce(baud16),
.clear(clear),
.rxd(rxd_i),
.data_present(data_present_o),
.frame_err(frame_err),
.overrun(over_run)
);
 
rtfSimpleUartTx uart_tx0(
.rst_i(rst_i),
.clk_i(clk_i),
.cyc_i(cyc_i),
.stb_i(stb_i),
.cs_i(txrx),
.we_i(we_i),
.dat_i(dat_i),
.baud16x_ce(baud16),
.cts(ctsx[1]|~hwfc),
.txd(txd_o),
.empty(tx_empty)
);
 
// mux the reg outputs
always @*
if (cs) begin
case(adr_i[3:0]) // synopsys full_case parallel_case
`UART_MS: dat_o <= {dcdx[1],1'b0,dsrx[1],ctsx[1],dcd_chg,3'b0};
`UART_IS: dat_o <= {irq_o, 2'b0, irqenc, 2'b0};
`UART_LS: dat_o <= {1'b0, tx_empty, tx_empty, 1'b0, frame_err, 1'b0, over_run, data_present_o};
default: dat_o <= rx_do;
endcase
end
else
dat_o <= 8'b0;
 
// Note: baud clock should pulse high for only a single
// cycle!
always @(posedge clk_i)
if (rst_i)
c <= 0;
else
c <= c + ck_mul;
 
// for detecting an edge on the msb
edge_det ed0(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(c[23]), .pe(baud16), .ne(), .ee() );
 
// register updates
always @(posedge clk_i) begin
if (rst_i) begin
rts_no <= ~pRts;
rx_present_ie <= 1'b0;
tx_empty_ie <= 1'b0;
dcd_ie <= 1'b0;
hwfc <= 1'b1;
dtr_no <= ~pDtr;
ck_mul <= pClkMul;
end
else if (cs & we_i) begin
case (adr_i)
`UART_IER:
begin
rx_present_ie <= dat_i[0];
tx_empty_ie <= dat_i[1];
dcd_ie <= dat_i[3];
end
`UART_MC:
begin
dtr_no <= ~dat_i[0];
rts_no <= ~dat_i[1];
end
`UART_CTRL: hwfc <= dat_i[0];
`UART_CLKM1: ck_mul[7:0] <= dat_i;
`UART_CLKM2: ck_mul[15:8] <= dat_i;
`UART_CLKM3: ck_mul[23:16] <= dat_i;
default:
;
endcase
end
end
 
 
// synchronize external signals
always @(posedge clk_i)
ctsx <= {ctsx[0],~cts_ni};
 
always @(posedge clk_i)
dcdx <= {dcdx[0],~dcd_ni};
 
always @(posedge clk_i)
dsrx <= {dsrx[0],~dsr_ni};
 
endmodule
 
/trunk/rtl/verilog/PSGOutputSummer.v
0,0 → 1,44
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
rob@birdcomputer.ca
 
bcPSGOutputSummer.v
Sum the filtered and unfiltered output.
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
============================================================================ */
 
module PSGOutputSummer(clk_i, cnt, ufi, fi, o);
input clk_i; // master clock
input [7:0] cnt; // clock divider
input [21:0] ufi; // unfiltered audio input
input [21:0] fi; // filtered audio input
output [21:0] o; // summed output
reg [21:0] o;
 
always @(posedge clk_i)
if (cnt==8'd0)
o <= ufi + fi;
 
endmodule
/trunk/rtl/verilog/rtfColorROM.v
0,0 → 1,110
// ============================================================================
// 2006-2011 Robert Finch
// robfinch@<remove>sympatico.ca
//
// rtfColorROM.v
// Color lookup ROM for TextController.
// Converts a 5-bit color code to a 24 bit RGB value.
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
 
 
// TC64 color codes
`define TC64_BLACK 5'd0
`define TC64_WHITE 5'd1
`define TC64_RED 5'd2
`define TC64_CYAN 5'd3
`define TC64_PURPLE 5'd4
`define TC64_GREEN 5'd5
`define TC64_BLUE 5'd6
`define TC64_YELLOW 5'd7
`define TC64_ORANGE 5'd8
`define TC64_BROWN 5'd9
`define TC64_PINK 5'd10
`define TC64_DARK_GREY 5'd11
`define TC64_MEDIUM_GREY 5'd12
`define TC64_LIGHT_GREEN 5'd13
`define TC64_LIGHT_BLUE 5'd14
`define TC64_LIGHT_GREY 5'd15
 
`define TC64_BLACKa 5'd16
`define TC64_WHITEa 5'd17
`define TC64_REDa 5'd18
`define TC64_CYANa 5'd19
`define TC64_PURPLEa 5'd20
`define TC64_GREENa 5'd21
`define TC64_BLUEa 5'd22
`define TC64_YELLOWa 5'd23
`define TC64_ORANGEa 5'd24
`define TC64_BROWNa 5'd25
`define TC64_PINKa 5'd26
`define TC64_DARK_GREYa 5'd27
`define TC64_GREY3 5'd28
`define TC64_LIGHT_GREENa 5'd29
`define TC64_LIGHT_BLUEa 5'd30
`define TC64_GREY5 5'd31
 
module rtfColorROM(clk, ce, code, color);
input clk;
input ce;
input [4:0] code;
output [23:0] color;
reg [23:0] color;
 
always @(posedge clk)
if (ce) begin
case (code)
`TC64_BLACK: color = 24'h10_10_10;
`TC64_WHITE: color = 24'hFF_FF_FF;
`TC64_RED: color = 24'hE0_40_40;
`TC64_CYAN: color = 24'h60_FF_FF;
`TC64_PURPLE: color = 24'hE0_60_E0;
`TC64_GREEN: color = 24'h40_E0_40;
`TC64_BLUE: color = 24'h40_40_E0;
`TC64_YELLOW: color = 24'hFF_FF_40;
`TC64_ORANGE: color = 24'hE0_A0_40;
`TC64_BROWN: color = 24'h9C_74_48;
`TC64_PINK: color = 24'hFF_A0_A0;
`TC64_DARK_GREY: color = 24'h54_54_54;
`TC64_MEDIUM_GREY: color = 24'h88_88_88;
`TC64_LIGHT_GREEN: color = 24'hA0_FF_A0;
`TC64_LIGHT_BLUE: color = 24'hA0_A0_FF;
`TC64_LIGHT_GREY: color = 24'hC0_C0_C0;
 
`TC64_BLACKa: color = 24'h10_10_10;
`TC64_WHITEa: color = 24'hFF_FF_FF;
`TC64_REDa: color = 24'hE0_40_40;
`TC64_CYANa: color = 24'h60_FF_FF;
`TC64_PURPLEa: color = 24'hE0_60_E0;
`TC64_GREENa: color = 24'h40_E0_40;
`TC64_BLUEa: color = 24'h40_40_E0;
`TC64_YELLOWa: color = 24'hFF_FF_40;
`TC64_ORANGEa: color = 24'hE0_A0_40;
`TC64_BROWNa: color = 24'h9C_74_48;
`TC64_PINKa: color = 24'hFF_A0_A0;
`TC64_DARK_GREYa: color = 24'h54_54_54;
`TC64_GREY3: color = 24'h30_30_30;
`TC64_LIGHT_GREENa: color = 24'hA0_FF_A0;
`TC64_LIGHT_BLUEa: color = 24'hA0_A0_FF;
`TC64_GREY5: color = 24'h50_50_50;
 
endcase
end
 
endmodule
 
 
/trunk/rtl/verilog/busTimeoutCtr.v
0,0 → 1,94
/* ===============================================================
(C) 2005 Robert Finch
All rights reserved.
rob@birdcomputer.ca
 
busTimeoutCtr.v
Generates a timeout signal if the bus hasn't responded
within a preset period.
 
 
This source code is free for use and modification for
non-commercial or evaluation purposes, provided this
copyright statement and disclaimer remains present in
the file.
 
If you do modify the code, please state the origin and
note that you have modified the code.
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
the entire risk of using the Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
USE.
 
 
The default reset state is to request the bus.
This little circuit asserts the br line to an external
bus when req pulses high (for a clock cycle or more) and
removes the br signal if there is no pending req, once a
bg has been given.
br goes high as soon as req goes high, but then remains
high even if req is removed.
br goes low as soon as bg goes high UNLESS there is also
a req present, in which case it stays high.
 
br = the signal to the external bus that a request is
present
bg = the signal from the external bus that the bus has
been granted
req = signal provided by the master to indicate that it
needs the bus. The master should monitor the bg
signal to know when it has control of the bus.
rdy = input indicating that the bus transaction is
complete
timeout = flag indicating that the request has timed out.
Pulses high for one cycle.
 
9LUTs / 8 slices
=============================================================== */
 
module busTimeoutCtr(
input rst, // reset
input crst, // critical reset
input clk, // system clock
input ce, // core clock enable
input req, // request bus
input rdy, // data ready input
output timeout // timeout
);
parameter pTimeout = 20; // max 61
 
reg [5:0] btc; // bus timeout counter
 
always @(posedge clk)
if (rst)
btc <= 0;
else if (ce) begin
if (req)
btc <= pTimeout+2;
else if (rdy)
btc <= 0;
else if (btc > 0)
btc <= btc - 1;
end
 
assign timeout = btc==6'd1;
 
endmodule
 
 
/trunk/rtl/verilog/PSGChannelSummer.v
0,0 → 1,51
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
rob@birdcomputer.ca
 
PSGChannelSummer.v
Sums the channel outputs.
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
Spartan3
1255 LUTs / 975 slices / 56MHz
============================================================================ */
 
module PSGChannelSummer(clk_i, cnt, outctrl, tmc_i, o);
input clk_i; // master clock
input [7:0] cnt; // select counter
input [3:0] outctrl; // channel output enable control
input [19:0] tmc_i; // time-multiplexed channel input
output [21:0] o; // summed output
reg [21:0] o;
 
// channel select signal
wire [1:0] sel = cnt[1:0];
 
always @(posedge clk_i)
if (cnt==8'd0)
o <= 22'd0 + (tmc_i & {20{outctrl[sel]}});
else if (cnt < 8'd4)
o <= o + (tmc_i & {20{outctrl[sel]}});
 
endmodule
/trunk/rtl/verilog/rtfSimpleUartRx.v
0,0 → 1,201
/* ============================================================================
2011 Robert Finch
robfinch@<remove>sympatico.ca
 
rtfSimpleUartRx.v
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
Simple UART receiver core
Features:
false start bit detection
framing error detection
overrun state detection
resynchronization on every character
fixed format 1 start - 8 data - 1 stop bits
uses 16x clock rate
This core may be used as a standalone peripheral
on a SoC bus if all that is desired is recieve
capability. It requires a 16x baud rate clock.
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|WISHBONE Datasheet
|WISHBONE SoC Architecture Specification, Revision B.3
|
|Description: Specifications:
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|General Description: simple serial UART receiver
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Supported Cycles: SLAVE,READ
| SLAVE,BLOCK READ
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Data port, size: 8 bit
|Data port, granularity: 8 bit
|Data port, maximum operand size: 8 bit
|Data transfer ordering: Undefined
|Data transfer sequencing: Undefined
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Clock frequency constraints: none
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Supported signal list and Signal Name WISHBONE equiv.
|cross reference to equivalent ack_o ACK_O
|WISHBONE signals
| clk_i CLK_I
| rst_i RST_I
| dat_o(7:0) DAT_O()
| cyc_i CYC_I
| stb_i STB_I
| we_i WE_I
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Special requirements:
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
Ref: Spartan3 -4
27 LUTs / 24 slices / 170 MHz
============================================================================ */
 
`define IDLE 0
`define CNT 1
 
module rtfSimpleUartRx(
// WISHBONE SoC bus interface
input rst_i, // reset
input clk_i, // clock
input cyc_i, // cycle is valid
input stb_i, // strobe
output ack_o, // data is ready
input we_i, // write (this signal is used to qualify reads)
output [7:0] dat_o, // data out
//------------------------
input cs_i, // chip select
input baud16x_ce, // baud rate clock enable
input clear, // clear reciever
input rxd, // external serial input
output reg data_present, // data present in fifo
output reg frame_err, // framing error
output reg overrun // receiver overrun
);
 
// variables
reg [3:0] rxdd; // synchronizer flops
reg [7:0] cnt; // sample bit rate counter
reg [9:0] rx_data; // working receive data register
reg state; // state machine
reg wf; // buffer write
reg [7:0] dat;
 
assign ack_o = cyc_i & stb_i & cs_i;
assign dat_o = ack_o ? dat : 8'b0;
 
// update data register
always @(posedge clk_i)
if (wf) dat <= rx_data[8:1];
 
// on a read clear the data present status
// but set the status when the data register
// is updated by the receiver
always @(posedge clk_i)
if (wf) data_present <= 1;
else if (ack_o & ~we_i) data_present <= 0;
 
 
// Three stage synchronizer to synchronize incoming data to
// the local clock (avoids metastability).
always @(posedge clk_i)
rxdd <= {rxdd[2:0],rxd};
 
always @(posedge clk_i) begin
if (rst_i) begin
state <= `IDLE;
wf <= 1'b0;
overrun <= 1'b0;
end
else begin
 
// Clear write flag
wf <= 1'b0;
 
if (clear) begin
wf <= 1'b0;
state <= `IDLE;
overrun <= 1'b0;
end
 
else if (baud16x_ce) begin
 
case (state)
 
// Sit in the idle state until a start bit is
// detected.
`IDLE:
// look for start bit
if (~rxdd[3])
state <= `CNT;
 
`CNT:
begin
// End of the frame ?
// - check for framing error
// - write data to read buffer
if (cnt==8'h97)
begin
frame_err <= ~rxdd[3];
if (!data_present)
wf <= 1'b1;
else
overrun <= 1'b1;
end
// Switch back to the idle state a little
// bit too soon.
if (cnt==8'h9D)
state <= `IDLE;
 
// On start bit check make sure the start
// bit is low, otherwise go back to the
// idle state because it's a false start.
if (cnt==8'h07 && rxdd[3])
state <= `IDLE;
 
if (cnt[3:0]==4'h7)
rx_data <= {rxdd[3],rx_data[9:1]};
end
 
endcase
end
end
end
 
 
// bit rate counter
always @(posedge clk_i)
if (baud16x_ce) begin
if (state == `IDLE)
cnt <= 0;
else
cnt <= cnt + 1;
end
 
endmodule
 
/trunk/rtl/verilog/FF_PS2KbdToAscii.v
0,0 → 1,188
// ============================================================================
// Keyboard
// - Reads keys from PS2 style keyboard
//
// 2010-2011 Robert Finch
// robfinch<remove>@FPGAfield.ca
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// Convert a PS2 keyboard to ascii
//
// Reg
// $00 ascii code - bit 15 = strobe
// $01 access this address clears keyboard strobe
//
//
// Verilog 1995
// Webpack 9.2i xc3s1200-4fg320
// 64 slices / 118 LUTs / 175.009 MHz
// 72 ff's / 2 BRAM (2048x16)
//
// ============================================================================
 
// PS2 scan codes
`define SC_LSHIFT 8'h12
`define SC_RSHIFT 8'h59
`define SC_CTRL 8'h14
`define SC_ALT 8'h11
`define SC_DEL 8'h71 // extend
`define SC_LCTRL 8'h58
`define SC_EXTEND 8'hE0
`define SC_KEYUP 8'hF0
 
module FF_PS2KbdToAscii(rst_i, clk_i, cyc_i, stb_i, ack_o, adr_i, dat_o, kclk, kd, irq, rst_o);
input rst_i; // reset
input clk_i; // master clock
input cyc_i;
input stb_i;
output ack_o; // ready
input [43:0] adr_i; // address
output [15:0] dat_o; // data output
inout kclk; // keyboard clock from keyboard
tri kclk;
inout kd; // keyboard data
tri kd;
output irq; // data available
output rst_o; // reset output CTRL-ALT-DEL was pressed
 
wire cs = cyc_i && stb_i && (adr_i[43:4]==40'hFFF_FFDC_000);
 
reg strobe;
wire ps2_irq;
reg ps2_irq1;
reg ps2_cs;
wire [15:0] ps2_o;
 
// keyboard state
reg keyup;
reg extend; // extended keycode active
reg shift; // shift status
reg ctrl; // control status
reg alt; // alt status
reg x;
 
reg [7:0] sc;
 
assign ack_o = cs;
 
wire ign;
wire [7:0] xlat_o;
PS2ScanToAscii u1
(
.shift(shift),
.ctrl(ctrl),
.alt(1'b0),
.sc(sc),
.extend(x),
.ascii(xlat_o)
);
assign irq = strobe;
assign dat_o = cs ? {strobe,7'b0,xlat_o} : 16'h0000;
 
 
FF_PS2kbd u2
(
.rst_i(rst_i),
.clk_i(clk_i),
.cyc_i(ps2_cs),
.stb_i(ps2_cs),
.ack_o(),
.we_i(1'b0),
.adr_i(44'hFFF_FFDC_0000),
.dat_i(16'h0000),
.dat_o(ps2_o),
.vol_o(),
.irq(ps2_irq),
.kclk(kclk),
.kd(kd)
);
 
 
// This little machine takes care of issuing a read cycle to the ps2 keyboard
// when data is present.
always @(posedge clk_i)
if (rst_i) begin
ps2_cs <= 0;
ps2_irq1 <= 0;
end
else begin
// has an PS2 keyboard event happened ?
// If so, read the ps2 port
ps2_irq1 <= ps2_irq;
if (ps2_irq & ~ps2_irq1)
ps2_cs <= 1;
else
ps2_cs <= 0;
end
 
 
// This machine
// 1) clears the strobe line on an access to the keyboard strobe clear address
// 2) activates the strobe on a keydown event, filtering out special keys
// like control and alt
// 3) captures the state of ctrl,alt and shift and filters these codes out
always @(posedge clk_i)
if (rst_i) begin
keyup <= 0;
extend <= 0;
shift <= 0;
ctrl <= 0;
alt <= 0;
sc <= 0;
x <= 1'b0;
strobe <= 0;
end
else begin
if (cs & adr_i[1])
strobe <= 0;
if (ps2_cs) begin
case (ps2_o[7:0])
`SC_KEYUP: keyup <= 1;
`SC_EXTEND: extend <= 1;
default:
begin
case(ps2_o[7:0])
`SC_CTRL: ctrl <= ~keyup;
`SC_ALT: alt <= ~keyup;
`SC_LSHIFT,
`SC_RSHIFT: shift <= ~keyup;
default:
begin
sc <= ps2_o;
x <= extend;
strobe <= keyup ? strobe : 1;
end
endcase
keyup <= 0;
extend <= 0;
end
endcase
end
end
 
// CTRL-ALT-DEL
assign rst_o = ps2_o[7:0]==`SC_DEL && alt && ctrl;
 
endmodule
/trunk/rtl/verilog/VeriwordColors.vwb
0,0 → 1,1627
Begin Object VWColorMap
Definition:
Dim FileExtensions(20) As String
Dim color(20,80) As COLORREF
Data:
FileExtensions(0)="V"
FileExtensions(1)="VHDL"
FileExtensions(2)="C CPP H"
FileExtensions(3)="VB"
FileExtensions(4)="V"
FileExtensions(5)="V"
FileExtensions(6)="V"
FileExtensions(7)="V"
FileExtensions(8)="V"
FileExtensions(9)="V"
FileExtensions(10)="V"
FileExtensions(11)="V"
FileExtensions(12)="V"
FileExtensions(13)="V"
FileExtensions(14)="V"
FileExtensions(15)="V"
FileExtensions(16)="V"
FileExtensions(17)="V"
FileExtensions(18)="V"
FileExtensions(19)="V"
 
color(0,0)=#ffffff
color(0,1)=#ffffff
color(0,2)=#000000
color(0,3)=#c8c8c8
color(0,4)=#000000
color(0,5)=#ffffff
color(0,6)=#c00000
color(0,7)=#008000
color(0,8)=#000000
color(0,9)=#000000
color(0,10)=#0000ff
color(0,11)=#c08000
color(0,12)=#0000ff
color(0,13)=#0000ff
color(0,14)=#0000ff
color(0,15)=#0000ff
color(0,16)=#0000ff
color(0,17)=#0000ff
color(0,18)=#0000ff
color(0,19)=#208020
color(0,20)=#8040c0
color(0,21)=#0000ff
color(0,22)=#0000ff
color(0,23)=#0000ff
color(0,24)=#0000ff
color(0,25)=#0000ff
color(0,26)=#0000ff
color(0,27)=#0000ff
color(0,28)=#0000ff
color(0,29)=#0000ff
color(0,30)=#0000ff
color(0,31)=#0000ff
color(0,32)=#0000ff
color(0,33)=#0000ff
color(0,34)=#0000ff
color(0,35)=#0000ff
color(0,36)=#0000ff
color(0,37)=#0000ff
color(0,38)=#0000ff
color(0,39)=#0000ff
color(0,40)=#0000ff
color(0,41)=#0000ff
color(0,42)=#0000ff
color(0,43)=#0000ff
color(0,44)=#0000ff
color(0,45)=#0000ff
color(0,46)=#0000ff
color(0,47)=#0000ff
color(0,48)=#0000ff
color(0,49)=#0000ff
color(0,50)=#0000ff
color(0,51)=#0000ff
color(0,52)=#0000ff
color(0,53)=#0000ff
color(0,54)=#0000ff
color(0,55)=#0000ff
color(0,56)=#0000ff
color(0,57)=#0000ff
color(0,58)=#0000ff
color(0,59)=#0000ff
color(0,60)=#0000ff
color(0,61)=#0000ff
color(0,62)=#0000ff
color(0,63)=#0000ff
color(0,64)=#0000ff
color(0,65)=#0000ff
color(0,66)=#0000ff
color(0,67)=#0000ff
color(0,68)=#0000ff
color(0,69)=#0000ff
color(0,70)=#0000ff
color(0,71)=#0000ff
color(0,72)=#0000ff
color(0,73)=#0000ff
color(0,74)=#0000ff
color(0,75)=#0000ff
color(0,76)=#0000ff
color(0,77)=#0000ff
color(0,78)=#0000ff
color(0,79)=#0000ff
color(1,0)=#ffffff
color(1,1)=#ffffff
color(1,2)=#000000
color(1,3)=#c8c8c8
color(1,4)=#000000
color(1,5)=#ffffff
color(1,6)=#c00000
color(1,7)=#008000
color(1,8)=#000000
color(1,9)=#000000
color(1,10)=#0000ff
color(1,11)=#c08000
color(1,12)=#0000ff
color(1,13)=#0000ff
color(1,14)=#0000ff
color(1,15)=#0000ff
color(1,16)=#0000ff
color(1,17)=#0000ff
color(1,18)=#0000ff
color(1,19)=#208020
color(1,20)=#8040c0
color(1,21)=#0000ff
color(1,22)=#0000ff
color(1,23)=#0000ff
color(1,24)=#0000ff
color(1,25)=#0000ff
color(1,26)=#0000ff
color(1,27)=#0000ff
color(1,28)=#0000ff
color(1,29)=#0000ff
color(1,30)=#0000ff
color(1,31)=#0000ff
color(1,32)=#0000ff
color(1,33)=#0000ff
color(1,34)=#0000ff
color(1,35)=#0000ff
color(1,36)=#0000ff
color(1,37)=#0000ff
color(1,38)=#0000ff
color(1,39)=#0000ff
color(1,40)=#0000ff
color(1,41)=#0000ff
color(1,42)=#0000ff
color(1,43)=#0000ff
color(1,44)=#0000ff
color(1,45)=#0000ff
color(1,46)=#0000ff
color(1,47)=#0000ff
color(1,48)=#0000ff
color(1,49)=#0000ff
color(1,50)=#0000ff
color(1,51)=#0000ff
color(1,52)=#0000ff
color(1,53)=#0000ff
color(1,54)=#0000ff
color(1,55)=#0000ff
color(1,56)=#0000ff
color(1,57)=#0000ff
color(1,58)=#0000ff
color(1,59)=#0000ff
color(1,60)=#0000ff
color(1,61)=#0000ff
color(1,62)=#0000ff
color(1,63)=#0000ff
color(1,64)=#0000ff
color(1,65)=#0000ff
color(1,66)=#0000ff
color(1,67)=#0000ff
color(1,68)=#0000ff
color(1,69)=#0000ff
color(1,70)=#0000ff
color(1,71)=#0000ff
color(1,72)=#0000ff
color(1,73)=#0000ff
color(1,74)=#0000ff
color(1,75)=#0000ff
color(1,76)=#0000ff
color(1,77)=#0000ff
color(1,78)=#0000ff
color(1,79)=#0000ff
color(2,0)=#ffffff
color(2,1)=#ffffff
color(2,2)=#000000
color(2,3)=#c8c8c8
color(2,4)=#000000
color(2,5)=#ffffff
color(2,6)=#c00000
color(2,7)=#008000
color(2,8)=#000000
color(2,9)=#000000
color(2,10)=#0000ff
color(2,11)=#c08000
color(2,12)=#0000ff
color(2,13)=#0000ff
color(2,14)=#0000ff
color(2,15)=#0000ff
color(2,16)=#0000ff
color(2,17)=#0000ff
color(2,18)=#0000ff
color(2,19)=#208020
color(2,20)=#8040c0
color(2,21)=#0000ff
color(2,22)=#0000ff
color(2,23)=#0000ff
color(2,24)=#0000ff
color(2,25)=#0000ff
color(2,26)=#0000ff
color(2,27)=#0000ff
color(2,28)=#0000ff
color(2,29)=#0000ff
color(2,30)=#0000ff
color(2,31)=#0000ff
color(2,32)=#0000ff
color(2,33)=#0000ff
color(2,34)=#0000ff
color(2,35)=#0000ff
color(2,36)=#0000ff
color(2,37)=#0000ff
color(2,38)=#0000ff
color(2,39)=#0000ff
color(2,40)=#0000ff
color(2,41)=#0000ff
color(2,42)=#0000ff
color(2,43)=#0000ff
color(2,44)=#0000ff
color(2,45)=#0000ff
color(2,46)=#0000ff
color(2,47)=#0000ff
color(2,48)=#0000ff
color(2,49)=#0000ff
color(2,50)=#0000ff
color(2,51)=#0000ff
color(2,52)=#0000ff
color(2,53)=#0000ff
color(2,54)=#0000ff
color(2,55)=#0000ff
color(2,56)=#0000ff
color(2,57)=#0000ff
color(2,58)=#0000ff
color(2,59)=#0000ff
color(2,60)=#0000ff
color(2,61)=#0000ff
color(2,62)=#0000ff
color(2,63)=#0000ff
color(2,64)=#0000ff
color(2,65)=#0000ff
color(2,66)=#0000ff
color(2,67)=#0000ff
color(2,68)=#0000ff
color(2,69)=#0000ff
color(2,70)=#0000ff
color(2,71)=#0000ff
color(2,72)=#0000ff
color(2,73)=#0000ff
color(2,74)=#0000ff
color(2,75)=#0000ff
color(2,76)=#0000ff
color(2,77)=#0000ff
color(2,78)=#0000ff
color(2,79)=#0000ff
color(3,0)=#ffffff
color(3,1)=#ffffff
color(3,2)=#000000
color(3,3)=#c8c8c8
color(3,4)=#000000
color(3,5)=#ffffff
color(3,6)=#c00000
color(3,7)=#008000
color(3,8)=#000000
color(3,9)=#000000
color(3,10)=#0000ff
color(3,11)=#c08000
color(3,12)=#0000ff
color(3,13)=#0000ff
color(3,14)=#0000ff
color(3,15)=#0000ff
color(3,16)=#0000ff
color(3,17)=#0000ff
color(3,18)=#0000ff
color(3,19)=#208020
color(3,20)=#8040c0
color(3,21)=#0000ff
color(3,22)=#0000ff
color(3,23)=#0000ff
color(3,24)=#0000ff
color(3,25)=#0000ff
color(3,26)=#0000ff
color(3,27)=#0000ff
color(3,28)=#0000ff
color(3,29)=#0000ff
color(3,30)=#0000ff
color(3,31)=#0000ff
color(3,32)=#0000ff
color(3,33)=#0000ff
color(3,34)=#0000ff
color(3,35)=#0000ff
color(3,36)=#0000ff
color(3,37)=#0000ff
color(3,38)=#0000ff
color(3,39)=#0000ff
color(3,40)=#0000ff
color(3,41)=#0000ff
color(3,42)=#0000ff
color(3,43)=#0000ff
color(3,44)=#0000ff
color(3,45)=#0000ff
color(3,46)=#0000ff
color(3,47)=#0000ff
color(3,48)=#0000ff
color(3,49)=#0000ff
color(3,50)=#0000ff
color(3,51)=#0000ff
color(3,52)=#0000ff
color(3,53)=#0000ff
color(3,54)=#0000ff
color(3,55)=#0000ff
color(3,56)=#0000ff
color(3,57)=#0000ff
color(3,58)=#0000ff
color(3,59)=#0000ff
color(3,60)=#0000ff
color(3,61)=#0000ff
color(3,62)=#0000ff
color(3,63)=#0000ff
color(3,64)=#0000ff
color(3,65)=#0000ff
color(3,66)=#0000ff
color(3,67)=#0000ff
color(3,68)=#0000ff
color(3,69)=#0000ff
color(3,70)=#0000ff
color(3,71)=#0000ff
color(3,72)=#0000ff
color(3,73)=#0000ff
color(3,74)=#0000ff
color(3,75)=#0000ff
color(3,76)=#0000ff
color(3,77)=#0000ff
color(3,78)=#0000ff
color(3,79)=#0000ff
color(4,0)=#ffffff
color(4,1)=#ffffff
color(4,2)=#000000
color(4,3)=#c8c8c8
color(4,4)=#000000
color(4,5)=#ffffff
color(4,6)=#c00000
color(4,7)=#008000
color(4,8)=#000000
color(4,9)=#000000
color(4,10)=#0000ff
color(4,11)=#c08000
color(4,12)=#0000ff
color(4,13)=#0000ff
color(4,14)=#0000ff
color(4,15)=#0000ff
color(4,16)=#0000ff
color(4,17)=#0000ff
color(4,18)=#0000ff
color(4,19)=#208020
color(4,20)=#8040c0
color(4,21)=#0000ff
color(4,22)=#0000ff
color(4,23)=#0000ff
color(4,24)=#0000ff
color(4,25)=#0000ff
color(4,26)=#0000ff
color(4,27)=#0000ff
color(4,28)=#0000ff
color(4,29)=#0000ff
color(4,30)=#0000ff
color(4,31)=#0000ff
color(4,32)=#0000ff
color(4,33)=#0000ff
color(4,34)=#0000ff
color(4,35)=#0000ff
color(4,36)=#0000ff
color(4,37)=#0000ff
color(4,38)=#0000ff
color(4,39)=#0000ff
color(4,40)=#0000ff
color(4,41)=#0000ff
color(4,42)=#0000ff
color(4,43)=#0000ff
color(4,44)=#0000ff
color(4,45)=#0000ff
color(4,46)=#0000ff
color(4,47)=#0000ff
color(4,48)=#0000ff
color(4,49)=#0000ff
color(4,50)=#0000ff
color(4,51)=#0000ff
color(4,52)=#0000ff
color(4,53)=#0000ff
color(4,54)=#0000ff
color(4,55)=#0000ff
color(4,56)=#0000ff
color(4,57)=#0000ff
color(4,58)=#0000ff
color(4,59)=#0000ff
color(4,60)=#0000ff
color(4,61)=#0000ff
color(4,62)=#0000ff
color(4,63)=#0000ff
color(4,64)=#0000ff
color(4,65)=#0000ff
color(4,66)=#0000ff
color(4,67)=#0000ff
color(4,68)=#0000ff
color(4,69)=#0000ff
color(4,70)=#0000ff
color(4,71)=#0000ff
color(4,72)=#0000ff
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color(14,16)=#0000ff
color(14,17)=#0000ff
color(14,18)=#0000ff
color(14,19)=#208020
color(14,20)=#8040c0
color(14,21)=#0000ff
color(14,22)=#0000ff
color(14,23)=#0000ff
color(14,24)=#0000ff
color(14,25)=#0000ff
color(14,26)=#0000ff
color(14,27)=#0000ff
color(14,28)=#0000ff
color(14,29)=#0000ff
color(14,30)=#0000ff
color(14,31)=#0000ff
color(14,32)=#0000ff
color(14,33)=#0000ff
color(14,34)=#0000ff
color(14,35)=#0000ff
color(14,36)=#0000ff
color(14,37)=#0000ff
color(14,38)=#0000ff
color(14,39)=#0000ff
color(14,40)=#0000ff
color(14,41)=#0000ff
color(14,42)=#0000ff
color(14,43)=#0000ff
color(14,44)=#0000ff
color(14,45)=#0000ff
color(14,46)=#0000ff
color(14,47)=#0000ff
color(14,48)=#0000ff
color(14,49)=#0000ff
color(14,50)=#0000ff
color(14,51)=#0000ff
color(14,52)=#0000ff
color(14,53)=#0000ff
color(14,54)=#0000ff
color(14,55)=#0000ff
color(14,56)=#0000ff
color(14,57)=#0000ff
color(14,58)=#0000ff
color(14,59)=#0000ff
color(14,60)=#0000ff
color(14,61)=#0000ff
color(14,62)=#0000ff
color(14,63)=#0000ff
color(14,64)=#0000ff
color(14,65)=#0000ff
color(14,66)=#0000ff
color(14,67)=#0000ff
color(14,68)=#0000ff
color(14,69)=#0000ff
color(14,70)=#0000ff
color(14,71)=#0000ff
color(14,72)=#0000ff
color(14,73)=#0000ff
color(14,74)=#0000ff
color(14,75)=#0000ff
color(14,76)=#0000ff
color(14,77)=#0000ff
color(14,78)=#0000ff
color(14,79)=#0000ff
color(15,0)=#ffffff
color(15,1)=#ffffff
color(15,2)=#000000
color(15,3)=#c8c8c8
color(15,4)=#000000
color(15,5)=#ffffff
color(15,6)=#c00000
color(15,7)=#008000
color(15,8)=#000000
color(15,9)=#000000
color(15,10)=#0000ff
color(15,11)=#c08000
color(15,12)=#0000ff
color(15,13)=#0000ff
color(15,14)=#0000ff
color(15,15)=#0000ff
color(15,16)=#0000ff
color(15,17)=#0000ff
color(15,18)=#0000ff
color(15,19)=#208020
color(15,20)=#8040c0
color(15,21)=#0000ff
color(15,22)=#0000ff
color(15,23)=#0000ff
color(15,24)=#0000ff
color(15,25)=#0000ff
color(15,26)=#0000ff
color(15,27)=#0000ff
color(15,28)=#0000ff
color(15,29)=#0000ff
color(15,30)=#0000ff
color(15,31)=#0000ff
color(15,32)=#0000ff
color(15,33)=#0000ff
color(15,34)=#0000ff
color(15,35)=#0000ff
color(15,36)=#0000ff
color(15,37)=#0000ff
color(15,38)=#0000ff
color(15,39)=#0000ff
color(15,40)=#0000ff
color(15,41)=#0000ff
color(15,42)=#0000ff
color(15,43)=#0000ff
color(15,44)=#0000ff
color(15,45)=#0000ff
color(15,46)=#0000ff
color(15,47)=#0000ff
color(15,48)=#0000ff
color(15,49)=#0000ff
color(15,50)=#0000ff
color(15,51)=#0000ff
color(15,52)=#0000ff
color(15,53)=#0000ff
color(15,54)=#0000ff
color(15,55)=#0000ff
color(15,56)=#0000ff
color(15,57)=#0000ff
color(15,58)=#0000ff
color(15,59)=#0000ff
color(15,60)=#0000ff
color(15,61)=#0000ff
color(15,62)=#0000ff
color(15,63)=#0000ff
color(15,64)=#0000ff
color(15,65)=#0000ff
color(15,66)=#0000ff
color(15,67)=#0000ff
color(15,68)=#0000ff
color(15,69)=#0000ff
color(15,70)=#0000ff
color(15,71)=#0000ff
color(15,72)=#0000ff
color(15,73)=#0000ff
color(15,74)=#0000ff
color(15,75)=#0000ff
color(15,76)=#0000ff
color(15,77)=#0000ff
color(15,78)=#0000ff
color(15,79)=#0000ff
color(16,0)=#ffffff
color(16,1)=#ffffff
color(16,2)=#000000
color(16,3)=#c8c8c8
color(16,4)=#000000
color(16,5)=#ffffff
color(16,6)=#c00000
color(16,7)=#008000
color(16,8)=#000000
color(16,9)=#000000
color(16,10)=#0000ff
color(16,11)=#c08000
color(16,12)=#0000ff
color(16,13)=#0000ff
color(16,14)=#0000ff
color(16,15)=#0000ff
color(16,16)=#0000ff
color(16,17)=#0000ff
color(16,18)=#0000ff
color(16,19)=#208020
color(16,20)=#8040c0
color(16,21)=#0000ff
color(16,22)=#0000ff
color(16,23)=#0000ff
color(16,24)=#0000ff
color(16,25)=#0000ff
color(16,26)=#0000ff
color(16,27)=#0000ff
color(16,28)=#0000ff
color(16,29)=#0000ff
color(16,30)=#0000ff
color(16,31)=#0000ff
color(16,32)=#0000ff
color(16,33)=#0000ff
color(16,34)=#0000ff
color(16,35)=#0000ff
color(16,36)=#0000ff
color(16,37)=#0000ff
color(16,38)=#0000ff
color(16,39)=#0000ff
color(16,40)=#0000ff
color(16,41)=#0000ff
color(16,42)=#0000ff
color(16,43)=#0000ff
color(16,44)=#0000ff
color(16,45)=#0000ff
color(16,46)=#0000ff
color(16,47)=#0000ff
color(16,48)=#0000ff
color(16,49)=#0000ff
color(16,50)=#0000ff
color(16,51)=#0000ff
color(16,52)=#0000ff
color(16,53)=#0000ff
color(16,54)=#0000ff
color(16,55)=#0000ff
color(16,56)=#0000ff
color(16,57)=#0000ff
color(16,58)=#0000ff
color(16,59)=#0000ff
color(16,60)=#0000ff
color(16,61)=#0000ff
color(16,62)=#0000ff
color(16,63)=#0000ff
color(16,64)=#0000ff
color(16,65)=#0000ff
color(16,66)=#0000ff
color(16,67)=#0000ff
color(16,68)=#0000ff
color(16,69)=#0000ff
color(16,70)=#0000ff
color(16,71)=#0000ff
color(16,72)=#0000ff
color(16,73)=#0000ff
color(16,74)=#0000ff
color(16,75)=#0000ff
color(16,76)=#0000ff
color(16,77)=#0000ff
color(16,78)=#0000ff
color(16,79)=#0000ff
color(17,0)=#ffffff
color(17,1)=#ffffff
color(17,2)=#000000
color(17,3)=#c8c8c8
color(17,4)=#000000
color(17,5)=#ffffff
color(17,6)=#c00000
color(17,7)=#008000
color(17,8)=#000000
color(17,9)=#000000
color(17,10)=#0000ff
color(17,11)=#c08000
color(17,12)=#0000ff
color(17,13)=#0000ff
color(17,14)=#0000ff
color(17,15)=#0000ff
color(17,16)=#0000ff
color(17,17)=#0000ff
color(17,18)=#0000ff
color(17,19)=#208020
color(17,20)=#8040c0
color(17,21)=#0000ff
color(17,22)=#0000ff
color(17,23)=#0000ff
color(17,24)=#0000ff
color(17,25)=#0000ff
color(17,26)=#0000ff
color(17,27)=#0000ff
color(17,28)=#0000ff
color(17,29)=#0000ff
color(17,30)=#0000ff
color(17,31)=#0000ff
color(17,32)=#0000ff
color(17,33)=#0000ff
color(17,34)=#0000ff
color(17,35)=#0000ff
color(17,36)=#0000ff
color(17,37)=#0000ff
color(17,38)=#0000ff
color(17,39)=#0000ff
color(17,40)=#0000ff
color(17,41)=#0000ff
color(17,42)=#0000ff
color(17,43)=#0000ff
color(17,44)=#0000ff
color(17,45)=#0000ff
color(17,46)=#0000ff
color(17,47)=#0000ff
color(17,48)=#0000ff
color(17,49)=#0000ff
color(17,50)=#0000ff
color(17,51)=#0000ff
color(17,52)=#0000ff
color(17,53)=#0000ff
color(17,54)=#0000ff
color(17,55)=#0000ff
color(17,56)=#0000ff
color(17,57)=#0000ff
color(17,58)=#0000ff
color(17,59)=#0000ff
color(17,60)=#0000ff
color(17,61)=#0000ff
color(17,62)=#0000ff
color(17,63)=#0000ff
color(17,64)=#0000ff
color(17,65)=#0000ff
color(17,66)=#0000ff
color(17,67)=#0000ff
color(17,68)=#0000ff
color(17,69)=#0000ff
color(17,70)=#0000ff
color(17,71)=#0000ff
color(17,72)=#0000ff
color(17,73)=#0000ff
color(17,74)=#0000ff
color(17,75)=#0000ff
color(17,76)=#0000ff
color(17,77)=#0000ff
color(17,78)=#0000ff
color(17,79)=#0000ff
color(18,0)=#ffffff
color(18,1)=#ffffff
color(18,2)=#000000
color(18,3)=#c8c8c8
color(18,4)=#000000
color(18,5)=#ffffff
color(18,6)=#c00000
color(18,7)=#008000
color(18,8)=#000000
color(18,9)=#000000
color(18,10)=#0000ff
color(18,11)=#c08000
color(18,12)=#0000ff
color(18,13)=#0000ff
color(18,14)=#0000ff
color(18,15)=#0000ff
color(18,16)=#0000ff
color(18,17)=#0000ff
color(18,18)=#0000ff
color(18,19)=#208020
color(18,20)=#8040c0
color(18,21)=#0000ff
color(18,22)=#0000ff
color(18,23)=#0000ff
color(18,24)=#0000ff
color(18,25)=#0000ff
color(18,26)=#0000ff
color(18,27)=#0000ff
color(18,28)=#0000ff
color(18,29)=#0000ff
color(18,30)=#0000ff
color(18,31)=#0000ff
color(18,32)=#0000ff
color(18,33)=#0000ff
color(18,34)=#0000ff
color(18,35)=#0000ff
color(18,36)=#0000ff
color(18,37)=#0000ff
color(18,38)=#0000ff
color(18,39)=#0000ff
color(18,40)=#0000ff
color(18,41)=#0000ff
color(18,42)=#0000ff
color(18,43)=#0000ff
color(18,44)=#0000ff
color(18,45)=#0000ff
color(18,46)=#0000ff
color(18,47)=#0000ff
color(18,48)=#0000ff
color(18,49)=#0000ff
color(18,50)=#0000ff
color(18,51)=#0000ff
color(18,52)=#0000ff
color(18,53)=#0000ff
color(18,54)=#0000ff
color(18,55)=#0000ff
color(18,56)=#0000ff
color(18,57)=#0000ff
color(18,58)=#0000ff
color(18,59)=#0000ff
color(18,60)=#0000ff
color(18,61)=#0000ff
color(18,62)=#0000ff
color(18,63)=#0000ff
color(18,64)=#0000ff
color(18,65)=#0000ff
color(18,66)=#0000ff
color(18,67)=#0000ff
color(18,68)=#0000ff
color(18,69)=#0000ff
color(18,70)=#0000ff
color(18,71)=#0000ff
color(18,72)=#0000ff
color(18,73)=#0000ff
color(18,74)=#0000ff
color(18,75)=#0000ff
color(18,76)=#0000ff
color(18,77)=#0000ff
color(18,78)=#0000ff
color(18,79)=#0000ff
color(19,0)=#ffffff
color(19,1)=#ffffff
color(19,2)=#000000
color(19,3)=#c8c8c8
color(19,4)=#000000
color(19,5)=#ffffff
color(19,6)=#c00000
color(19,7)=#008000
color(19,8)=#000000
color(19,9)=#000000
color(19,10)=#0000ff
color(19,11)=#c08000
color(19,12)=#0000ff
color(19,13)=#0000ff
color(19,14)=#0000ff
color(19,15)=#0000ff
color(19,16)=#0000ff
color(19,17)=#0000ff
color(19,18)=#0000ff
color(19,19)=#208020
color(19,20)=#8040c0
color(19,21)=#0000ff
color(19,22)=#0000ff
color(19,23)=#0000ff
color(19,24)=#0000ff
color(19,25)=#0000ff
color(19,26)=#0000ff
color(19,27)=#0000ff
color(19,28)=#0000ff
color(19,29)=#0000ff
color(19,30)=#0000ff
color(19,31)=#0000ff
color(19,32)=#0000ff
color(19,33)=#0000ff
color(19,34)=#0000ff
color(19,35)=#0000ff
color(19,36)=#0000ff
color(19,37)=#0000ff
color(19,38)=#0000ff
color(19,39)=#0000ff
color(19,40)=#0000ff
color(19,41)=#0000ff
color(19,42)=#0000ff
color(19,43)=#0000ff
color(19,44)=#0000ff
color(19,45)=#0000ff
color(19,46)=#0000ff
color(19,47)=#0000ff
color(19,48)=#0000ff
color(19,49)=#0000ff
color(19,50)=#0000ff
color(19,51)=#0000ff
color(19,52)=#0000ff
color(19,53)=#0000ff
color(19,54)=#0000ff
color(19,55)=#0000ff
color(19,56)=#0000ff
color(19,57)=#0000ff
color(19,58)=#0000ff
color(19,59)=#0000ff
color(19,60)=#0000ff
color(19,61)=#0000ff
color(19,62)=#0000ff
color(19,63)=#0000ff
color(19,64)=#0000ff
color(19,65)=#0000ff
color(19,66)=#0000ff
color(19,67)=#0000ff
color(19,68)=#0000ff
color(19,69)=#0000ff
color(19,70)=#0000ff
color(19,71)=#0000ff
color(19,72)=#0000ff
color(19,73)=#0000ff
color(19,74)=#0000ff
color(19,75)=#0000ff
color(19,76)=#0000ff
color(19,77)=#0000ff
color(19,78)=#0000ff
color(19,79)=#0000ff
End Object
/trunk/rtl/verilog/HVCounter.v
0,0 → 1,148
// ============================================================================
// 2011 Robert Finch
// robfinch@<remove>sympatico.ca
//
// HVCounter.v
// Horizontal / Vertical counter:
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
 
// horizontal pixel prescale counter
// Each pixel may be multiple clocks wide
//
// 37 slices / 64 LUTs / 161.525 MHz
// 28 ff's / 1 Mult
 
module HVCounter(
rst, vclk, pixcce, sync, cnt_offs, pixsz, maxpix, nxt_pix, pos, nxt_pos, ctr
);
input rst;
input vclk; // video clock
input pixcce; // pixel counter clock enable
input sync; // synchronization input (eol or eof)
input [11:0] cnt_offs; // counter offset: top or left of display area
input [3:0] pixsz; // size of a pixel in video clock
input [4:0] maxpix; // maximum pixels for width / height of character
output nxt_pix; // when the next pixel will happen
output [11:0] pos; // current row or column position
output nxt_pos; // flag: when the row or column is about to change
output [11:0] ctr; // counter output
 
reg [11:0] pos;
reg [11:0] ctr;
reg nxt_pix;
 
wire [11:0] ctr1;
wire nxp;
reg [23:0] x4096;
 
// Lookup reciprocal of number of pixels per character
// - used to calculate the column position
reg [11:0] inv;
always @(posedge vclk)
case(maxpix)
5'd00: inv <= 12'd4095;
5'd01: inv <= 12'd2048;
5'd02: inv <= 12'd1365;
5'd03: inv <= 12'd1024;
5'd04: inv <= 12'd0819;
5'd05: inv <= 12'd0683;
5'd06: inv <= 12'd0585;
5'd07: inv <= 12'd0512;
5'd08: inv <= 12'd0455;
5'd09: inv <= 12'd0409;
5'd10: inv <= 12'd0372;
5'd11: inv <= 12'd0341;
5'd12: inv <= 12'd0315;
5'd13: inv <= 12'd0292;
5'd14: inv <= 12'd0273;
5'd15: inv <= 12'd0256;
5'd16: inv <= 12'd0240;
5'd17: inv <= 12'd0227;
5'd18: inv <= 12'd0215;
5'd19: inv <= 12'd0204;
5'd20: inv <= 12'd0195;
5'd21: inv <= 12'd0186;
5'd22: inv <= 12'd0178;
5'd23: inv <= 12'd0170;
5'd24: inv <= 12'd0163;
5'd25: inv <= 12'd0157;
5'd26: inv <= 12'd0151;
5'd27: inv <= 12'd0146;
5'd28: inv <= 12'd0141;
5'd29: inv <= 12'd0136;
5'd30: inv <= 12'd0132;
5'd31: inv <= 12'd0128;
endcase
 
 
// Calculate character position
// - divide the raw count by the number of pixels per character
// - done by multiplying by the reciprocal
always @(posedge vclk)
x4096 <= ctr * inv;
always @(x4096)
pos <= x4096[23:12];
always @(posedge vclk) // pipeline delay
ctr <= ctr1;
always @(posedge vclk)
nxt_pix <= nxp;
 
// Pixel width counter
// Controls number of clock cycles per pixel
VT163 #(4) u1
(
.clk(vclk),
.clr_n(!rst),
.ent(pixcce),
.enp(1'b1),
.ld_n(!sync & !nxp), // synchronize count to start of scan
.d(4'hF-pixsz),
.q(),
.rco(nxp)
);
 
 
// Pixel counter
// - raw pixel count
// - just increments every time the nxt_pix signal is active
// - synchronized to the end-of-line or end-of-frame signal
VT163 #(12) u2
(
.clk(vclk),
.clr_n(!rst),
.ent(nxp),
.enp(1'b1),
.ld_n(!sync), // synchronize count to start of scan
.d(12'h000-cnt_offs),
.q(ctr1),
.rco()
);
 
 
// Detect when the position changes
// - compare current pos to previous pos when the position might change
change_det #(12) u3
(
.rst(rst),
.clk(vclk),
.ce(nxt_pix),
.i(pos),
.cd(nxt_pos)
);
 
endmodule
/trunk/rtl/verilog/rtfSimpleUartTx.v
0,0 → 1,137
/* ============================================================================
2011 Robert Finch
robfinch@<remove>sympatico.ca
 
rtfSimpleUartTx.v
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
Simple uart transmitter core.
Features:
Fixed format 1 start - 8 data - 1 stop bits
 
 
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|WISHBONE Datasheet
|WISHBONE SoC Architecture Specification, Revision B.3
|
|Description: Specifications:
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|General Description: simple serial UART transmitter
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Supported Cycles: SLAVE,WRITE
| SLAVE,BLOCK WRITE
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Data port, size: 8 bit
|Data port, granularity: 8 bit
|Data port, maximum operand size: 8 bit
|Data transfer ordering: Undefined
|Data transfer sequencing: Undefined
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Clock frequency constraints: none
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Supported signal list and Signal Name WISHBONE equiv.
|cross reference to equivalent ack_o ACK_O
|WISHBONE signals
| clk_i CLK_I
| rst_i RST_I
| dat_i[7:0] DAT_I()
| cyc_i CYC_I
| stb_i STB_I
| we_i WE_I
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|Special requirements:
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
 
REF: Spartan3 - 4
30 LUTs / 23 slices / 165MHz
============================================================================ */
 
module rtfSimpleUartTx(
// WISHBONE SoC bus interface
input rst_i, // reset
input clk_i, // clock
input cyc_i, // cycle valid
input stb_i, // strobe
output ack_o, // transfer done
input we_i, // write transmitter
input [7:0] dat_i, // data in
//--------------------
input cs_i, // chip select
input baud16x_ce, // baud rate clock enable
input cts, // clear to send
output txd, // external serial output
output reg empty // buffer is empty
);
 
reg [9:0] tx_data; // transmit data working reg (raw)
reg [7:0] fdo; // data output
reg [7:0] cnt; // baud clock counter
reg rd;
 
assign ack_o = cyc_i & stb_i & cs_i;
assign txd = tx_data[0];
 
always @(posedge clk_i)
if (ack_o & we_i) fdo <= dat_i;
 
// set full / empty status
always @(posedge clk_i)
if (rst_i) empty <= 1;
else begin
if (ack_o & we_i) empty <= 0;
else if (rd) empty <= 1;
end
 
 
always @(posedge clk_i)
if (rst_i) begin
cnt <= 8'h00;
rd <= 0;
tx_data <= 10'h3FF;
end
else begin
 
rd <= 0;
 
if (baud16x_ce) begin
 
cnt <= cnt + 1;
// Load next data ?
if (cnt==8'h9F) begin
cnt <= 0;
if (!empty && cts) begin
tx_data <= {1'b1,fdo,1'b0};
rd <= 1;
end
end
// Shift the data out. LSB first.
else if (cnt[3:0]==4'hF)
tx_data <= {1'b1,tx_data[9:1]};
 
end
end
 
endmodule
/trunk/rtl/verilog/SampleCharGlyphs.ucf
0,0 → 1,132
# Character Glyphs
# 512 Ascii characters
#
INST tc1/charRam0/ram0 INIT_00=003C66060606663C003E66663E66663E006666667E663C18003C46067676663C;
INST tc1/charRam0/ram0 INIT_01=003C66667606663C000606061E06067E007E06061E06067E001E36666666361E;
INST tc1/charRam0/ram0 INIT_02=0066361E0E1E3666001C363030303078003C18181818183C006666667E666666;
INST tc1/charRam0/ram0 INIT_03=003C66666666663C006666767E7E6E6600C6C6C6D6FEEEC6007E060606060606;
INST tc1/charRam0/ram0 INIT_04=003C66603C06663C0066361E3E66663E00703C666666663C000606063E66663E;
INST tc1/charRam0/ram0 INIT_05=00C6EEFED6C6C6C600183C6666666666003C666666666666001818181818187E;
INST tc1/charRam0/ram0 INIT_06=003C0C0C0C0C0C3C007E060C1830607E001818183C6666660066663C183C6666;
INST tc1/charRam0/ram0 INIT_07=00080CFEFE0C0800181818187E3C1800003C30303030303C003F460C3E0C4830;
INST tc1/charRam0/ram0 INIT_08=006666FF66FF6666000000000066666600180000181818180000000000000000;
INST tc1/charRam0/ram0 INIT_09=000000000018306000FC66E61C3C663C0062660C1830664600183E603C067C18;
INST tc1/charRam0/ram0 INIT_0A=000018187E1818000000663CFF3C6600000C18303030180C0030180C0C0C1830;
INST tc1/charRam0/ram0 INIT_0B=00060C183060C0000018180000000000000000007E0000000C18180000000000;
INST tc1/charRam0/ram0 INIT_0C=003C66603860663C007E060C3060663C007E1818181C1818003C66666E76663C;
INST tc1/charRam0/ram0 INIT_0D=001818181830667E003C66663E06663C003C6660603E067E006060FE66787060;
INST tc1/charRam0/ram0 INIT_0E=0C181800001800000000180000180000003C66607C66663C003C66663C66663C;
INST tc1/charRam0/ram0 INIT_0F=001800183060663C000E18306030180E0000007E007E00000070180C060C1870;
INST tc1/charRam0/ram0 INIT_10=000000FFFF0000001818181818181818007C38FEFE7C3810000000FFFF000000;
INST tc1/charRam0/ram0 INIT_11=0C0C0C0C0C0C0C0C0000FFFF000000000000000000FFFF0000000000FFFF0000;
INST tc1/charRam0/ram0 INIT_12=000000070F1C1818000000E0F038181818181C0F070000003030303030303030;
INST tc1/charRam0/ram0 INIT_13=030303030303FFFF03070E1C3870E0C0C0E070381C0E0703FFFF030303030303;
INST tc1/charRam0/ram0 INIT_14=0010387CFEFEFE6C00FFFF0000000000003C7E7E7E7E3C00C0C0C0C0C0C0FFFF;
INST tc1/charRam0/ram0 INIT_15=003C7E66667E3C00C3E77E3C3C7EE7C3181838F0E00000000606060606060606;
INST tc1/charRam0/ram0 INIT_16=181818FFFF1818180010387CFE7C38106060606060606060003C181866661818;
INST tc1/charRam0/ram0 INIT_17=80C0E0F0F8FCFEFF006C6C6E7CC0000018181818181818180C0C03030C0C0303;
INST tc1/charRam0/ram0 INIT_18=00000000000000FFFFFFFFFF000000000F0F0F0F0F0F0F0F0000000000000000;
INST tc1/charRam0/ram0 INIT_19=C0C0C0C0C0C0C0C0CCCC3333CCCC33330303030303030303FF00000000000000;
INST tc1/charRam0/ram0 INIT_1A=181818F8F8181818C0C0C0C0C0C0C0C00103070F1F3F7FFFCCCC333300000000;
INST tc1/charRam0/ram0 INIT_1B=FFFF0000000000001818181F1F000000000000F8F8181818F0F0F0F000000000;
INST tc1/charRam0/ram0 INIT_1C=1818181F1F181818181818FFFF000000000000FFFF181818181818F8F8000000;
INST tc1/charRam0/ram0 INIT_1D=000000000000FFFFE0E0E0E0E0E0E0E007070707070707070303030303030303;
INST tc1/charRam0/ram0 INIT_1E=0F0F0F0F00000000FFFFC0C0C0C0C0C0FFFFFF00000000000000000000FFFFFF;
INST tc1/charRam0/ram0 INIT_1F=F0F0F0F00F0F0F0F000000000F0F0F0F0000001F1F18181800000000F0F0F0F0;
INST tc1/charRam0/ram0 INIT_20=FFC399F9F9F999C3FFC19999C19999C1FF9999998199C3E7FFC399F9898999C3;
INST tc1/charRam0/ram0 INIT_21=FFC3999989F999C3FFF9F9F9E1F9F981FF81F9F9E1F9F981FFE1C9999999C9E1;
INST tc1/charRam0/ram0 INIT_22=FF99C9E1F1E1C999FFE3C9CFCFCFCF87FFC3E7E7E7E7E7C3FF99999981999999;
INST tc1/charRam0/ram0 INIT_23=FFC39999999999C3FF99998981819199FF39393929011139FF81F9F9F9F9F9F9;
INST tc1/charRam0/ram0 INIT_24=FFC3999FC3F999C3FF99C9E1C19999C1FF8FC399999999C3FFF9F9F9C19999C1;
INST tc1/charRam0/ram0 INIT_25=FF39110129393939FFE7C39999999999FFC3999999999999FFE7E7E7E7E7E781;
INST tc1/charRam0/ram0 INIT_26=FFC3F3F3F3F3F3C3FF81F9F3E7CF9F81FFE7E7E7C3999999FF9999C3E7C39999;
INST tc1/charRam0/ram0 INIT_27=FFF7F30101F3F7FFE7E7E7E781C3E7FFFFC3CFCFCFCFCFC3FFC0B9F3C1F3B7CF;
INST tc1/charRam0/ram0 INIT_28=FF99990099009999FFFFFFFFFF999999FFE7FFFFE7E7E7E7FFFFFFFFFFFFFFFF;
INST tc1/charRam0/ram0 INIT_29=FFFFFFFFFFE7CF9FFF039919E3C399C3FF9D99F3E7CF99B9FFE7C19FC3F983E7;
INST tc1/charRam0/ram0 INIT_2A=FFFFE7E781E7E7FFFFFF99C300C399FFFFF3E7CFCFCFE7F3FFCFE7F3F3F3E7CF;
INST tc1/charRam0/ram0 INIT_2B=FFF9F3E7CF9F3FFFFFE7E7FFFFFFFFFFFFFFFFFF81FFFFFFF3E7E7FFFFFFFFFF;
INST tc1/charRam0/ram0 INIT_2C=FFC3999FC79F99C3FF81F9F3CF9F99C3FF81E7E7E7E3E7E7FFC39999918999C3;
INST tc1/charRam0/ram0 INIT_2D=FFE7E7E7E7CF9981FFC39999C1F999C3FFC3999F9FC1F981FF9F9F0199878F9F;
INST tc1/charRam0/ram0 INIT_2E=F3E7E7FFFFE7FFFFFFFFE7FFFFE7FFFFFFC3999F839999C3FFC39999C39999C3;
INST tc1/charRam0/ram0 INIT_2F=FFE7FFE7CF9F99C3FFF1E7CF9FCFE7F1FFFFFF81FF81FFFFFF8FE7F3F9F3E78F;
INST tc1/charRam0/ram0 INIT_30=FFFFFF0000FFFFFFE7E7E7E7E7E7E7E7FF83C7010183C7EFFFFFFF0000FFFFFF;
INST tc1/charRam0/ram0 INIT_31=F3F3F3F3F3F3F3F3FFFF0000FFFFFFFFFFFFFFFFFF0000FFFFFFFFFF0000FFFF;
INST tc1/charRam0/ram0 INIT_32=FFFFFFF8F0E3E7E7FFFFFF1F0FC7E7E7E7E7E3F0F8FFFFFFCFCFCFCFCFCFCFCF;
INST tc1/charRam0/ram0 INIT_33=FCFCFCFCFCFC0000FCF8F1E3C78F1F3F3F1F8FC7E3F1F8FC0000FCFCFCFCFCFC;
INST tc1/charRam0/ram0 INIT_34=FFEFC78301010193FF0000FFFFFFFFFFFFC381818181C3FF3F3F3F3F3F3F0000;
INST tc1/charRam0/ram0 INIT_35=FFC381999981C3FF3C1881C3C381183CE7E7C70F1FFFFFFFF9F9F9F9F9F9F9F9;
INST tc1/charRam0/ram0 INIT_36=E7E7E70000E7E7E7FFEFC7830183C7EF9F9F9F9F9F9F9F9FFFC3E7E79999E7E7;
INST tc1/charRam0/ram0 INIT_37=7F3F1F0F07030100FF939391833FFFFFE7E7E7E7E7E7E7E7F3F3FCFCF3F3FCFC;
INST tc1/charRam0/ram0 INIT_38=FFFFFFFFFFFFFF0000000000FFFFFFFFF0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFF;
INST tc1/charRam0/ram0 INIT_39=3F3F3F3F3F3F3F3F3333CCCC3333CCCCFCFCFCFCFCFCFCFC00FFFFFFFFFFFFFF;
INST tc1/charRam0/ram0 INIT_3A=E7E7E70707E7E7E73F3F3F3F3F3F3F3FFEFCF8F0E0C080003333CCCCFFFFFFFF;
INST tc1/charRam0/ram0 INIT_3B=0000FFFFFFFFFFFFE7E7E7E0E0FFFFFFFFFFFF0707E7E7E70F0F0F0FFFFFFFFF;
INST tc1/charRam0/ram0 INIT_3C=E7E7E7E0E0E7E7E7E7E7E70000FFFFFFFFFFFF0000E7E7E7E7E7E70707FFFFFF;
INST tc1/charRam0/ram0 INIT_3D=FFFFFFFFFFFF00001F1F1F1F1F1F1F1FF8F8F8F8F8F8F8F8FCFCFCFCFCFCFCFC;
INST tc1/charRam0/ram0 INIT_3E=F0F0F0F0FFFFFFFF00003F3F3F3F3F3F000000FFFFFFFFFFFFFFFFFFFF000000;
INST tc1/charRam0/ram0 INIT_3F=0F0F0F0FF0F0F0F0FFFFFFFFF0F0F0F0FFFFFFE0E0E7E7E7FFFFFFFF0F0F0F0F;
 
INST tc1/charRam0/ram1 INIT_00=003C0606063C0000003E66663E060600007C667C603C0000003C46067676663C;
INST tc1/charRam0/ram1 INIT_01=3E607C66667C0000001818187C187000003C067E663C0000007C66667C606000;
INST tc1/charRam0/ram1 INIT_02=0066361E360606003C60606060006000003C18181C001800006666663E060600;
INST tc1/charRam0/ram1 INIT_03=003C6666663C000000666666663E000000C6D6FEFE660000003C181818181C00;
INST tc1/charRam0/ram1 INIT_04=003E603C067C000000060606663E000060607C66667C000006063E66663E0000;
INST tc1/charRam0/ram1 INIT_05=006C7CFED6C6000000183C6666660000007C66666666000000701818187E1800;
INST tc1/charRam0/ram1 INIT_06=003C0C0C0C0C0C3C007E0C18307E00001E307C666666000000663C183C660000;
INST tc1/charRam0/ram1 INIT_07=00080CFEFE0C0800181818187E3C1800003C30303030303C003F460C3E0C4830;
INST tc1/charRam0/ram1 INIT_08=006666FF66FF6666000000000066666600180000181818180000000000000000;
INST tc1/charRam0/ram1 INIT_09=000000000018306000FC66E61C3C663C0062660C1830664600183E603C067C18;
INST tc1/charRam0/ram1 INIT_0A=000018187E1818000000663CFF3C6600000C18303030180C0030180C0C0C1830;
INST tc1/charRam0/ram1 INIT_0B=00060C183060C0000018180000000000000000007E0000000C18180000000000;
INST tc1/charRam0/ram1 INIT_0C=003C66603860663C007E060C3060663C007E1818181C1818003C66666E76663C;
INST tc1/charRam0/ram1 INIT_0D=001818181830667E003C66663E06663C003C6660603E067E006060FE66787060;
INST tc1/charRam0/ram1 INIT_0E=0C181800001800000000180000180000003C66607C66663C003C66663C66663C;
INST tc1/charRam0/ram1 INIT_0F=001800183060663C000E18306030180E0000007E007E00000070180C060C1870;
INST tc1/charRam0/ram1 INIT_10=003C66060606663C003E66663E66663E006666667E663C18000000FFFF000000;
INST tc1/charRam0/ram1 INIT_11=003C66667606663C000606061E06067E007E06061E06067E001E36666666361E;
INST tc1/charRam0/ram1 INIT_12=0066361E0E1E3666001C363030303078003C18181818183C006666667E666666;
INST tc1/charRam0/ram1 INIT_13=003C66666666663C006666767E7E6E6600C6C6C6D6FEEEC6007E060606060606;
INST tc1/charRam0/ram1 INIT_14=003C66603C06663C0066361E3E66663E00703C666666663C000606063E66663E;
INST tc1/charRam0/ram1 INIT_15=00C6EEFED6C6C6C600183C6666666666003C666666666666001818181818187E;
INST tc1/charRam0/ram1 INIT_16=181818FFFF181818007E060C1830607E001818183C6666660066663C183C6666;
INST tc1/charRam0/ram1 INIT_17=663399CC663399CC3333CCCC3333CCCC18181818181818180C0C03030C0C0303;
INST tc1/charRam0/ram1 INIT_18=00000000000000FFFFFFFFFF000000000F0F0F0F0F0F0F0F0000000000000000;
INST tc1/charRam0/ram1 INIT_19=C0C0C0C0C0C0C0C0CCCC3333CCCC33330303030303030303FF00000000000000;
INST tc1/charRam0/ram1 INIT_1A=181818F8F8181818C0C0C0C0C0C0C0C066CC993366CC9933CCCC333300000000;
INST tc1/charRam0/ram1 INIT_1B=FFFF0000000000001818181F1F000000000000F8F8181818F0F0F0F000000000;
INST tc1/charRam0/ram1 INIT_1C=1818181F1F181818181818FFFF000000000000FFFF181818181818F8F8000000;
INST tc1/charRam0/ram1 INIT_1D=000000000000FFFFE0E0E0E0E0E0E0E007070707070707070303030303030303;
INST tc1/charRam0/ram1 INIT_1E=0F0F0F0F0000000000060E1E3660C080FFFFFF00000000000000000000FFFFFF;
INST tc1/charRam0/ram1 INIT_1F=F0F0F0F00F0F0F0F000000000F0F0F0F0000001F1F18181800000000F0F0F0F0;
INST tc1/charRam0/ram1 INIT_20=FFC3F9F9F9C3FFFFFFC19999C1F9F9FFFF8399839FC3FFFFFFC399F9898999C3;
INST tc1/charRam0/ram1 INIT_21=C19F83999983FFFFFFE7E7E783E78FFFFFC3F98199C3FFFFFF839999839F9FFF;
INST tc1/charRam0/ram1 INIT_22=FF99C9E1C9F9F9FFC39F9F9F9FFF9FFFFFC3E7E7E3FFE7FFFF999999C1F9F9FF;
INST tc1/charRam0/ram1 INIT_23=FFC3999999C3FFFFFF99999999C1FFFFFF3929010199FFFFFFC3E7E7E7E7E3FF;
INST tc1/charRam0/ram1 INIT_24=FFC19FC3F983FFFFFFF9F9F999C1FFFF9F9F83999983FFFFF9F9C19999C1FFFF;
INST tc1/charRam0/ram1 INIT_25=FF9383012939FFFFFFE7C3999999FFFFFF8399999999FFFFFF8FE7E7E781E7FF;
INST tc1/charRam0/ram1 INIT_26=FFC3F3F3F3F3F3C3FF81F3E7CF81FFFFE1CF83999999FFFFFF99C3E7C399FFFF;
INST tc1/charRam0/ram1 INIT_27=FFF7F30101F3F7FFE7E7E7E781C3E7FFFFC3CFCFCFCFCFC3FFC0B9F3C1F3B7CF;
INST tc1/charRam0/ram1 INIT_28=FF99990099009999FFFFFFFFFF999999FFE7FFFFE7E7E7E7FFFFFFFFFFFFFFFF;
INST tc1/charRam0/ram1 INIT_29=FFFFFFFFFFE7CF9FFF039919E3C399C3FF9D99F3E7CF99B9FFE7C19FC3F983E7;
INST tc1/charRam0/ram1 INIT_2A=FFFFE7E781E7E7FFFFFF99C300C399FFFFF3E7CFCFCFE7F3FFCFE7F3F3F3E7CF;
INST tc1/charRam0/ram1 INIT_2B=FFF9F3E7CF9F3FFFFFE7E7FFFFFFFFFFFFFFFFFF81FFFFFFF3E7E7FFFFFFFFFF;
INST tc1/charRam0/ram1 INIT_2C=FFC3999FC79F99C3FF81F9F3CF9F99C3FF81E7E7E7E3E7E7FFC39999918999C3;
INST tc1/charRam0/ram1 INIT_2D=FFE7E7E7E7CF9981FFC39999C1F999C3FFC3999F9FC1F981FF9F9F0199878F9F;
INST tc1/charRam0/ram1 INIT_2E=F3E7E7FFFFE7FFFFFFFFE7FFFFE7FFFFFFC3999F839999C3FFC39999C39999C3;
INST tc1/charRam0/ram1 INIT_2F=FFE7FFE7CF9F99C3FFF1E7CF9FCFE7F1FFFFFF81FF81FFFFFF8FE7F3F9F3E78F;
INST tc1/charRam0/ram1 INIT_30=FFC399F9F9F999C3FFC19999C19999C1FF9999998199C3E7FFFFFF0000FFFFFF;
INST tc1/charRam0/ram1 INIT_31=FFC3999989F999C3FFF9F9F9E1F9F981FF81F9F9E1F9F981FFE1C9999999C9E1;
INST tc1/charRam0/ram1 INIT_32=FF99C9E1F1E1C999FFE3C9CFCFCFCF87FFC3E7E7E7E7E7C3FF99999981999999;
INST tc1/charRam0/ram1 INIT_33=FFC39999999999C3FF99998981819199FF39393929011139FF81F9F9F9F9F9F9;
INST tc1/charRam0/ram1 INIT_34=FFC3999FC3F999C3FF99C9E1C19999C1FF8FC399999999C3FFF9F9F9C19999C1;
INST tc1/charRam0/ram1 INIT_35=FF39110129393939FFE7C39999999999FFC3999999999999FFE7E7E7E7E7E781;
INST tc1/charRam0/ram1 INIT_36=E7E7E70000E7E7E7FF81F9F3E7CF9F81FFE7E7E7C3999999FF9999C3E7C39999;
INST tc1/charRam0/ram1 INIT_37=99CC663399CC6633CCCC3333CCCC3333E7E7E7E7E7E7E7E7F3F3FCFCF3F3FCFC;
INST tc1/charRam0/ram1 INIT_38=FFFFFFFFFFFFFF0000000000FFFFFFFFF0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFF;
INST tc1/charRam0/ram1 INIT_39=3F3F3F3F3F3F3F3F3333CCCC3333CCCCFCFCFCFCFCFCFCFC00FFFFFFFFFFFFFF;
INST tc1/charRam0/ram1 INIT_3A=E7E7E70707E7E7E73F3F3F3F3F3F3F3F993366CC993366CC3333CCCCFFFFFFFF;
INST tc1/charRam0/ram1 INIT_3B=0000FFFFFFFFFFFFE7E7E7E0E0FFFFFFFFFFFF0707E7E7E70F0F0F0FFFFFFFFF;
INST tc1/charRam0/ram1 INIT_3C=E7E7E7E0E0E7E7E7E7E7E70000FFFFFFFFFFFF0000E7E7E7E7E7E70707FFFFFF;
INST tc1/charRam0/ram1 INIT_3D=FFFFFFFFFFFF00001F1F1F1F1F1F1F1FF8F8F8F8F8F8F8F8FCFCFCFCFCFCFCFC;
INST tc1/charRam0/ram1 INIT_3E=F0F0F0F0FFFFFFFFFFF9F1E1C99F3F7F000000FFFFFFFFFFFFFFFFFFFF000000;
INST tc1/charRam0/ram1 INIT_3F=0F0F0F0FF0F0F0F0FFFFFFFFF0F0F0F0FFFFFFE0E0E7E7E7FFFFFFFF0F0F0F0F;
/trunk/rtl/verilog/seven_seg.v
0,0 → 1,100
// ============================================================================
// (C) 2005-2011 Robert Finch
// All Rights Reserved.
//
// seven_seg.v
// Seven segment display driver.
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// Webpack 9.2i xc3s1200e 4fg320
// 32 slices / 62 LUTs / 208.160 MHz
// 27 ff's / 1 DCM
//
// 500us on per digit
// 10us interdigit blanking
//=============================================================================
 
module seven_seg(rst, clk, dp, val, ssLedAnode, ssLedSeg);
parameter pClkFreq=25000000;
parameter pTermCnt=pClkFreq/250000;
input rst; // reset
input clk; // clock
input [3:0] dp;
input [15:0] val;
output [3:0] ssLedAnode;
output [7:0] ssLedSeg;
 
reg [3:0] ssLedAnode;
reg [7:0] ssLedSeg;
 
// Generate 250kHz clock from input
wire [ 9:0] q1;
wire [11:0] q2;
down_counter #(10) u1 (rst, clk, 1'b1, z, pTermCnt, q1, z);
counter #(12) u2 (rst, clk, z, 1'b0, 12'h000, q2);
 
reg [4:0] nyb;
 
wire [2:0] dig_ndx = q2[11:9];
wire dig_en = q2[8:1]!=8'hFF;
 
always @(dig_ndx or dig_en)
if (dig_en)
case (dig_ndx)
3'd0: ssLedAnode = 4'hE;
3'd1: ssLedAnode = 4'hD;
3'd2: ssLedAnode = 4'hB;
3'd3: ssLedAnode = 4'h7;
default: ssLedAnode = 4'hF;
endcase
else
ssLedAnode = 4'hF;
 
always @(dig_ndx or dp or val)
case (dig_ndx)
3'd0: nyb = {dp[0],val[ 3: 0]};
3'd1: nyb = {dp[1],val[ 7: 4]};
3'd2: nyb = {dp[2],val[11: 8]};
3'd3: nyb = {dp[3],val[15:12]};
default: nyb = 5'd0;
endcase
 
always @(dig_en or nyb)
if (dig_en) begin
case (nyb[3:0])
4'h0: ssLedSeg <= 8'b11000000;
4'h1: ssLedSeg <= 8'b11111001;
4'h2: ssLedSeg <= 8'b10100100;
4'h3: ssLedSeg <= 8'b10110000;
4'h4: ssLedSeg <= 8'b10011001;
4'h5: ssLedSeg <= 8'b10010010;
4'h6: ssLedSeg <= 8'b10000010;
4'h7: ssLedSeg <= 8'b11111000;
4'h8: ssLedSeg <= 8'b10000000;
4'h9: ssLedSeg <= 8'b10011000;
4'hA: ssLedSeg <= 8'b10001000;
4'hB: ssLedSeg <= 8'b10000011;
4'hC: ssLedSeg <= 8'b11000110;
4'hD: ssLedSeg <= 8'b10100001;
4'hE: ssLedSeg <= 8'b10000110;
4'hF: ssLedSeg <= 8'b10001110;
endcase
ssLedSeg[7] <= !nyb[4];
end
else
ssLedSeg <= 8'b11111111;
 
endmodule
/trunk/rtl/verilog/counter.v
0,0 → 1,43
// ============================================================================
// (C) 2007 Robert Finch
// All Rights Reserved.
//
// counter.v
// generic up counter
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module counter(rst, clk, ce, ld, d, q);
parameter WID=8;
input rst;
input clk;
input ce;
input ld;
input [WID:1] d;
output [WID:1] q;
reg [WID:1] q;
 
always @(posedge clk)
if (rst)
q <= 0;
else if (ce) begin
if (ld)
q <= d;
else
q <= q + 1;
end
 
endmodule
/trunk/rtl/verilog/My8x8charset.ucf
0,0 → 1,129
INST charrom0 INIT_00=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_01=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_02=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_03=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_04=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_05=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_06=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_07=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_08=0024247E247E2424000000000024242400080008080808080000000000000000;
INST charrom0 INIT_09=00000000000000000000000000000000006162040810234300083E283E0A3E08;
INST charrom0 INIT_0A=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_0B=0000000000000000000000000000000000000000000000000000000000000000;
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INST charrom0 INIT_0E=00040800080800000000000C000C0000001C20203C22221C001C22221C22221C;
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INST charrom0 INIT_10=001C22020202221C001E22221E22221E002222223E141C08001C3E361A02221C;
INST charrom0 INIT_11=001C22223202221C000202020E02023E003E02020E02023E001E22222222221E;
INST charrom0 INIT_12=0022120A060A1222000C12101010101C001C08080808081C002222223E222222;
INST charrom0 INIT_13=001C22222222221C002232322A26262200222222222A3622003E020202020202;
INST charrom0 INIT_14=001C22201C02221C0022120A1E22221E003C322A2222221C000202021E22221E;
INST charrom0 INIT_15=002A3636222222220008142222222222001C222222222222000808080808083E;
INST charrom0 INIT_16=001C04040404041C003E02040810203E00080808081422220022221408142222;
INST charrom0 INIT_17=007F000000000000000000000022140800382020202020380020101008040402;
INST charrom0 INIT_18=000C1202120C0000000C12120E020200002C120C100C00000000000000040201;
INST charrom0 INIT_19=1C203824241800000004040C042418000018041C04180000001C22223C202000;
INST charrom0 INIT_1A=00120A060A1202000C121010101000000008080808000800002424241C040400;
INST charrom0 INIT_1B=001C22221C000000001212120E000000002A2A2A140000000018080808080800;
INST charrom0 INIT_1C=001C2018041800000004042418000000103C12120C000000041C24241C000000;
INST charrom0 INIT_1D=002A3622220000000008142222000000001C222222000000000808083E080800;
INST charrom0 INIT_1E=1008080408081000001C0408101C00000C101C12120000000022140814220000;
INST charrom0 INIT_1F=0000000000000000000000000019260004080810080804000008080808080808;
INST charrom0 INIT_20=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_21=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_22=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_23=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_24=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_25=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_26=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_27=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_28=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_29=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_2A=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_2B=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_2C=000030300C0C0303000030300006060000000018180000000000000000000000;
INST charrom0 INIT_2D=000000003333007F000000000303007F000000000000007F0000333300003333;
INST charrom0 INIT_2E=00000000000000000000000000000000003333003333007F000303003333007F;
INST charrom0 INIT_2F=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_30=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_31=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_32=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_33=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_34=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_35=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_36=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_37=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_38=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_39=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_3A=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_3B=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_3C=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_3D=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_3E=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom0 INIT_3F=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_00=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_01=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_02=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_03=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_04=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_05=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_06=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_07=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_08=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_09=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_0A=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_0B=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_0C=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_0D=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_0E=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_0F=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_10=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_11=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_12=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_13=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_14=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_15=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_16=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_17=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_18=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_19=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_1A=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_1B=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_1C=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_1D=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_1E=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_1F=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_20=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_21=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_22=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_23=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_24=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_25=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_26=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_27=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_28=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_29=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_2A=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_2B=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_2C=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_2D=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_2E=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_2F=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_30=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_31=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_32=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_33=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_34=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_35=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_36=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_37=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_38=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_39=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_3A=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_3B=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_3C=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_3D=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_3E=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom1 INIT_3F=0000000000000000000000000000000000000000000000000000000000000000;
INST charrom2 INIT_00=0000000000000000000000000000000000000000000000000000000000000000;
/trunk/rtl/verilog/PSRAMCtrl_PudTimer.v
0,0 → 1,54
// ============================================================================
// 2008 Robert Finch
//
// PSRAM power up delay timer
// PSRAM requires a 150 us delay on power up before operation
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// Webpack 9.2i xc3s1200e-4fg320
// 21 LUTs / 12 slices / 220.848MHz
// 20 FFs
//
// ============================================================================
 
module PSRAMCtrl_PudTimer(rst, clk, pud);
parameter pClkFreq = 60000000; // 60 MHz
parameter tPWR = pClkFreq / 6667 + 1; // 150 micro seconds
input rst;
input clk;
output pud;
 
reg [19:0] pudcnt;
assign pud = ~pudcnt[19];
 
always @(posedge clk)
if (rst)
pudcnt <= tPWR;
else begin
if (pudcnt[19]==1'b0)
pudcnt <= pudcnt - 20'd1;
end
 
endmodule
/trunk/rtl/verilog/dac121s101.v
0,0 → 1,142
//=============================================================================
// dac121s101
// - DAC (digital to analogue) converter interface core
//
//
// 2010 Robert T Finch
// robfinch<remove>@FPGAfield.ca
//
//
// This source code is available only for veiwing, testing and evaluation
// purposes. Any commercial use requires a license. This copyright
// statement and disclaimer must remain present in the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// Webpack 9.2i xc3s1200e 4fg320
// 38 slices / 71 LUTs / 183.824 MHz
// 36 ff's
//
//=============================================================================
 
module dac121s101(rst_i, clk_i, cyc_i, stb_i, ack_o, we_i, dat_i, sclk, sync, d);
parameter pClkFreq=60000000;
parameter pPrescale=pClkFreq/50000000 + 1; //2x freq
// states
parameter IDLE=4'd0;
parameter LOAD=4'd1;
parameter SHIFT=4'd2;
parameter TERM=4'd3;
 
// SYSCON
input rst_i;
input clk_i;
 
input cyc_i;
input stb_i;
input we_i;
output ack_o;
input [15:0] dat_i;
 
output sclk;
output sync;
output d;
 
// Registered outputs
reg sclk;
reg sync;
 
reg [1:0] state;
reg pe_sclk;
reg [7:0] ps_cnt; // prescale counter
reg [3:0] cnt; // shift bit counter
reg [15:0] dd;
reg ack;
 
assign ack_o = cyc_i & stb_i & ack;
 
 
// Prescale the system clock
// The DAC has a max clock frequency of 30MHz.
//
always @(posedge clk_i)
if (rst_i) begin
ps_cnt <= 8'd1;
sclk <= 1'b0;
pe_sclk <= 1'b0;
end
else begin
pe_sclk <= 1'b0;
if (ps_cnt==pPrescale) begin
ps_cnt <= 8'd1;
sclk <= !sclk;
pe_sclk <= sclk==1'b0;
end
else
ps_cnt <= ps_cnt + 8'd1;
end
 
 
always @(posedge clk_i)
if (rst_i) begin
ack <= 1'b0;
sync <= 1'b1;
dd <= 16'h0000;
cnt <= 4'd0;
state <= IDLE;
end
else begin
 
if (!cyc_i || !stb_i)
ack <= 1'b0;
 
case(state)
IDLE:
if (cyc_i & stb_i & we_i) begin
state <= LOAD;
dd[11:0] <= dat_i[13:0];
dd[15:12] <= 4'b0000;
ack <= 1'b1;
end
LOAD:
if (pe_sclk) begin
sync <= 1'b0;
cnt <= 4'd0;
state <= SHIFT;
end
SHIFT:
if (pe_sclk) begin
dd <= {dd[14:0],1'b0};
cnt <= cnt + 4'd1;
if (cnt==4'd15)
state <= TERM;
end
TERM:
if (pe_sclk) begin
sync <= 1'b1;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
 
assign d = dd[15];
 
endmodule
/trunk/rtl/verilog/bootrom.v
0,0 → 1,3816
module bootrom(clk,adr,romo);
input clk;
input [31:0] adr;
output [15:0] romo;
reg [15:0] romo;
reg [15:0] romout;
always @(adr)
case(adr & 32'hFFFFFFFE)
32'hFFFF1000: romout <= 16'h564C;
32'hFFFF1002: romout <= 16'h4944;
32'hFFFF1004: romout <= 16'h0010;
32'hFFFF1006: romout <= 16'h0000;
32'hFFFF1008: romout <= 16'h0020;
32'hFFFF100A: romout <= 16'h0000;
32'hFFFF100C: romout <= 16'h0000;
32'hFFFF100E: romout <= 16'h0000;
32'hFFFF1010: romout <= 16'h0000;
32'hFFFF1012: romout <= 16'h0000;
32'hFFFF1014: romout <= 16'hFFFF;
32'hFFFF1016: romout <= 16'h1074;
32'hFFFF1018: romout <= 16'hFFFF;
32'hFFFF101A: romout <= 16'h1084;
32'hFFFF101C: romout <= 16'h0000;
32'hFFFF101E: romout <= 16'h0003;
32'hFFFF1020: romout <= 16'hFFFF;
32'hFFFF1022: romout <= 16'h1A5E;
32'hFFFF1024: romout <= 16'h4D4F;
32'hFFFF1026: romout <= 16'h4E49;
32'hFFFF1028: romout <= 16'h544F;
32'hFFFF102A: romout <= 16'h5220;
32'hFFFF102C: romout <= 16'h0000;
32'hFFFF102E: romout <= 16'h0800;
32'hFFFF1030: romout <= 16'h0000;
32'hFFFF1032: romout <= 16'h0000;
32'hFFFF1034: romout <= 16'h0000;
32'hFFFF1036: romout <= 16'h0000;
32'hFFFF1038: romout <= 16'h0000;
32'hFFFF103A: romout <= 16'h0001;
32'hFFFF103C: romout <= 16'hFFFF;
32'hFFFF103E: romout <= 16'h2400;
32'hFFFF1040: romout <= 16'h5449;
32'hFFFF1042: romout <= 16'h4E59;
32'hFFFF1044: romout <= 16'h2042;
32'hFFFF1046: romout <= 16'h4153;
32'hFFFF1048: romout <= 16'h0000;
32'hFFFF104A: romout <= 16'h0800;
32'hFFFF104C: romout <= 16'h0000;
32'hFFFF104E: romout <= 16'h0000;
32'hFFFF1050: romout <= 16'h0000;
32'hFFFF1052: romout <= 16'h0000;
32'hFFFF1054: romout <= 16'h0001;
32'hFFFF1056: romout <= 16'h0002;
32'hFFFF1058: romout <= 16'hFFFF;
32'hFFFF105A: romout <= 16'h12EC;
32'hFFFF105C: romout <= 16'h4944;
32'hFFFF105E: romout <= 16'h4C45;
32'hFFFF1060: romout <= 16'h5441;
32'hFFFF1062: romout <= 16'h534B;
32'hFFFF1064: romout <= 16'h0000;
32'hFFFF1066: romout <= 16'h0400;
32'hFFFF1068: romout <= 16'h0000;
32'hFFFF106A: romout <= 16'h0000;
32'hFFFF106C: romout <= 16'h0000;
32'hFFFF106E: romout <= 16'h0000;
32'hFFFF1070: romout <= 16'h0001;
32'hFFFF1072: romout <= 16'h0003;
32'hFFFF1074: romout <= 16'hFFFF;
32'hFFFF1076: romout <= 16'h16B0;
32'hFFFF1078: romout <= 16'hFFFF;
32'hFFFF107A: romout <= 16'h16D4;
32'hFFFF107C: romout <= 16'hFFFF;
32'hFFFF107E: romout <= 16'h1680;
32'hFFFF1080: romout <= 16'hFFFF;
32'hFFFF1082: romout <= 16'h169A;
32'hFFFF1084: romout <= 16'h0000;
32'hFFFF1086: romout <= 16'h0200;
32'hFFFF1100: romout <= 16'h31FC;
32'hFFFF1102: romout <= 16'h00CE;
32'hFFFF1104: romout <= 16'h0414;
32'hFFFF1106: romout <= 16'h11FC;
32'hFFFF1108: romout <= 16'h0001;
32'hFFFF110A: romout <= 16'h041C;
32'hFFFF110C: romout <= 16'h4EB9;
32'hFFFF110E: romout <= 16'hFFFF;
32'hFFFF1110: romout <= 16'h18E8;
32'hFFFF1112: romout <= 16'h4278;
32'hFFFF1114: romout <= 16'h0418;
32'hFFFF1116: romout <= 16'h4278;
32'hFFFF1118: romout <= 16'h041A;
32'hFFFF111A: romout <= 16'h43F9;
32'hFFFF111C: romout <= 16'hFFFF;
32'hFFFF111E: romout <= 16'h1238;
32'hFFFF1120: romout <= 16'h4EB9;
32'hFFFF1122: romout <= 16'hFFFF;
32'hFFFF1124: romout <= 16'h1858;
32'hFFFF1126: romout <= 16'h47F9;
32'hFFFF1128: romout <= 16'hFFFF;
32'hFFFF112A: romout <= 16'h1132;
32'hFFFF112C: romout <= 16'h4EF9;
32'hFFFF112E: romout <= 16'hFFFF;
32'hFFFF1130: romout <= 16'h1F52;
32'hFFFF1132: romout <= 16'h2079;
32'hFFFF1134: romout <= 16'hFFFF;
32'hFFFF1136: romout <= 16'h2420;
32'hFFFF1138: romout <= 16'h4E60;
32'hFFFF113A: romout <= 16'h31FC;
32'hFFFF113C: romout <= 16'h00CE;
32'hFFFF113E: romout <= 16'h0414;
32'hFFFF1140: romout <= 16'h11FC;
32'hFFFF1142: romout <= 16'h0001;
32'hFFFF1144: romout <= 16'h041C;
32'hFFFF1146: romout <= 16'h4278;
32'hFFFF1148: romout <= 16'h0418;
32'hFFFF114A: romout <= 16'h4278;
32'hFFFF114C: romout <= 16'h041A;
32'hFFFF114E: romout <= 16'h223C;
32'hFFFF1150: romout <= 16'h0000;
32'hFFFF1152: romout <= 16'h8000;
32'hFFFF1154: romout <= 16'h41F9;
32'hFFFF1156: romout <= 16'hFFD8;
32'hFFFF1158: romout <= 16'h0000;
32'hFFFF115A: romout <= 16'h2039;
32'hFFFF115C: romout <= 16'hFFDC;
32'hFFFF115E: romout <= 16'h0C00;
32'hFFFF1160: romout <= 16'h30C0;
32'hFFFF1162: romout <= 16'h5381;
32'hFFFF1164: romout <= 16'h66F4;
32'hFFFF1166: romout <= 16'h41F9;
32'hFFFF1168: romout <= 16'hFFFF;
32'hFFFF116A: romout <= 16'h2022;
32'hFFFF116C: romout <= 16'h21C8;
32'hFFFF116E: romout <= 16'h0008;
32'hFFFF1170: romout <= 16'h41F9;
32'hFFFF1172: romout <= 16'hFFFF;
32'hFFFF1174: romout <= 16'h200C;
32'hFFFF1176: romout <= 16'h21C8;
32'hFFFF1178: romout <= 16'h000C;
32'hFFFF117A: romout <= 16'h41F9;
32'hFFFF117C: romout <= 16'hFFFF;
32'hFFFF117E: romout <= 16'h2038;
32'hFFFF1180: romout <= 16'h21C8;
32'hFFFF1182: romout <= 16'h0010;
32'hFFFF1184: romout <= 16'h41F9;
32'hFFFF1186: romout <= 16'hFFFF;
32'hFFFF1188: romout <= 16'h1298;
32'hFFFF118A: romout <= 16'h21C8;
32'hFFFF118C: romout <= 16'h0078;
32'hFFFF118E: romout <= 16'h41F9;
32'hFFFF1190: romout <= 16'hFFFF;
32'hFFFF1192: romout <= 16'h1250;
32'hFFFF1194: romout <= 16'h21C8;
32'hFFFF1196: romout <= 16'h007C;
32'hFFFF1198: romout <= 16'h41F9;
32'hFFFF119A: romout <= 16'hFFFF;
32'hFFFF119C: romout <= 16'h0800;
32'hFFFF119E: romout <= 16'h21C8;
32'hFFFF11A0: romout <= 16'h0080;
32'hFFFF11A2: romout <= 16'h41F9;
32'hFFFF11A4: romout <= 16'hFFFF;
32'hFFFF11A6: romout <= 16'h0400;
32'hFFFF11A8: romout <= 16'h21C8;
32'hFFFF11AA: romout <= 16'h0084;
32'hFFFF11AC: romout <= 16'h41F9;
32'hFFFF11AE: romout <= 16'hFFFF;
32'hFFFF11B0: romout <= 16'h0C00;
32'hFFFF11B2: romout <= 16'h21C8;
32'hFFFF11B4: romout <= 16'h0088;
32'hFFFF11B6: romout <= 16'h41F9;
32'hFFFF11B8: romout <= 16'hFFFF;
32'hFFFF11BA: romout <= 16'h1312;
32'hFFFF11BC: romout <= 16'h21C8;
32'hFFFF11BE: romout <= 16'h00BC;
32'hFFFF11C0: romout <= 16'h42B8;
32'hFFFF11C2: romout <= 16'h0400;
32'hFFFF11C4: romout <= 16'h027C;
32'hFFFF11C6: romout <= 16'hF000;
32'hFFFF11C8: romout <= 16'h700E;
32'hFFFF11CA: romout <= 16'h43F9;
32'hFFFF11CC: romout <= 16'hFFFF;
32'hFFFF11CE: romout <= 16'h1241;
32'hFFFF11D0: romout <= 16'h4E4F;
32'hFFFF11D2: romout <= 16'h4EF9;
32'hFFFF11D4: romout <= 16'hFFFF;
32'hFFFF11D6: romout <= 16'h2400;
32'hFFFF11D8: romout <= 16'h7005;
32'hFFFF11DA: romout <= 16'h4E4F;
32'hFFFF11DC: romout <= 16'h0C01;
32'hFFFF11DE: romout <= 16'h0078;
32'hFFFF11E0: romout <= 16'h66F0;
32'hFFFF11E2: romout <= 16'h203C;
32'hFFFF11E4: romout <= 16'h0004;
32'hFFFF11E6: romout <= 16'h0000;
32'hFFFF11E8: romout <= 16'h41F9;
32'hFFFF11EA: romout <= 16'h0002;
32'hFFFF11EC: romout <= 16'h0000;
32'hFFFF11EE: romout <= 16'h343C;
32'hFFFF11F0: romout <= 16'h1234;
32'hFFFF11F2: romout <= 16'h30C2;
32'hFFFF11F4: romout <= 16'h5380;
32'hFFFF11F6: romout <= 16'h66FA;
32'hFFFF11F8: romout <= 16'h4EF9;
32'hFFFF11FA: romout <= 16'hFFFF;
32'hFFFF11FC: romout <= 16'h2400;
32'hFFFF11FE: romout <= 16'h4239;
32'hFFFF1200: romout <= 16'hFFDC;
32'hFFFF1202: romout <= 16'h0A07;
32'hFFFF1204: romout <= 16'h45F9;
32'hFFFF1206: romout <= 16'hFFFF;
32'hFFFF1208: romout <= 16'h0000;
32'hFFFF120A: romout <= 16'h121A;
32'hFFFF120C: romout <= 16'h1039;
32'hFFFF120E: romout <= 16'hFFDC;
32'hFFFF1210: romout <= 16'h0A01;
32'hFFFF1212: romout <= 16'h0800;
32'hFFFF1214: romout <= 16'h0005;
32'hFFFF1216: romout <= 16'h67F4;
32'hFFFF1218: romout <= 16'h13C1;
32'hFFFF121A: romout <= 16'hFFDC;
32'hFFFF121C: romout <= 16'h0A00;
32'hFFFF121E: romout <= 16'hB5FC;
32'hFFFF1220: romout <= 16'hFFFF;
32'hFFFF1222: romout <= 16'h0100;
32'hFFFF1224: romout <= 16'h65E4;
32'hFFFF1226: romout <= 16'h60DC;
32'hFFFF1228: romout <= 16'h1039;
32'hFFFF122A: romout <= 16'hFFDD;
32'hFFFF122C: romout <= 16'h0000;
32'hFFFF122E: romout <= 16'h6AF8;
32'hFFFF1230: romout <= 16'h2079;
32'hFFFF1232: romout <= 16'hFFDD;
32'hFFFF1234: romout <= 16'h0004;
32'hFFFF1236: romout <= 16'h4ED0;
32'hFFFF1238: romout <= 16'h5241;
32'hFFFF123A: romout <= 16'h4D20;
32'hFFFF123C: romout <= 16'h5445;
32'hFFFF123E: romout <= 16'h5354;
32'hFFFF1240: romout <= 16'h0042;
32'hFFFF1242: romout <= 16'h4F4F;
32'hFFFF1244: romout <= 16'h5449;
32'hFFFF1246: romout <= 16'h4E47;
32'hFFFF1248: romout <= 16'h2E2E;
32'hFFFF124A: romout <= 16'h2E2E;
32'hFFFF124C: romout <= 16'h00FF;
32'hFFFF124E: romout <= 16'hFFFF;
32'hFFFF1250: romout <= 16'h4EF9;
32'hFFFF1252: romout <= 16'hFFFF;
32'hFFFF1254: romout <= 16'h1100;
32'hFFFF1256: romout <= 16'h4E73;
32'hFFFF1258: romout <= 16'h48E7;
32'hFFFF125A: romout <= 16'hC080;
32'hFFFF125C: romout <= 16'h3238;
32'hFFFF125E: romout <= 16'h0450;
32'hFFFF1260: romout <= 16'h0241;
32'hFFFF1262: romout <= 16'h000F;
32'hFFFF1264: romout <= 16'h41F8;
32'hFFFF1266: romout <= 16'h0440;
32'hFFFF1268: romout <= 16'h3039;
32'hFFFF126A: romout <= 16'hFFDC;
32'hFFFF126C: romout <= 16'h0000;
32'hFFFF126E: romout <= 16'h4279;
32'hFFFF1270: romout <= 16'hFFDC;
32'hFFFF1272: romout <= 16'h0002;
32'hFFFF1274: romout <= 16'h1180;
32'hFFFF1276: romout <= 16'h1000;
32'hFFFF1278: romout <= 16'h5241;
32'hFFFF127A: romout <= 16'h0241;
32'hFFFF127C: romout <= 16'h000F;
32'hFFFF127E: romout <= 16'h31C1;
32'hFFFF1280: romout <= 16'h0450;
32'hFFFF1282: romout <= 16'hB278;
32'hFFFF1284: romout <= 16'h0452;
32'hFFFF1286: romout <= 16'h660A;
32'hFFFF1288: romout <= 16'h5241;
32'hFFFF128A: romout <= 16'h0241;
32'hFFFF128C: romout <= 16'h000F;
32'hFFFF128E: romout <= 16'h31C1;
32'hFFFF1290: romout <= 16'h0452;
32'hFFFF1292: romout <= 16'h4CDF;
32'hFFFF1294: romout <= 16'h0103;
32'hFFFF1296: romout <= 16'h4E73;
32'hFFFF1298: romout <= 16'h2F00;
32'hFFFF129A: romout <= 16'h52B8;
32'hFFFF129C: romout <= 16'h0400;
32'hFFFF129E: romout <= 16'h5279;
32'hFFFF12A0: romout <= 16'hFFD0;
32'hFFFF12A2: romout <= 16'h0066;
32'hFFFF12A4: romout <= 16'h4A39;
32'hFFFF12A6: romout <= 16'hFFFF;
32'hFFFF12A8: romout <= 16'h0000;
32'hFFFF12AA: romout <= 16'h2038;
32'hFFFF12AC: romout <= 16'h0400;
32'hFFFF12AE: romout <= 16'h0200;
32'hFFFF12B0: romout <= 16'h007F;
32'hFFFF12B2: romout <= 16'h0C00;
32'hFFFF12B4: romout <= 16'h0040;
32'hFFFF12B6: romout <= 16'h6604;
32'hFFFF12B8: romout <= 16'h6100;
32'hFFFF12BA: romout <= 16'h0006;
32'hFFFF12BC: romout <= 16'h201F;
32'hFFFF12BE: romout <= 16'h4E73;
32'hFFFF12C0: romout <= 16'h48E7;
32'hFFFF12C2: romout <= 16'hA0C0;
32'hFFFF12C4: romout <= 16'h6100;
32'hFFFF12C6: romout <= 16'h0440;
32'hFFFF12C8: romout <= 16'hD1FC;
32'hFFFF12CA: romout <= 16'h0001;
32'hFFFF12CC: romout <= 16'h0000;
32'hFFFF12CE: romout <= 16'h3010;
32'hFFFF12D0: romout <= 16'hE818;
32'hFFFF12D2: romout <= 16'h3080;
32'hFFFF12D4: romout <= 16'hB1F8;
32'hFFFF12D6: romout <= 16'h0404;
32'hFFFF12D8: romout <= 16'h670C;
32'hFFFF12DA: romout <= 16'h2278;
32'hFFFF12DC: romout <= 16'h0404;
32'hFFFF12DE: romout <= 16'h32B8;
32'hFFFF12E0: romout <= 16'h0414;
32'hFFFF12E2: romout <= 16'h21C8;
32'hFFFF12E4: romout <= 16'h0404;
32'hFFFF12E6: romout <= 16'h4CDF;
32'hFFFF12E8: romout <= 16'h0305;
32'hFFFF12EA: romout <= 16'h4E75;
32'hFFFF12EC: romout <= 16'h4E55;
32'hFFFF12EE: romout <= 16'hFFE8;
32'hFFFF12F0: romout <= 16'h41ED;
32'hFFFF12F2: romout <= 16'hFFFA;
32'hFFFF12F4: romout <= 16'h43ED;
32'hFFFF12F6: romout <= 16'hFFFC;
32'hFFFF12F8: romout <= 16'h3B7C;
32'hFFFF12FA: romout <= 16'h0000;
32'hFFFF12FC: romout <= 16'hFFFA;
32'hFFFF12FE: romout <= 16'h3B7C;
32'hFFFF1300: romout <= 16'h0002;
32'hFFFF1302: romout <= 16'hFFF8;
32'hFFFF1304: romout <= 16'h7048;
32'hFFFF1306: romout <= 16'h4E41;
32'hFFFF1308: romout <= 16'h5279;
32'hFFFF130A: romout <= 16'hFFD0;
32'hFFFF130C: romout <= 16'h0064;
32'hFFFF130E: romout <= 16'h4E40;
32'hFFFF1310: romout <= 16'h60F6;
32'hFFFF1312: romout <= 16'h48E7;
32'hFFFF1314: romout <= 16'h8080;
32'hFFFF1316: romout <= 16'h41F9;
32'hFFFF1318: romout <= 16'hFFFF;
32'hFFFF131A: romout <= 16'h1330;
32'hFFFF131C: romout <= 16'h0280;
32'hFFFF131E: romout <= 16'h0000;
32'hFFFF1320: romout <= 16'h00FF;
32'hFFFF1322: romout <= 16'hE580;
32'hFFFF1324: romout <= 16'h2070;
32'hFFFF1326: romout <= 16'h0000;
32'hFFFF1328: romout <= 16'h4E90;
32'hFFFF132A: romout <= 16'h4CDF;
32'hFFFF132C: romout <= 16'h0101;
32'hFFFF132E: romout <= 16'h4E73;
32'hFFFF1330: romout <= 16'hFFFF;
32'hFFFF1332: romout <= 16'h189A;
32'hFFFF1334: romout <= 16'hFFFF;
32'hFFFF1336: romout <= 16'h187A;
32'hFFFF1338: romout <= 16'hFFFF;
32'hFFFF133A: romout <= 16'h149C;
32'hFFFF133C: romout <= 16'hFFFF;
32'hFFFF133E: romout <= 16'h19A0;
32'hFFFF1340: romout <= 16'hFFFF;
32'hFFFF1342: romout <= 16'h149C;
32'hFFFF1344: romout <= 16'hFFFF;
32'hFFFF1346: romout <= 16'h1658;
32'hFFFF1348: romout <= 16'hFFFF;
32'hFFFF134A: romout <= 16'h1732;
32'hFFFF134C: romout <= 16'hFFFF;
32'hFFFF134E: romout <= 16'h16DA;
32'hFFFF1350: romout <= 16'hFFFF;
32'hFFFF1352: romout <= 16'h149C;
32'hFFFF1354: romout <= 16'hFFFF;
32'hFFFF1356: romout <= 16'h149C;
32'hFFFF1358: romout <= 16'hFFFF;
32'hFFFF135A: romout <= 16'h149C;
32'hFFFF135C: romout <= 16'hFFFF;
32'hFFFF135E: romout <= 16'h18A2;
32'hFFFF1360: romout <= 16'hFFFF;
32'hFFFF1362: romout <= 16'h162C;
32'hFFFF1364: romout <= 16'hFFFF;
32'hFFFF1366: romout <= 16'h1872;
32'hFFFF1368: romout <= 16'hFFFF;
32'hFFFF136A: romout <= 16'h1858;
32'hFFFF136C: romout <= 16'hFFFF;
32'hFFFF136E: romout <= 16'h149C;
32'hFFFF1370: romout <= 16'hFFFF;
32'hFFFF1372: romout <= 16'h149C;
32'hFFFF1374: romout <= 16'hFFFF;
32'hFFFF1376: romout <= 16'h149C;
32'hFFFF1378: romout <= 16'hFFFF;
32'hFFFF137A: romout <= 16'h149C;
32'hFFFF137C: romout <= 16'hFFFF;
32'hFFFF137E: romout <= 16'h149C;
32'hFFFF1380: romout <= 16'hFFFF;
32'hFFFF1382: romout <= 16'h198C;
32'hFFFF1384: romout <= 16'hFFFF;
32'hFFFF1386: romout <= 16'h149C;
32'hFFFF1388: romout <= 16'hFFFF;
32'hFFFF138A: romout <= 16'h149C;
32'hFFFF138C: romout <= 16'hFFFF;
32'hFFFF138E: romout <= 16'h149C;
32'hFFFF1390: romout <= 16'hFFFF;
32'hFFFF1392: romout <= 16'h149C;
32'hFFFF1394: romout <= 16'hFFFF;
32'hFFFF1396: romout <= 16'h149C;
32'hFFFF1398: romout <= 16'hFFFF;
32'hFFFF139A: romout <= 16'h149C;
32'hFFFF139C: romout <= 16'hFFFF;
32'hFFFF139E: romout <= 16'h149C;
32'hFFFF13A0: romout <= 16'hFFFF;
32'hFFFF13A2: romout <= 16'h149C;
32'hFFFF13A4: romout <= 16'hFFFF;
32'hFFFF13A6: romout <= 16'h149C;
32'hFFFF13A8: romout <= 16'hFFFF;
32'hFFFF13AA: romout <= 16'h149C;
32'hFFFF13AC: romout <= 16'hFFFF;
32'hFFFF13AE: romout <= 16'h149C;
32'hFFFF13B0: romout <= 16'hFFFF;
32'hFFFF13B2: romout <= 16'h149C;
32'hFFFF13B4: romout <= 16'hFFFF;
32'hFFFF13B6: romout <= 16'h149C;
32'hFFFF13B8: romout <= 16'hFFFF;
32'hFFFF13BA: romout <= 16'h149C;
32'hFFFF13BC: romout <= 16'hFFFF;
32'hFFFF13BE: romout <= 16'h149C;
32'hFFFF13C0: romout <= 16'hFFFF;
32'hFFFF13C2: romout <= 16'h149C;
32'hFFFF13C4: romout <= 16'hFFFF;
32'hFFFF13C6: romout <= 16'h149C;
32'hFFFF13C8: romout <= 16'hFFFF;
32'hFFFF13CA: romout <= 16'h149C;
32'hFFFF13CC: romout <= 16'hFFFF;
32'hFFFF13CE: romout <= 16'h149C;
32'hFFFF13D0: romout <= 16'hFFFF;
32'hFFFF13D2: romout <= 16'h149C;
32'hFFFF13D4: romout <= 16'hFFFF;
32'hFFFF13D6: romout <= 16'h149C;
32'hFFFF13D8: romout <= 16'hFFFF;
32'hFFFF13DA: romout <= 16'h149C;
32'hFFFF13DC: romout <= 16'hFFFF;
32'hFFFF13DE: romout <= 16'h149C;
32'hFFFF13E0: romout <= 16'hFFFF;
32'hFFFF13E2: romout <= 16'h149C;
32'hFFFF13E4: romout <= 16'hFFFF;
32'hFFFF13E6: romout <= 16'h149C;
32'hFFFF13E8: romout <= 16'hFFFF;
32'hFFFF13EA: romout <= 16'h149C;
32'hFFFF13EC: romout <= 16'hFFFF;
32'hFFFF13EE: romout <= 16'h149C;
32'hFFFF13F0: romout <= 16'hFFFF;
32'hFFFF13F2: romout <= 16'h149C;
32'hFFFF13F4: romout <= 16'hFFFF;
32'hFFFF13F6: romout <= 16'h149C;
32'hFFFF13F8: romout <= 16'hFFFF;
32'hFFFF13FA: romout <= 16'h149C;
32'hFFFF13FC: romout <= 16'hFFFF;
32'hFFFF13FE: romout <= 16'h149C;
32'hFFFF1400: romout <= 16'hFFFF;
32'hFFFF1402: romout <= 16'h149C;
32'hFFFF1404: romout <= 16'hFFFF;
32'hFFFF1406: romout <= 16'h149C;
32'hFFFF1408: romout <= 16'hFFFF;
32'hFFFF140A: romout <= 16'h149C;
32'hFFFF140C: romout <= 16'hFFFF;
32'hFFFF140E: romout <= 16'h149C;
32'hFFFF1410: romout <= 16'hFFFF;
32'hFFFF1412: romout <= 16'h149C;
32'hFFFF1414: romout <= 16'hFFFF;
32'hFFFF1416: romout <= 16'h149C;
32'hFFFF1418: romout <= 16'hFFFF;
32'hFFFF141A: romout <= 16'h149C;
32'hFFFF141C: romout <= 16'hFFFF;
32'hFFFF141E: romout <= 16'h149C;
32'hFFFF1420: romout <= 16'hFFFF;
32'hFFFF1422: romout <= 16'h149C;
32'hFFFF1424: romout <= 16'hFFFF;
32'hFFFF1426: romout <= 16'h149C;
32'hFFFF1428: romout <= 16'hFFFF;
32'hFFFF142A: romout <= 16'h149C;
32'hFFFF142C: romout <= 16'hFFFF;
32'hFFFF142E: romout <= 16'h149C;
32'hFFFF1430: romout <= 16'hFFFF;
32'hFFFF1432: romout <= 16'h149C;
32'hFFFF1434: romout <= 16'hFFFF;
32'hFFFF1436: romout <= 16'h149C;
32'hFFFF1438: romout <= 16'hFFFF;
32'hFFFF143A: romout <= 16'h149C;
32'hFFFF143C: romout <= 16'hFFFF;
32'hFFFF143E: romout <= 16'h149C;
32'hFFFF1440: romout <= 16'hFFFF;
32'hFFFF1442: romout <= 16'h149C;
32'hFFFF1444: romout <= 16'hFFFF;
32'hFFFF1446: romout <= 16'h149C;
32'hFFFF1448: romout <= 16'hFFFF;
32'hFFFF144A: romout <= 16'h149C;
32'hFFFF144C: romout <= 16'hFFFF;
32'hFFFF144E: romout <= 16'h149C;
32'hFFFF1450: romout <= 16'hFFFF;
32'hFFFF1452: romout <= 16'h149C;
32'hFFFF1454: romout <= 16'hFFFF;
32'hFFFF1456: romout <= 16'h149C;
32'hFFFF1458: romout <= 16'hFFFF;
32'hFFFF145A: romout <= 16'h149C;
32'hFFFF145C: romout <= 16'hFFFF;
32'hFFFF145E: romout <= 16'h149C;
32'hFFFF1460: romout <= 16'hFFFF;
32'hFFFF1462: romout <= 16'h149C;
32'hFFFF1464: romout <= 16'hFFFF;
32'hFFFF1466: romout <= 16'h149C;
32'hFFFF1468: romout <= 16'hFFFF;
32'hFFFF146A: romout <= 16'h149C;
32'hFFFF146C: romout <= 16'hFFFF;
32'hFFFF146E: romout <= 16'h149C;
32'hFFFF1470: romout <= 16'hFFFF;
32'hFFFF1472: romout <= 16'h149E;
32'hFFFF1474: romout <= 16'hFFFF;
32'hFFFF1476: romout <= 16'h14B4;
32'hFFFF1478: romout <= 16'hFFFF;
32'hFFFF147A: romout <= 16'h14FE;
32'hFFFF147C: romout <= 16'hFFFF;
32'hFFFF147E: romout <= 16'h149C;
32'hFFFF1480: romout <= 16'hFFFF;
32'hFFFF1482: romout <= 16'h1528;
32'hFFFF1484: romout <= 16'hFFFF;
32'hFFFF1486: romout <= 16'h159A;
32'hFFFF1488: romout <= 16'hFFFF;
32'hFFFF148A: romout <= 16'h15B4;
32'hFFFF148C: romout <= 16'hFFFF;
32'hFFFF148E: romout <= 16'h15FA;
32'hFFFF1490: romout <= 16'hFFFF;
32'hFFFF1492: romout <= 16'h149C;
32'hFFFF1494: romout <= 16'hFFFF;
32'hFFFF1496: romout <= 16'h149C;
32'hFFFF1498: romout <= 16'hFFFF;
32'hFFFF149A: romout <= 16'h15BE;
32'hFFFF149C: romout <= 16'h4E75;
32'hFFFF149E: romout <= 16'h48E7;
32'hFFFF14A0: romout <= 16'hC000;
32'hFFFF14A2: romout <= 16'h21C1;
32'hFFFF14A4: romout <= 16'h0420;
32'hFFFF14A6: romout <= 16'h6100;
32'hFFFF14A8: romout <= 16'h0022;
32'hFFFF14AA: romout <= 16'h11C1;
32'hFFFF14AC: romout <= 16'h0424;
32'hFFFF14AE: romout <= 16'h4CDF;
32'hFFFF14B0: romout <= 16'h0003;
32'hFFFF14B2: romout <= 16'h4E75;
32'hFFFF14B4: romout <= 16'h48E7;
32'hFFFF14B6: romout <= 16'hC000;
32'hFFFF14B8: romout <= 16'h21C1;
32'hFFFF14BA: romout <= 16'h0428;
32'hFFFF14BC: romout <= 16'h6100;
32'hFFFF14BE: romout <= 16'h000C;
32'hFFFF14C0: romout <= 16'h11C1;
32'hFFFF14C2: romout <= 16'h042C;
32'hFFFF14C4: romout <= 16'h4CDF;
32'hFFFF14C6: romout <= 16'h0003;
32'hFFFF14C8: romout <= 16'h4E75;
32'hFFFF14CA: romout <= 16'h48E7;
32'hFFFF14CC: romout <= 16'hA000;
32'hFFFF14CE: romout <= 16'h4282;
32'hFFFF14D0: romout <= 16'hEC99;
32'hFFFF14D2: romout <= 16'h2001;
32'hFFFF14D4: romout <= 16'h0200;
32'hFFFF14D6: romout <= 16'h0003;
32'hFFFF14D8: romout <= 16'h1400;
32'hFFFF14DA: romout <= 16'hE499;
32'hFFFF14DC: romout <= 16'hEA99;
32'hFFFF14DE: romout <= 16'h1001;
32'hFFFF14E0: romout <= 16'h0200;
32'hFFFF14E2: romout <= 16'h0007;
32'hFFFF14E4: romout <= 16'hE540;
32'hFFFF14E6: romout <= 16'h8400;
32'hFFFF14E8: romout <= 16'hE699;
32'hFFFF14EA: romout <= 16'hEA99;
32'hFFFF14EC: romout <= 16'h1001;
32'hFFFF14EE: romout <= 16'h0200;
32'hFFFF14F0: romout <= 16'h0007;
32'hFFFF14F2: romout <= 16'hEB40;
32'hFFFF14F4: romout <= 16'h8400;
32'hFFFF14F6: romout <= 16'h2202;
32'hFFFF14F8: romout <= 16'h4CDF;
32'hFFFF14FA: romout <= 16'h0005;
32'hFFFF14FC: romout <= 16'h4E75;
32'hFFFF14FE: romout <= 16'h48E7;
32'hFFFF1500: romout <= 16'h6080;
32'hFFFF1502: romout <= 16'hC4FC;
32'hFFFF1504: romout <= 16'h00D0;
32'hFFFF1506: romout <= 16'h0282;
32'hFFFF1508: romout <= 16'h0000;
32'hFFFF150A: romout <= 16'hFFFF;
32'hFFFF150C: romout <= 16'hE382;
32'hFFFF150E: romout <= 16'h0281;
32'hFFFF1510: romout <= 16'h0000;
32'hFFFF1512: romout <= 16'h01FF;
32'hFFFF1514: romout <= 16'hD481;
32'hFFFF1516: romout <= 16'h0682;
32'hFFFF1518: romout <= 16'h0002;
32'hFFFF151A: romout <= 16'h0000;
32'hFFFF151C: romout <= 16'h2042;
32'hFFFF151E: romout <= 16'h10B8;
32'hFFFF1520: romout <= 16'h0424;
32'hFFFF1522: romout <= 16'h4CDF;
32'hFFFF1524: romout <= 16'h0106;
32'hFFFF1526: romout <= 16'h4E75;
32'hFFFF1528: romout <= 16'h48E7;
32'hFFFF152A: romout <= 16'hFF30;
32'hFFFF152C: romout <= 16'h0281;
32'hFFFF152E: romout <= 16'h0000;
32'hFFFF1530: romout <= 16'h01FF;
32'hFFFF1532: romout <= 16'h0282;
32'hFFFF1534: romout <= 16'h0000;
32'hFFFF1536: romout <= 16'h01FF;
32'hFFFF1538: romout <= 16'h0283;
32'hFFFF153A: romout <= 16'h0000;
32'hFFFF153C: romout <= 16'h01FF;
32'hFFFF153E: romout <= 16'h0284;
32'hFFFF1540: romout <= 16'h0000;
32'hFFFF1542: romout <= 16'h01FF;
32'hFFFF1544: romout <= 16'h31C3;
32'hFFFF1546: romout <= 16'h0430;
32'hFFFF1548: romout <= 16'h31C4;
32'hFFFF154A: romout <= 16'h0432;
32'hFFFF154C: romout <= 16'h2A01;
32'hFFFF154E: romout <= 16'h9A83;
32'hFFFF1550: romout <= 16'h6A02;
32'hFFFF1552: romout <= 16'h4485;
32'hFFFF1554: romout <= 16'h2C02;
32'hFFFF1556: romout <= 16'h9C84;
32'hFFFF1558: romout <= 16'h6A02;
32'hFFFF155A: romout <= 16'h4486;
32'hFFFF155C: romout <= 16'h7001;
32'hFFFF155E: romout <= 16'h7E01;
32'hFFFF1560: romout <= 16'hB283;
32'hFFFF1562: romout <= 16'h6502;
32'hFFFF1564: romout <= 16'h4480;
32'hFFFF1566: romout <= 16'hB484;
32'hFFFF1568: romout <= 16'h6502;
32'hFFFF156A: romout <= 16'h4487;
32'hFFFF156C: romout <= 16'h2445;
32'hFFFF156E: romout <= 16'h95C6;
32'hFFFF1570: romout <= 16'h4486;
32'hFFFF1572: romout <= 16'h6100;
32'hFFFF1574: romout <= 16'hFF8A;
32'hFFFF1576: romout <= 16'hB681;
32'hFFFF1578: romout <= 16'h6604;
32'hFFFF157A: romout <= 16'hB882;
32'hFFFF157C: romout <= 16'h6716;
32'hFFFF157E: romout <= 16'h264A;
32'hFFFF1580: romout <= 16'hD7CB;
32'hFFFF1582: romout <= 16'hB7C6;
32'hFFFF1584: romout <= 16'h6F04;
32'hFFFF1586: romout <= 16'hD5C6;
32'hFFFF1588: romout <= 16'hD280;
32'hFFFF158A: romout <= 16'hB7C5;
32'hFFFF158C: romout <= 16'h6C04;
32'hFFFF158E: romout <= 16'hD5C5;
32'hFFFF1590: romout <= 16'hD487;
32'hFFFF1592: romout <= 16'h60DE;
32'hFFFF1594: romout <= 16'h4CDF;
32'hFFFF1596: romout <= 16'h0CFF;
32'hFFFF1598: romout <= 16'h4E75;
32'hFFFF159A: romout <= 16'h48E7;
32'hFFFF159C: romout <= 16'h7800;
32'hFFFF159E: romout <= 16'h3601;
32'hFFFF15A0: romout <= 16'h3802;
32'hFFFF15A2: romout <= 16'h3238;
32'hFFFF15A4: romout <= 16'h0430;
32'hFFFF15A6: romout <= 16'h3438;
32'hFFFF15A8: romout <= 16'h0432;
32'hFFFF15AA: romout <= 16'h6100;
32'hFFFF15AC: romout <= 16'hFF7C;
32'hFFFF15AE: romout <= 16'h4CDF;
32'hFFFF15B0: romout <= 16'h001E;
32'hFFFF15B2: romout <= 16'h4E75;
32'hFFFF15B4: romout <= 16'h31C1;
32'hFFFF15B6: romout <= 16'h0430;
32'hFFFF15B8: romout <= 16'h31C2;
32'hFFFF15BA: romout <= 16'h0432;
32'hFFFF15BC: romout <= 16'h4E75;
32'hFFFF15BE: romout <= 16'h48E7;
32'hFFFF15C0: romout <= 16'hFF00;
32'hFFFF15C2: romout <= 16'h3001;
32'hFFFF15C4: romout <= 16'h3E02;
32'hFFFF15C6: romout <= 16'h3A03;
32'hFFFF15C8: romout <= 16'h3C04;
32'hFFFF15CA: romout <= 16'h3802;
32'hFFFF15CC: romout <= 16'h6100;
32'hFFFF15CE: romout <= 16'hFF5A;
32'hFFFF15D0: romout <= 16'h3203;
32'hFFFF15D2: romout <= 16'h3404;
32'hFFFF15D4: romout <= 16'h3605;
32'hFFFF15D6: romout <= 16'h3806;
32'hFFFF15D8: romout <= 16'h6100;
32'hFFFF15DA: romout <= 16'hFF4E;
32'hFFFF15DC: romout <= 16'h3203;
32'hFFFF15DE: romout <= 16'h3404;
32'hFFFF15E0: romout <= 16'h3600;
32'hFFFF15E2: romout <= 16'h3806;
32'hFFFF15E4: romout <= 16'h6100;
32'hFFFF15E6: romout <= 16'hFF42;
32'hFFFF15E8: romout <= 16'h3203;
32'hFFFF15EA: romout <= 16'h3404;
32'hFFFF15EC: romout <= 16'h3600;
32'hFFFF15EE: romout <= 16'h3807;
32'hFFFF15F0: romout <= 16'h6100;
32'hFFFF15F2: romout <= 16'hFF36;
32'hFFFF15F4: romout <= 16'h4CDF;
32'hFFFF15F6: romout <= 16'h00FF;
32'hFFFF15F8: romout <= 16'h4E75;
32'hFFFF15FA: romout <= 16'h48E7;
32'hFFFF15FC: romout <= 16'h7800;
32'hFFFF15FE: romout <= 16'h3F38;
32'hFFFF1600: romout <= 16'h0424;
32'hFFFF1602: romout <= 16'h6100;
32'hFFFF1604: romout <= 16'hFFBA;
32'hFFFF1606: romout <= 16'h31F8;
32'hFFFF1608: romout <= 16'h042C;
32'hFFFF160A: romout <= 16'h0424;
32'hFFFF160C: romout <= 16'hB641;
32'hFFFF160E: romout <= 16'h6504;
32'hFFFF1610: romout <= 16'hB842;
32'hFFFF1612: romout <= 16'h640E;
32'hFFFF1614: romout <= 16'h5241;
32'hFFFF1616: romout <= 16'h5242;
32'hFFFF1618: romout <= 16'h5343;
32'hFFFF161A: romout <= 16'h5344;
32'hFFFF161C: romout <= 16'h6100;
32'hFFFF161E: romout <= 16'hFFA0;
32'hFFFF1620: romout <= 16'h60EA;
32'hFFFF1622: romout <= 16'h31DF;
32'hFFFF1624: romout <= 16'h0424;
32'hFFFF1626: romout <= 16'h4CDF;
32'hFFFF1628: romout <= 16'h001E;
32'hFFFF162A: romout <= 16'h4E75;
32'hFFFF162C: romout <= 16'h11C1;
32'hFFFF162E: romout <= 16'h041C;
32'hFFFF1630: romout <= 16'h4E75;
32'hFFFF1632: romout <= 16'h4E71;
32'hFFFF1634: romout <= 16'h4E71;
32'hFFFF1636: romout <= 16'h4E71;
32'hFFFF1638: romout <= 16'h4E71;
32'hFFFF163A: romout <= 16'h4E71;
32'hFFFF163C: romout <= 16'h4E71;
32'hFFFF163E: romout <= 16'h4E71;
32'hFFFF1640: romout <= 16'h4E71;
32'hFFFF1642: romout <= 16'h4E71;
32'hFFFF1644: romout <= 16'h4E71;
32'hFFFF1646: romout <= 16'h4E71;
32'hFFFF1648: romout <= 16'h4E71;
32'hFFFF164A: romout <= 16'h4E71;
32'hFFFF164C: romout <= 16'h4E71;
32'hFFFF164E: romout <= 16'h4E71;
32'hFFFF1650: romout <= 16'h4E71;
32'hFFFF1652: romout <= 16'h4E71;
32'hFFFF1654: romout <= 16'h4E71;
32'hFFFF1656: romout <= 16'h4E71;
32'hFFFF1658: romout <= 16'h3239;
32'hFFFF165A: romout <= 16'hFFDC;
32'hFFFF165C: romout <= 16'h0000;
32'hFFFF165E: romout <= 16'h6AF8;
32'hFFFF1660: romout <= 16'h4279;
32'hFFFF1662: romout <= 16'hFFDC;
32'hFFFF1664: romout <= 16'h0002;
32'hFFFF1666: romout <= 16'h0241;
32'hFFFF1668: romout <= 16'h00FF;
32'hFFFF166A: romout <= 16'h0C38;
32'hFFFF166C: romout <= 16'h0000;
32'hFFFF166E: romout <= 16'h041C;
32'hFFFF1670: romout <= 16'h670C;
32'hFFFF1672: romout <= 16'h0C01;
32'hFFFF1674: romout <= 16'h000D;
32'hFFFF1676: romout <= 16'h6774;
32'hFFFF1678: romout <= 16'h4EB9;
32'hFFFF167A: romout <= 16'hFFFF;
32'hFFFF167C: romout <= 16'h1732;
32'hFFFF167E: romout <= 16'h4E75;
32'hFFFF1680: romout <= 16'h3F01;
32'hFFFF1682: romout <= 16'h3239;
32'hFFFF1684: romout <= 16'hFFDC;
32'hFFFF1686: romout <= 16'h0000;
32'hFFFF1688: romout <= 16'h6A08;
32'hFFFF168A: romout <= 16'h321F;
32'hFFFF168C: romout <= 16'h003C;
32'hFFFF168E: romout <= 16'h0001;
32'hFFFF1690: romout <= 16'h4E75;
32'hFFFF1692: romout <= 16'h321F;
32'hFFFF1694: romout <= 16'h023C;
32'hFFFF1696: romout <= 16'h00FE;
32'hFFFF1698: romout <= 16'h4E75;
32'hFFFF169A: romout <= 16'h0839;
32'hFFFF169C: romout <= 16'h0000;
32'hFFFF169E: romout <= 16'hFFDC;
32'hFFFF16A0: romout <= 16'h0A01;
32'hFFFF16A2: romout <= 16'h6706;
32'hFFFF16A4: romout <= 16'h003C;
32'hFFFF16A6: romout <= 16'h0001;
32'hFFFF16A8: romout <= 16'h4E75;
32'hFFFF16AA: romout <= 16'h023C;
32'hFFFF16AC: romout <= 16'h00FE;
32'hFFFF16AE: romout <= 16'h4E75;
32'hFFFF16B0: romout <= 16'h4280;
32'hFFFF16B2: romout <= 16'h3039;
32'hFFFF16B4: romout <= 16'hFFDC;
32'hFFFF16B6: romout <= 16'h0000;
32'hFFFF16B8: romout <= 16'h6A12;
32'hFFFF16BA: romout <= 16'h0240;
32'hFFFF16BC: romout <= 16'h00FF;
32'hFFFF16BE: romout <= 16'h4279;
32'hFFFF16C0: romout <= 16'hFFDC;
32'hFFFF16C2: romout <= 16'h0002;
32'hFFFF16C4: romout <= 16'h41F8;
32'hFFFF16C6: romout <= 16'h0460;
32'hFFFF16C8: romout <= 16'h2080;
32'hFFFF16CA: romout <= 16'h4E75;
32'hFFFF16CC: romout <= 16'h41F8;
32'hFFFF16CE: romout <= 16'h0460;
32'hFFFF16D0: romout <= 16'h4290;
32'hFFFF16D2: romout <= 16'h4E75;
32'hFFFF16D4: romout <= 16'h6100;
32'hFFFF16D6: romout <= 16'h005C;
32'hFFFF16D8: romout <= 16'h4E75;
32'hFFFF16DA: romout <= 16'h3239;
32'hFFFF16DC: romout <= 16'hFFDC;
32'hFFFF16DE: romout <= 16'h0000;
32'hFFFF16E0: romout <= 16'h6A06;
32'hFFFF16E2: romout <= 16'h123C;
32'hFFFF16E4: romout <= 16'h0001;
32'hFFFF16E6: romout <= 16'h4E75;
32'hFFFF16E8: romout <= 16'h4201;
32'hFFFF16EA: romout <= 16'h4E75;
32'hFFFF16EC: romout <= 16'h2F01;
32'hFFFF16EE: romout <= 16'h123C;
32'hFFFF16F0: romout <= 16'h000D;
32'hFFFF16F2: romout <= 16'h4EB9;
32'hFFFF16F4: romout <= 16'hFFFF;
32'hFFFF16F6: romout <= 16'h1732;
32'hFFFF16F8: romout <= 16'h123C;
32'hFFFF16FA: romout <= 16'h000A;
32'hFFFF16FC: romout <= 16'h4EB9;
32'hFFFF16FE: romout <= 16'hFFFF;
32'hFFFF1700: romout <= 16'h1732;
32'hFFFF1702: romout <= 16'h221F;
32'hFFFF1704: romout <= 16'h4E75;
32'hFFFF1706: romout <= 16'h3038;
32'hFFFF1708: romout <= 16'h0418;
32'hFFFF170A: romout <= 16'h0240;
32'hFFFF170C: romout <= 16'h007F;
32'hFFFF170E: romout <= 16'hC0F9;
32'hFFFF1710: romout <= 16'hFFDA;
32'hFFFF1712: romout <= 16'h0000;
32'hFFFF1714: romout <= 16'h3438;
32'hFFFF1716: romout <= 16'h041A;
32'hFFFF1718: romout <= 16'h0242;
32'hFFFF171A: romout <= 16'h00FF;
32'hFFFF171C: romout <= 16'hD042;
32'hFFFF171E: romout <= 16'hE340;
32'hFFFF1720: romout <= 16'h0680;
32'hFFFF1722: romout <= 16'hFFD0;
32'hFFFF1724: romout <= 16'h0000;
32'hFFFF1726: romout <= 16'h2040;
32'hFFFF1728: romout <= 16'hE288;
32'hFFFF172A: romout <= 16'h33C0;
32'hFFFF172C: romout <= 16'hFFDA;
32'hFFFF172E: romout <= 16'h0016;
32'hFFFF1730: romout <= 16'h4E75;
32'hFFFF1732: romout <= 16'h0C01;
32'hFFFF1734: romout <= 16'h000D;
32'hFFFF1736: romout <= 16'h6606;
32'hFFFF1738: romout <= 16'h4278;
32'hFFFF173A: romout <= 16'h041A;
32'hFFFF173C: romout <= 16'h4E75;
32'hFFFF173E: romout <= 16'h0C01;
32'hFFFF1740: romout <= 16'h0091;
32'hFFFF1742: romout <= 16'h660E;
32'hFFFF1744: romout <= 16'h0C78;
32'hFFFF1746: romout <= 16'h0033;
32'hFFFF1748: romout <= 16'h041A;
32'hFFFF174A: romout <= 16'h6704;
32'hFFFF174C: romout <= 16'h5278;
32'hFFFF174E: romout <= 16'h041A;
32'hFFFF1750: romout <= 16'h4E75;
32'hFFFF1752: romout <= 16'h0C01;
32'hFFFF1754: romout <= 16'h0090;
32'hFFFF1756: romout <= 16'h660E;
32'hFFFF1758: romout <= 16'h0C78;
32'hFFFF175A: romout <= 16'h0000;
32'hFFFF175C: romout <= 16'h0418;
32'hFFFF175E: romout <= 16'h67F0;
32'hFFFF1760: romout <= 16'h5378;
32'hFFFF1762: romout <= 16'h0418;
32'hFFFF1764: romout <= 16'h4E75;
32'hFFFF1766: romout <= 16'h0C01;
32'hFFFF1768: romout <= 16'h0093;
32'hFFFF176A: romout <= 16'h660E;
32'hFFFF176C: romout <= 16'h0C78;
32'hFFFF176E: romout <= 16'h0000;
32'hFFFF1770: romout <= 16'h041A;
32'hFFFF1772: romout <= 16'h67DC;
32'hFFFF1774: romout <= 16'h5378;
32'hFFFF1776: romout <= 16'h041A;
32'hFFFF1778: romout <= 16'h4E75;
32'hFFFF177A: romout <= 16'h0C01;
32'hFFFF177C: romout <= 16'h0092;
32'hFFFF177E: romout <= 16'h660E;
32'hFFFF1780: romout <= 16'h0C78;
32'hFFFF1782: romout <= 16'h001E;
32'hFFFF1784: romout <= 16'h0418;
32'hFFFF1786: romout <= 16'h67C8;
32'hFFFF1788: romout <= 16'h5278;
32'hFFFF178A: romout <= 16'h0418;
32'hFFFF178C: romout <= 16'h4E75;
32'hFFFF178E: romout <= 16'h0C01;
32'hFFFF1790: romout <= 16'h0094;
32'hFFFF1792: romout <= 16'h6614;
32'hFFFF1794: romout <= 16'h0C78;
32'hFFFF1796: romout <= 16'h0000;
32'hFFFF1798: romout <= 16'h041A;
32'hFFFF179A: romout <= 16'h6706;
32'hFFFF179C: romout <= 16'h4278;
32'hFFFF179E: romout <= 16'h041A;
32'hFFFF17A0: romout <= 16'h4E75;
32'hFFFF17A2: romout <= 16'h4278;
32'hFFFF17A4: romout <= 16'h0418;
32'hFFFF17A6: romout <= 16'h4E75;
32'hFFFF17A8: romout <= 16'h48E7;
32'hFFFF17AA: romout <= 16'hE080;
32'hFFFF17AC: romout <= 16'h0C01;
32'hFFFF17AE: romout <= 16'h0099;
32'hFFFF17B0: romout <= 16'h660A;
32'hFFFF17B2: romout <= 16'h6100;
32'hFFFF17B4: romout <= 16'hFF52;
32'hFFFF17B6: romout <= 16'h3038;
32'hFFFF17B8: romout <= 16'h041A;
32'hFFFF17BA: romout <= 16'h601A;
32'hFFFF17BC: romout <= 16'h0C01;
32'hFFFF17BE: romout <= 16'h0008;
32'hFFFF17C0: romout <= 16'h662C;
32'hFFFF17C2: romout <= 16'h0C78;
32'hFFFF17C4: romout <= 16'h0000;
32'hFFFF17C6: romout <= 16'h041A;
32'hFFFF17C8: romout <= 16'h6742;
32'hFFFF17CA: romout <= 16'h5378;
32'hFFFF17CC: romout <= 16'h041A;
32'hFFFF17CE: romout <= 16'h6100;
32'hFFFF17D0: romout <= 16'hFF36;
32'hFFFF17D2: romout <= 16'h3038;
32'hFFFF17D4: romout <= 16'h041A;
32'hFFFF17D6: romout <= 16'h30E8;
32'hFFFF17D8: romout <= 16'h0002;
32'hFFFF17DA: romout <= 16'h5240;
32'hFFFF17DC: romout <= 16'hB079;
32'hFFFF17DE: romout <= 16'hFFDA;
32'hFFFF17E0: romout <= 16'h0000;
32'hFFFF17E2: romout <= 16'h65F2;
32'hFFFF17E4: romout <= 16'h303C;
32'hFFFF17E6: romout <= 16'h0020;
32'hFFFF17E8: romout <= 16'h3140;
32'hFFFF17EA: romout <= 16'hFFFE;
32'hFFFF17EC: romout <= 16'h601E;
32'hFFFF17EE: romout <= 16'h0C01;
32'hFFFF17F0: romout <= 16'h000A;
32'hFFFF17F2: romout <= 16'h6714;
32'hFFFF17F4: romout <= 16'h6100;
32'hFFFF17F6: romout <= 16'hFF10;
32'hFFFF17F8: romout <= 16'h6100;
32'hFFFF17FA: romout <= 16'h01B8;
32'hFFFF17FC: romout <= 16'h30C1;
32'hFFFF17FE: romout <= 16'h6100;
32'hFFFF1800: romout <= 16'h0012;
32'hFFFF1802: romout <= 16'h4CDF;
32'hFFFF1804: romout <= 16'h0107;
32'hFFFF1806: romout <= 16'h4E75;
32'hFFFF1808: romout <= 16'h6100;
32'hFFFF180A: romout <= 16'h0022;
32'hFFFF180C: romout <= 16'h4CDF;
32'hFFFF180E: romout <= 16'h0107;
32'hFFFF1810: romout <= 16'h4E75;
32'hFFFF1812: romout <= 16'h5279;
32'hFFFF1814: romout <= 16'hFFDA;
32'hFFFF1816: romout <= 16'h0016;
32'hFFFF1818: romout <= 16'h5278;
32'hFFFF181A: romout <= 16'h041A;
32'hFFFF181C: romout <= 16'h3039;
32'hFFFF181E: romout <= 16'hFFDA;
32'hFFFF1820: romout <= 16'h0000;
32'hFFFF1822: romout <= 16'hB078;
32'hFFFF1824: romout <= 16'h041A;
32'hFFFF1826: romout <= 16'h642E;
32'hFFFF1828: romout <= 16'h4278;
32'hFFFF182A: romout <= 16'h041A;
32'hFFFF182C: romout <= 16'h5278;
32'hFFFF182E: romout <= 16'h0418;
32'hFFFF1830: romout <= 16'h3039;
32'hFFFF1832: romout <= 16'hFFDA;
32'hFFFF1834: romout <= 16'h0002;
32'hFFFF1836: romout <= 16'hB078;
32'hFFFF1838: romout <= 16'h0418;
32'hFFFF183A: romout <= 16'h621A;
32'hFFFF183C: romout <= 16'h3039;
32'hFFFF183E: romout <= 16'hFFDA;
32'hFFFF1840: romout <= 16'h0002;
32'hFFFF1842: romout <= 16'h31C0;
32'hFFFF1844: romout <= 16'h0418;
32'hFFFF1846: romout <= 16'h5378;
32'hFFFF1848: romout <= 16'h0418;
32'hFFFF184A: romout <= 16'hE340;
32'hFFFF184C: romout <= 16'h9179;
32'hFFFF184E: romout <= 16'hFFDA;
32'hFFFF1850: romout <= 16'h0016;
32'hFFFF1852: romout <= 16'h6100;
32'hFFFF1854: romout <= 16'h00CE;
32'hFFFF1856: romout <= 16'h4E75;
32'hFFFF1858: romout <= 16'h48E7;
32'hFFFF185A: romout <= 16'hC040;
32'hFFFF185C: romout <= 16'h4281;
32'hFFFF185E: romout <= 16'h1219;
32'hFFFF1860: romout <= 16'h0C01;
32'hFFFF1862: romout <= 16'h0000;
32'hFFFF1864: romout <= 16'h6706;
32'hFFFF1866: romout <= 16'h6100;
32'hFFFF1868: romout <= 16'hFECA;
32'hFFFF186A: romout <= 16'h60F0;
32'hFFFF186C: romout <= 16'h4CDF;
32'hFFFF186E: romout <= 16'h0203;
32'hFFFF1870: romout <= 16'h4E75;
32'hFFFF1872: romout <= 16'h6100;
32'hFFFF1874: romout <= 16'hFFE4;
32'hFFFF1876: romout <= 16'h6000;
32'hFFFF1878: romout <= 16'hFE74;
32'hFFFF187A: romout <= 16'h48E7;
32'hFFFF187C: romout <= 16'hC040;
32'hFFFF187E: romout <= 16'h0241;
32'hFFFF1880: romout <= 16'h00FF;
32'hFFFF1882: romout <= 16'h2001;
32'hFFFF1884: romout <= 16'h1219;
32'hFFFF1886: romout <= 16'h0C01;
32'hFFFF1888: romout <= 16'h0000;
32'hFFFF188A: romout <= 16'h6708;
32'hFFFF188C: romout <= 16'h6100;
32'hFFFF188E: romout <= 16'hFEA4;
32'hFFFF1890: romout <= 16'h57C8;
32'hFFFF1892: romout <= 16'hFFF2;
32'hFFFF1894: romout <= 16'h4CDF;
32'hFFFF1896: romout <= 16'h0203;
32'hFFFF1898: romout <= 16'h4E75;
32'hFFFF189A: romout <= 16'h6100;
32'hFFFF189C: romout <= 16'hFFDE;
32'hFFFF189E: romout <= 16'h6000;
32'hFFFF18A0: romout <= 16'hFE4C;
32'hFFFF18A2: romout <= 16'h0C41;
32'hFFFF18A4: romout <= 16'h00FF;
32'hFFFF18A6: romout <= 16'h670E;
32'hFFFF18A8: romout <= 16'h0C41;
32'hFFFF18AA: romout <= 16'hFF00;
32'hFFFF18AC: romout <= 16'h6714;
32'hFFFF18AE: romout <= 16'h4EB9;
32'hFFFF18B0: romout <= 16'hFFFF;
32'hFFFF18B2: romout <= 16'h18E8;
32'hFFFF18B4: romout <= 16'h4E75;
32'hFFFF18B6: romout <= 16'h3238;
32'hFFFF18B8: romout <= 16'h041A;
32'hFFFF18BA: romout <= 16'hE141;
32'hFFFF18BC: romout <= 16'h1238;
32'hFFFF18BE: romout <= 16'h0418;
32'hFFFF18C0: romout <= 16'h4E75;
32'hFFFF18C2: romout <= 16'h2F01;
32'hFFFF18C4: romout <= 16'h11C1;
32'hFFFF18C6: romout <= 16'h0418;
32'hFFFF18C8: romout <= 16'hE049;
32'hFFFF18CA: romout <= 16'h31C1;
32'hFFFF18CC: romout <= 16'h041A;
32'hFFFF18CE: romout <= 16'h3238;
32'hFFFF18D0: romout <= 16'h0418;
32'hFFFF18D2: romout <= 16'hC2F9;
32'hFFFF18D4: romout <= 16'hFFDA;
32'hFFFF18D6: romout <= 16'h0000;
32'hFFFF18D8: romout <= 16'hD278;
32'hFFFF18DA: romout <= 16'h041A;
32'hFFFF18DC: romout <= 16'hE341;
32'hFFFF18DE: romout <= 16'h33C1;
32'hFFFF18E0: romout <= 16'hFFDA;
32'hFFFF18E2: romout <= 16'h0016;
32'hFFFF18E4: romout <= 16'h221F;
32'hFFFF18E6: romout <= 16'h4E75;
32'hFFFF18E8: romout <= 16'h3239;
32'hFFFF18EA: romout <= 16'hFFDA;
32'hFFFF18EC: romout <= 16'h0000;
32'hFFFF18EE: romout <= 16'hC2F9;
32'hFFFF18F0: romout <= 16'hFFDA;
32'hFFFF18F2: romout <= 16'h0002;
32'hFFFF18F4: romout <= 16'h303C;
32'hFFFF18F6: romout <= 16'h0020;
32'hFFFF18F8: romout <= 16'h207C;
32'hFFFF18FA: romout <= 16'hFFD0;
32'hFFFF18FC: romout <= 16'h0000;
32'hFFFF18FE: romout <= 16'h30C0;
32'hFFFF1900: romout <= 16'h57C9;
32'hFFFF1902: romout <= 16'hFFFC;
32'hFFFF1904: romout <= 16'h3239;
32'hFFFF1906: romout <= 16'hFFDA;
32'hFFFF1908: romout <= 16'h0000;
32'hFFFF190A: romout <= 16'hC2F9;
32'hFFFF190C: romout <= 16'hFFDA;
32'hFFFF190E: romout <= 16'h0002;
32'hFFFF1910: romout <= 16'h3038;
32'hFFFF1912: romout <= 16'h0414;
32'hFFFF1914: romout <= 16'h207C;
32'hFFFF1916: romout <= 16'hFFD1;
32'hFFFF1918: romout <= 16'h0000;
32'hFFFF191A: romout <= 16'h30C0;
32'hFFFF191C: romout <= 16'h57C9;
32'hFFFF191E: romout <= 16'hFFFC;
32'hFFFF1920: romout <= 16'h4E75;
32'hFFFF1922: romout <= 16'h48E7;
32'hFFFF1924: romout <= 16'hE080;
32'hFFFF1926: romout <= 16'h3039;
32'hFFFF1928: romout <= 16'hFFDA;
32'hFFFF192A: romout <= 16'h0000;
32'hFFFF192C: romout <= 16'hC0F9;
32'hFFFF192E: romout <= 16'hFFDA;
32'hFFFF1930: romout <= 16'h0002;
32'hFFFF1932: romout <= 16'h9079;
32'hFFFF1934: romout <= 16'hFFDA;
32'hFFFF1936: romout <= 16'h0000;
32'hFFFF1938: romout <= 16'h41F9;
32'hFFFF193A: romout <= 16'hFFD0;
32'hFFFF193C: romout <= 16'h0000;
32'hFFFF193E: romout <= 16'h3439;
32'hFFFF1940: romout <= 16'hFFDA;
32'hFFFF1942: romout <= 16'h0000;
32'hFFFF1944: romout <= 16'hE342;
32'hFFFF1946: romout <= 16'h30F0;
32'hFFFF1948: romout <= 16'h2000;
32'hFFFF194A: romout <= 16'h57C8;
32'hFFFF194C: romout <= 16'hFFFA;
32'hFFFF194E: romout <= 16'h3239;
32'hFFFF1950: romout <= 16'hFFDA;
32'hFFFF1952: romout <= 16'h0002;
32'hFFFF1954: romout <= 16'h5341;
32'hFFFF1956: romout <= 16'h4EB9;
32'hFFFF1958: romout <= 16'hFFFF;
32'hFFFF195A: romout <= 16'h1962;
32'hFFFF195C: romout <= 16'h4CDF;
32'hFFFF195E: romout <= 16'h0107;
32'hFFFF1960: romout <= 16'h4E75;
32'hFFFF1962: romout <= 16'h48E7;
32'hFFFF1964: romout <= 16'h8080;
32'hFFFF1966: romout <= 16'h3039;
32'hFFFF1968: romout <= 16'hFFDA;
32'hFFFF196A: romout <= 16'h0000;
32'hFFFF196C: romout <= 16'hC0C1;
32'hFFFF196E: romout <= 16'hE340;
32'hFFFF1970: romout <= 16'h0680;
32'hFFFF1972: romout <= 16'hFFD0;
32'hFFFF1974: romout <= 16'h0000;
32'hFFFF1976: romout <= 16'h2040;
32'hFFFF1978: romout <= 16'h3039;
32'hFFFF197A: romout <= 16'hFFDA;
32'hFFFF197C: romout <= 16'h0000;
32'hFFFF197E: romout <= 16'h30FC;
32'hFFFF1980: romout <= 16'h0020;
32'hFFFF1982: romout <= 16'h57C8;
32'hFFFF1984: romout <= 16'hFFFA;
32'hFFFF1986: romout <= 16'h4CDF;
32'hFFFF1988: romout <= 16'h0101;
32'hFFFF198A: romout <= 16'h4E75;
32'hFFFF198C: romout <= 16'h48E7;
32'hFFFF198E: romout <= 16'hF800;
32'hFFFF1990: romout <= 16'h4284;
32'hFFFF1992: romout <= 16'h1802;
32'hFFFF1994: romout <= 16'h4EB9;
32'hFFFF1996: romout <= 16'hFFFF;
32'hFFFF1998: romout <= 16'h2F7A;
32'hFFFF199A: romout <= 16'h4CDF;
32'hFFFF199C: romout <= 16'h001F;
32'hFFFF199E: romout <= 16'h4E75;
32'hFFFF19A0: romout <= 16'h48E7;
32'hFFFF19A2: romout <= 16'hF800;
32'hFFFF19A4: romout <= 16'h4284;
32'hFFFF19A6: romout <= 16'h4EB9;
32'hFFFF19A8: romout <= 16'hFFFF;
32'hFFFF19AA: romout <= 16'h2F7A;
32'hFFFF19AC: romout <= 16'h4CDF;
32'hFFFF19AE: romout <= 16'h001F;
32'hFFFF19B0: romout <= 16'h4E75;
32'hFFFF19B2: romout <= 16'h0241;
32'hFFFF19B4: romout <= 16'h00FF;
32'hFFFF19B6: romout <= 16'h0C01;
32'hFFFF19B8: romout <= 16'h0041;
32'hFFFF19BA: romout <= 16'h6516;
32'hFFFF19BC: romout <= 16'h0C01;
32'hFFFF19BE: romout <= 16'h005A;
32'hFFFF19C0: romout <= 16'h6310;
32'hFFFF19C2: romout <= 16'h0C01;
32'hFFFF19C4: romout <= 16'h007A;
32'hFFFF19C6: romout <= 16'h620A;
32'hFFFF19C8: romout <= 16'h0C01;
32'hFFFF19CA: romout <= 16'h0061;
32'hFFFF19CC: romout <= 16'h6504;
32'hFFFF19CE: romout <= 16'h0401;
32'hFFFF19D0: romout <= 16'h0060;
32'hFFFF19D2: romout <= 16'h0041;
32'hFFFF19D4: romout <= 16'h0100;
32'hFFFF19D6: romout <= 16'h4E75;
32'hFFFF19D8: romout <= 16'h0201;
32'hFFFF19DA: romout <= 16'h00FF;
32'hFFFF19DC: romout <= 16'h0C01;
32'hFFFF19DE: romout <= 16'h001A;
32'hFFFF19E0: romout <= 16'h6204;
32'hFFFF19E2: romout <= 16'h0601;
32'hFFFF19E4: romout <= 16'h0060;
32'hFFFF19E6: romout <= 16'h4E75;
32'hFFFF19E8: romout <= 16'h3F01;
32'hFFFF19EA: romout <= 16'h0201;
32'hFFFF19EC: romout <= 16'h000F;
32'hFFFF19EE: romout <= 16'h0601;
32'hFFFF19F0: romout <= 16'h0030;
32'hFFFF19F2: romout <= 16'h0C01;
32'hFFFF19F4: romout <= 16'h0039;
32'hFFFF19F6: romout <= 16'h6302;
32'hFFFF19F8: romout <= 16'h5E01;
32'hFFFF19FA: romout <= 16'h6100;
32'hFFFF19FC: romout <= 16'hFD36;
32'hFFFF19FE: romout <= 16'h321F;
32'hFFFF1A00: romout <= 16'h4E75;
32'hFFFF1A02: romout <= 16'h3F01;
32'hFFFF1A04: romout <= 16'hE819;
32'hFFFF1A06: romout <= 16'h6100;
32'hFFFF1A08: romout <= 16'hFFE0;
32'hFFFF1A0A: romout <= 16'hE919;
32'hFFFF1A0C: romout <= 16'h6100;
32'hFFFF1A0E: romout <= 16'hFFDA;
32'hFFFF1A10: romout <= 16'h321F;
32'hFFFF1A12: romout <= 16'h4E75;
32'hFFFF1A14: romout <= 16'hE199;
32'hFFFF1A16: romout <= 16'h6100;
32'hFFFF1A18: romout <= 16'hFFEA;
32'hFFFF1A1A: romout <= 16'hE199;
32'hFFFF1A1C: romout <= 16'h6100;
32'hFFFF1A1E: romout <= 16'hFFE4;
32'hFFFF1A20: romout <= 16'hE199;
32'hFFFF1A22: romout <= 16'h6100;
32'hFFFF1A24: romout <= 16'hFFDE;
32'hFFFF1A26: romout <= 16'hE199;
32'hFFFF1A28: romout <= 16'h6100;
32'hFFFF1A2A: romout <= 16'hFFD8;
32'hFFFF1A2C: romout <= 16'h4E75;
32'hFFFF1A2E: romout <= 16'h123C;
32'hFFFF1A30: romout <= 16'h003A;
32'hFFFF1A32: romout <= 16'h4EB9;
32'hFFFF1A34: romout <= 16'hFFFF;
32'hFFFF1A36: romout <= 16'h1732;
32'hFFFF1A38: romout <= 16'h2208;
32'hFFFF1A3A: romout <= 16'h4EB9;
32'hFFFF1A3C: romout <= 16'hFFFF;
32'hFFFF1A3E: romout <= 16'h1A14;
32'hFFFF1A40: romout <= 16'h7407;
32'hFFFF1A42: romout <= 16'h123C;
32'hFFFF1A44: romout <= 16'h0020;
32'hFFFF1A46: romout <= 16'h4EB9;
32'hFFFF1A48: romout <= 16'hFFFF;
32'hFFFF1A4A: romout <= 16'h1732;
32'hFFFF1A4C: romout <= 16'h1218;
32'hFFFF1A4E: romout <= 16'h4EB9;
32'hFFFF1A50: romout <= 16'hFFFF;
32'hFFFF1A52: romout <= 16'h1A02;
32'hFFFF1A54: romout <= 16'h51CA;
32'hFFFF1A56: romout <= 16'hFFEC;
32'hFFFF1A58: romout <= 16'h4EF9;
32'hFFFF1A5A: romout <= 16'hFFFF;
32'hFFFF1A5C: romout <= 16'h16EC;
32'hFFFF1A5E: romout <= 16'h4E55;
32'hFFFF1A60: romout <= 16'hFFE8;
32'hFFFF1A62: romout <= 16'h41ED;
32'hFFFF1A64: romout <= 16'hFFFA;
32'hFFFF1A66: romout <= 16'h43ED;
32'hFFFF1A68: romout <= 16'hFFFC;
32'hFFFF1A6A: romout <= 16'h3B7C;
32'hFFFF1A6C: romout <= 16'h0000;
32'hFFFF1A6E: romout <= 16'hFFFA;
32'hFFFF1A70: romout <= 16'h3B7C;
32'hFFFF1A72: romout <= 16'h0002;
32'hFFFF1A74: romout <= 16'hFFF8;
32'hFFFF1A76: romout <= 16'h7048;
32'hFFFF1A78: romout <= 16'h4E41;
32'hFFFF1A7A: romout <= 16'h4278;
32'hFFFF1A7C: romout <= 16'h041C;
32'hFFFF1A7E: romout <= 16'h6100;
32'hFFFF1A80: romout <= 16'hFC6C;
32'hFFFF1A82: romout <= 16'h123C;
32'hFFFF1A84: romout <= 16'h0024;
32'hFFFF1A86: romout <= 16'h6100;
32'hFFFF1A88: romout <= 16'hFCAA;
32'hFFFF1A8A: romout <= 16'h6100;
32'hFFFF1A8C: romout <= 16'hFBCC;
32'hFFFF1A8E: romout <= 16'h0C01;
32'hFFFF1A90: romout <= 16'h000D;
32'hFFFF1A92: romout <= 16'h6706;
32'hFFFF1A94: romout <= 16'h6100;
32'hFFFF1A96: romout <= 16'hFC9C;
32'hFFFF1A98: romout <= 16'h60F0;
32'hFFFF1A9A: romout <= 16'h4278;
32'hFFFF1A9C: romout <= 16'h041A;
32'hFFFF1A9E: romout <= 16'h6100;
32'hFFFF1AA0: romout <= 16'hFC66;
32'hFFFF1AA2: romout <= 16'h3218;
32'hFFFF1AA4: romout <= 16'h6100;
32'hFFFF1AA6: romout <= 16'hFF32;
32'hFFFF1AA8: romout <= 16'h0C01;
32'hFFFF1AAA: romout <= 16'h0024;
32'hFFFF1AAC: romout <= 16'h6606;
32'hFFFF1AAE: romout <= 16'h3218;
32'hFFFF1AB0: romout <= 16'h6100;
32'hFFFF1AB2: romout <= 16'hFF26;
32'hFFFF1AB4: romout <= 16'h0C01;
32'hFFFF1AB6: romout <= 16'h003A;
32'hFFFF1AB8: romout <= 16'h6700;
32'hFFFF1ABA: romout <= 16'h00FC;
32'hFFFF1ABC: romout <= 16'h0C01;
32'hFFFF1ABE: romout <= 16'h0044;
32'hFFFF1AC0: romout <= 16'h6700;
32'hFFFF1AC2: romout <= 16'h0162;
32'hFFFF1AC4: romout <= 16'h0C01;
32'hFFFF1AC6: romout <= 16'h0042;
32'hFFFF1AC8: romout <= 16'h6700;
32'hFFFF1ACA: romout <= 16'h0936;
32'hFFFF1ACC: romout <= 16'h0C01;
32'hFFFF1ACE: romout <= 16'h004A;
32'hFFFF1AD0: romout <= 16'h6700;
32'hFFFF1AD2: romout <= 16'h0142;
32'hFFFF1AD4: romout <= 16'h0C01;
32'hFFFF1AD6: romout <= 16'h004C;
32'hFFFF1AD8: romout <= 16'h6700;
32'hFFFF1ADA: romout <= 16'h01EE;
32'hFFFF1ADC: romout <= 16'h0C01;
32'hFFFF1ADE: romout <= 16'h003F;
32'hFFFF1AE0: romout <= 16'h672A;
32'hFFFF1AE2: romout <= 16'h0C01;
32'hFFFF1AE4: romout <= 16'h0043;
32'hFFFF1AE6: romout <= 16'h6702;
32'hFFFF1AE8: romout <= 16'h6090;
32'hFFFF1AEA: romout <= 16'h3218;
32'hFFFF1AEC: romout <= 16'h6100;
32'hFFFF1AEE: romout <= 16'hFEEA;
32'hFFFF1AF0: romout <= 16'h0C01;
32'hFFFF1AF2: romout <= 16'h004C;
32'hFFFF1AF4: romout <= 16'h6684;
32'hFFFF1AF6: romout <= 16'h3218;
32'hFFFF1AF8: romout <= 16'h6100;
32'hFFFF1AFA: romout <= 16'hFEDE;
32'hFFFF1AFC: romout <= 16'h0C01;
32'hFFFF1AFE: romout <= 16'h0053;
32'hFFFF1B00: romout <= 16'h6600;
32'hFFFF1B02: romout <= 16'hFF78;
32'hFFFF1B04: romout <= 16'h6100;
32'hFFFF1B06: romout <= 16'hFDE2;
32'hFFFF1B08: romout <= 16'h6000;
32'hFFFF1B0A: romout <= 16'hFF70;
32'hFFFF1B0C: romout <= 16'h43F9;
32'hFFFF1B0E: romout <= 16'hFFFF;
32'hFFFF1B10: romout <= 16'h1B1C;
32'hFFFF1B12: romout <= 16'h4EB9;
32'hFFFF1B14: romout <= 16'hFFFF;
32'hFFFF1B16: romout <= 16'h1858;
32'hFFFF1B18: romout <= 16'h6000;
32'hFFFF1B1A: romout <= 16'hFF60;
32'hFFFF1B1C: romout <= 16'h3F20;
32'hFFFF1B1E: romout <= 16'h3D20;
32'hFFFF1B20: romout <= 16'h4469;
32'hFFFF1B22: romout <= 16'h7370;
32'hFFFF1B24: romout <= 16'h6C61;
32'hFFFF1B26: romout <= 16'h7920;
32'hFFFF1B28: romout <= 16'h6865;
32'hFFFF1B2A: romout <= 16'h6C70;
32'hFFFF1B2C: romout <= 16'h0D0A;
32'hFFFF1B2E: romout <= 16'h434C;
32'hFFFF1B30: romout <= 16'h5320;
32'hFFFF1B32: romout <= 16'h3D20;
32'hFFFF1B34: romout <= 16'h636C;
32'hFFFF1B36: romout <= 16'h6561;
32'hFFFF1B38: romout <= 16'h7220;
32'hFFFF1B3A: romout <= 16'h7363;
32'hFFFF1B3C: romout <= 16'h7265;
32'hFFFF1B3E: romout <= 16'h656E;
32'hFFFF1B40: romout <= 16'h0D0A;
32'hFFFF1B42: romout <= 16'h3A20;
32'hFFFF1B44: romout <= 16'h3D20;
32'hFFFF1B46: romout <= 16'h4564;
32'hFFFF1B48: romout <= 16'h6974;
32'hFFFF1B4A: romout <= 16'h206D;
32'hFFFF1B4C: romout <= 16'h656D;
32'hFFFF1B4E: romout <= 16'h6F72;
32'hFFFF1B50: romout <= 16'h7920;
32'hFFFF1B52: romout <= 16'h6279;
32'hFFFF1B54: romout <= 16'h7465;
32'hFFFF1B56: romout <= 16'h730D;
32'hFFFF1B58: romout <= 16'h0A4C;
32'hFFFF1B5A: romout <= 16'h203D;
32'hFFFF1B5C: romout <= 16'h204C;
32'hFFFF1B5E: romout <= 16'h6F61;
32'hFFFF1B60: romout <= 16'h6420;
32'hFFFF1B62: romout <= 16'h5331;
32'hFFFF1B64: romout <= 16'h3920;
32'hFFFF1B66: romout <= 16'h6669;
32'hFFFF1B68: romout <= 16'h6C65;
32'hFFFF1B6A: romout <= 16'h0D0A;
32'hFFFF1B6C: romout <= 16'h4420;
32'hFFFF1B6E: romout <= 16'h3D20;
32'hFFFF1B70: romout <= 16'h4475;
32'hFFFF1B72: romout <= 16'h6D70;
32'hFFFF1B74: romout <= 16'h206D;
32'hFFFF1B76: romout <= 16'h656D;
32'hFFFF1B78: romout <= 16'h6F72;
32'hFFFF1B7A: romout <= 16'h790D;
32'hFFFF1B7C: romout <= 16'h0A42;
32'hFFFF1B7E: romout <= 16'h203D;
32'hFFFF1B80: romout <= 16'h2073;
32'hFFFF1B82: romout <= 16'h7461;
32'hFFFF1B84: romout <= 16'h7274;
32'hFFFF1B86: romout <= 16'h2074;
32'hFFFF1B88: romout <= 16'h696E;
32'hFFFF1B8A: romout <= 16'h7920;
32'hFFFF1B8C: romout <= 16'h6261;
32'hFFFF1B8E: romout <= 16'h7369;
32'hFFFF1B90: romout <= 16'h630D;
32'hFFFF1B92: romout <= 16'h0A4A;
32'hFFFF1B94: romout <= 16'h203D;
32'hFFFF1B96: romout <= 16'h204A;
32'hFFFF1B98: romout <= 16'h756D;
32'hFFFF1B9A: romout <= 16'h7020;
32'hFFFF1B9C: romout <= 16'h746F;
32'hFFFF1B9E: romout <= 16'h2063;
32'hFFFF1BA0: romout <= 16'h6F64;
32'hFFFF1BA2: romout <= 16'h650D;
32'hFFFF1BA4: romout <= 16'h0A00;
32'hFFFF1BA6: romout <= 16'h3218;
32'hFFFF1BA8: romout <= 16'h6100;
32'hFFFF1BAA: romout <= 16'hFE2E;
32'hFFFF1BAC: romout <= 16'h0C01;
32'hFFFF1BAE: romout <= 16'h0020;
32'hFFFF1BB0: romout <= 16'h67F4;
32'hFFFF1BB2: romout <= 16'h5588;
32'hFFFF1BB4: romout <= 16'h4E75;
32'hFFFF1BB6: romout <= 16'h6100;
32'hFFFF1BB8: romout <= 16'hFFEE;
32'hFFFF1BBA: romout <= 16'h6100;
32'hFFFF1BBC: romout <= 16'h009C;
32'hFFFF1BBE: romout <= 16'h2241;
32'hFFFF1BC0: romout <= 16'h6100;
32'hFFFF1BC2: romout <= 16'hFFE4;
32'hFFFF1BC4: romout <= 16'h6100;
32'hFFFF1BC6: romout <= 16'h0092;
32'hFFFF1BC8: romout <= 16'h12C1;
32'hFFFF1BCA: romout <= 16'h6100;
32'hFFFF1BCC: romout <= 16'hFFDA;
32'hFFFF1BCE: romout <= 16'h6100;
32'hFFFF1BD0: romout <= 16'h0088;
32'hFFFF1BD2: romout <= 16'h12C1;
32'hFFFF1BD4: romout <= 16'h6100;
32'hFFFF1BD6: romout <= 16'hFFD0;
32'hFFFF1BD8: romout <= 16'h6100;
32'hFFFF1BDA: romout <= 16'h007E;
32'hFFFF1BDC: romout <= 16'h12C1;
32'hFFFF1BDE: romout <= 16'h6100;
32'hFFFF1BE0: romout <= 16'hFFC6;
32'hFFFF1BE2: romout <= 16'h6100;
32'hFFFF1BE4: romout <= 16'h0074;
32'hFFFF1BE6: romout <= 16'h12C1;
32'hFFFF1BE8: romout <= 16'h6100;
32'hFFFF1BEA: romout <= 16'hFFBC;
32'hFFFF1BEC: romout <= 16'h6100;
32'hFFFF1BEE: romout <= 16'h006A;
32'hFFFF1BF0: romout <= 16'h12C1;
32'hFFFF1BF2: romout <= 16'h6100;
32'hFFFF1BF4: romout <= 16'hFFB2;
32'hFFFF1BF6: romout <= 16'h6100;
32'hFFFF1BF8: romout <= 16'h0060;
32'hFFFF1BFA: romout <= 16'h12C1;
32'hFFFF1BFC: romout <= 16'h6100;
32'hFFFF1BFE: romout <= 16'hFFA8;
32'hFFFF1C00: romout <= 16'h6100;
32'hFFFF1C02: romout <= 16'h0056;
32'hFFFF1C04: romout <= 16'h12C1;
32'hFFFF1C06: romout <= 16'h6100;
32'hFFFF1C08: romout <= 16'hFF9E;
32'hFFFF1C0A: romout <= 16'h6100;
32'hFFFF1C0C: romout <= 16'h004C;
32'hFFFF1C0E: romout <= 16'h12C1;
32'hFFFF1C10: romout <= 16'h6000;
32'hFFFF1C12: romout <= 16'hFE68;
32'hFFFF1C14: romout <= 16'h6100;
32'hFFFF1C16: romout <= 16'hFF90;
32'hFFFF1C18: romout <= 16'h6100;
32'hFFFF1C1A: romout <= 16'h003E;
32'hFFFF1C1C: romout <= 16'h2041;
32'hFFFF1C1E: romout <= 16'h4E90;
32'hFFFF1C20: romout <= 16'h6000;
32'hFFFF1C22: romout <= 16'hFE58;
32'hFFFF1C24: romout <= 16'h6100;
32'hFFFF1C26: romout <= 16'hFF80;
32'hFFFF1C28: romout <= 16'h6100;
32'hFFFF1C2A: romout <= 16'h002E;
32'hFFFF1C2C: romout <= 16'h2041;
32'hFFFF1C2E: romout <= 16'h4EB9;
32'hFFFF1C30: romout <= 16'hFFFF;
32'hFFFF1C32: romout <= 16'h16EC;
32'hFFFF1C34: romout <= 16'h6100;
32'hFFFF1C36: romout <= 16'hFDF8;
32'hFFFF1C38: romout <= 16'h6100;
32'hFFFF1C3A: romout <= 16'hFDF4;
32'hFFFF1C3C: romout <= 16'h6100;
32'hFFFF1C3E: romout <= 16'hFDF0;
32'hFFFF1C40: romout <= 16'h6100;
32'hFFFF1C42: romout <= 16'hFDEC;
32'hFFFF1C44: romout <= 16'h6100;
32'hFFFF1C46: romout <= 16'hFDE8;
32'hFFFF1C48: romout <= 16'h6100;
32'hFFFF1C4A: romout <= 16'hFDE4;
32'hFFFF1C4C: romout <= 16'h6100;
32'hFFFF1C4E: romout <= 16'hFDE0;
32'hFFFF1C50: romout <= 16'h6100;
32'hFFFF1C52: romout <= 16'hFDDC;
32'hFFFF1C54: romout <= 16'h6000;
32'hFFFF1C56: romout <= 16'hFE24;
32'hFFFF1C58: romout <= 16'h48E7;
32'hFFFF1C5A: romout <= 16'hA000;
32'hFFFF1C5C: romout <= 16'h4282;
32'hFFFF1C5E: romout <= 16'h7007;
32'hFFFF1C60: romout <= 16'h3218;
32'hFFFF1C62: romout <= 16'h6100;
32'hFFFF1C64: romout <= 16'hFD74;
32'hFFFF1C66: romout <= 16'h6100;
32'hFFFF1C68: romout <= 16'h001E;
32'hFFFF1C6A: romout <= 16'hB23C;
32'hFFFF1C6C: romout <= 16'h00FF;
32'hFFFF1C6E: romout <= 16'h670E;
32'hFFFF1C70: romout <= 16'hE98A;
32'hFFFF1C72: romout <= 16'h0281;
32'hFFFF1C74: romout <= 16'h0000;
32'hFFFF1C76: romout <= 16'h000F;
32'hFFFF1C78: romout <= 16'h8481;
32'hFFFF1C7A: romout <= 16'h51C8;
32'hFFFF1C7C: romout <= 16'hFFE4;
32'hFFFF1C7E: romout <= 16'h2202;
32'hFFFF1C80: romout <= 16'h4CDF;
32'hFFFF1C82: romout <= 16'h0005;
32'hFFFF1C84: romout <= 16'h4E75;
32'hFFFF1C86: romout <= 16'h0C01;
32'hFFFF1C88: romout <= 16'h0030;
32'hFFFF1C8A: romout <= 16'h6538;
32'hFFFF1C8C: romout <= 16'h0C01;
32'hFFFF1C8E: romout <= 16'h0039;
32'hFFFF1C90: romout <= 16'h6206;
32'hFFFF1C92: romout <= 16'h0401;
32'hFFFF1C94: romout <= 16'h0030;
32'hFFFF1C96: romout <= 16'h4E75;
32'hFFFF1C98: romout <= 16'h0C01;
32'hFFFF1C9A: romout <= 16'h0041;
32'hFFFF1C9C: romout <= 16'h6526;
32'hFFFF1C9E: romout <= 16'h0C01;
32'hFFFF1CA0: romout <= 16'h0046;
32'hFFFF1CA2: romout <= 16'h620A;
32'hFFFF1CA4: romout <= 16'h0401;
32'hFFFF1CA6: romout <= 16'h0041;
32'hFFFF1CA8: romout <= 16'h0601;
32'hFFFF1CAA: romout <= 16'h000A;
32'hFFFF1CAC: romout <= 16'h4E75;
32'hFFFF1CAE: romout <= 16'h0C01;
32'hFFFF1CB0: romout <= 16'h0061;
32'hFFFF1CB2: romout <= 16'h6510;
32'hFFFF1CB4: romout <= 16'h0C01;
32'hFFFF1CB6: romout <= 16'h0066;
32'hFFFF1CB8: romout <= 16'h620A;
32'hFFFF1CBA: romout <= 16'h0401;
32'hFFFF1CBC: romout <= 16'h0061;
32'hFFFF1CBE: romout <= 16'h0601;
32'hFFFF1CC0: romout <= 16'h000A;
32'hFFFF1CC2: romout <= 16'h4E75;
32'hFFFF1CC4: romout <= 16'h72FF;
32'hFFFF1CC6: romout <= 16'h4E75;
32'hFFFF1CC8: romout <= 16'h600A;
32'hFFFF1CCA: romout <= 16'h6100;
32'hFFFF1CCC: romout <= 16'h0174;
32'hFFFF1CCE: romout <= 16'h0C00;
32'hFFFF1CD0: romout <= 16'h000A;
32'hFFFF1CD2: romout <= 16'h66F6;
32'hFFFF1CD4: romout <= 16'h6100;
32'hFFFF1CD6: romout <= 16'h016A;
32'hFFFF1CD8: romout <= 16'h1800;
32'hFFFF1CDA: romout <= 16'h0C04;
32'hFFFF1CDC: romout <= 16'h001A;
32'hFFFF1CDE: romout <= 16'h6700;
32'hFFFF1CE0: romout <= 16'hFD9A;
32'hFFFF1CE2: romout <= 16'h0C04;
32'hFFFF1CE4: romout <= 16'h0053;
32'hFFFF1CE6: romout <= 16'h66E2;
32'hFFFF1CE8: romout <= 16'h6100;
32'hFFFF1CEA: romout <= 16'h0156;
32'hFFFF1CEC: romout <= 16'h1800;
32'hFFFF1CEE: romout <= 16'h0C04;
32'hFFFF1CF0: romout <= 16'h0030;
32'hFFFF1CF2: romout <= 16'h65D6;
32'hFFFF1CF4: romout <= 16'h0C04;
32'hFFFF1CF6: romout <= 16'h0039;
32'hFFFF1CF8: romout <= 16'h62D0;
32'hFFFF1CFA: romout <= 16'h6100;
32'hFFFF1CFC: romout <= 16'h0144;
32'hFFFF1CFE: romout <= 16'h6100;
32'hFFFF1D00: romout <= 16'hFF86;
32'hFFFF1D02: romout <= 16'h1401;
32'hFFFF1D04: romout <= 16'h6100;
32'hFFFF1D06: romout <= 16'h013A;
32'hFFFF1D08: romout <= 16'h6100;
32'hFFFF1D0A: romout <= 16'hFF7C;
32'hFFFF1D0C: romout <= 16'hE90A;
32'hFFFF1D0E: romout <= 16'h8202;
32'hFFFF1D10: romout <= 16'h1601;
32'hFFFF1D12: romout <= 16'h0C04;
32'hFFFF1D14: romout <= 16'h0030;
32'hFFFF1D16: romout <= 16'h67B2;
32'hFFFF1D18: romout <= 16'h0C04;
32'hFFFF1D1A: romout <= 16'h0031;
32'hFFFF1D1C: romout <= 16'h676A;
32'hFFFF1D1E: romout <= 16'h0C04;
32'hFFFF1D20: romout <= 16'h0032;
32'hFFFF1D22: romout <= 16'h676A;
32'hFFFF1D24: romout <= 16'h0C04;
32'hFFFF1D26: romout <= 16'h0033;
32'hFFFF1D28: romout <= 16'h676A;
32'hFFFF1D2A: romout <= 16'h0C04;
32'hFFFF1D2C: romout <= 16'h0035;
32'hFFFF1D2E: romout <= 16'h679A;
32'hFFFF1D30: romout <= 16'h0C04;
32'hFFFF1D32: romout <= 16'h0037;
32'hFFFF1D34: romout <= 16'h6764;
32'hFFFF1D36: romout <= 16'h0C04;
32'hFFFF1D38: romout <= 16'h0038;
32'hFFFF1D3A: romout <= 16'h676A;
32'hFFFF1D3C: romout <= 16'h0C04;
32'hFFFF1D3E: romout <= 16'h0039;
32'hFFFF1D40: romout <= 16'h6770;
32'hFFFF1D42: romout <= 16'h6086;
32'hFFFF1D44: romout <= 16'h0243;
32'hFFFF1D46: romout <= 16'h00FF;
32'hFFFF1D48: romout <= 16'h5343;
32'hFFFF1D4A: romout <= 16'h4282;
32'hFFFF1D4C: romout <= 16'h6100;
32'hFFFF1D4E: romout <= 16'h00F2;
32'hFFFF1D50: romout <= 16'h6100;
32'hFFFF1D52: romout <= 16'hFF34;
32'hFFFF1D54: romout <= 16'hE98A;
32'hFFFF1D56: romout <= 16'h8401;
32'hFFFF1D58: romout <= 16'h6100;
32'hFFFF1D5A: romout <= 16'h00E6;
32'hFFFF1D5C: romout <= 16'h6100;
32'hFFFF1D5E: romout <= 16'hFF28;
32'hFFFF1D60: romout <= 16'hE98A;
32'hFFFF1D62: romout <= 16'h8401;
32'hFFFF1D64: romout <= 16'h12C2;
32'hFFFF1D66: romout <= 16'h51CB;
32'hFFFF1D68: romout <= 16'hFFE2;
32'hFFFF1D6A: romout <= 16'h4282;
32'hFFFF1D6C: romout <= 16'h6100;
32'hFFFF1D6E: romout <= 16'h00D2;
32'hFFFF1D70: romout <= 16'h6100;
32'hFFFF1D72: romout <= 16'hFF14;
32'hFFFF1D74: romout <= 16'hE98A;
32'hFFFF1D76: romout <= 16'h8401;
32'hFFFF1D78: romout <= 16'h6100;
32'hFFFF1D7A: romout <= 16'h00C6;
32'hFFFF1D7C: romout <= 16'h6100;
32'hFFFF1D7E: romout <= 16'hFF08;
32'hFFFF1D80: romout <= 16'hE98A;
32'hFFFF1D82: romout <= 16'h8401;
32'hFFFF1D84: romout <= 16'h6000;
32'hFFFF1D86: romout <= 16'hFF44;
32'hFFFF1D88: romout <= 16'h6100;
32'hFFFF1D8A: romout <= 16'h0034;
32'hFFFF1D8C: romout <= 16'h60B6;
32'hFFFF1D8E: romout <= 16'h6100;
32'hFFFF1D90: romout <= 16'h003C;
32'hFFFF1D92: romout <= 16'h60B0;
32'hFFFF1D94: romout <= 16'h6100;
32'hFFFF1D96: romout <= 16'h0044;
32'hFFFF1D98: romout <= 16'h60AA;
32'hFFFF1D9A: romout <= 16'h6100;
32'hFFFF1D9C: romout <= 16'h003E;
32'hFFFF1D9E: romout <= 16'h21C9;
32'hFFFF1DA0: romout <= 16'h0800;
32'hFFFF1DA2: romout <= 16'h6000;
32'hFFFF1DA4: romout <= 16'hFCD6;
32'hFFFF1DA6: romout <= 16'h6100;
32'hFFFF1DA8: romout <= 16'h0024;
32'hFFFF1DAA: romout <= 16'h21C9;
32'hFFFF1DAC: romout <= 16'h0800;
32'hFFFF1DAE: romout <= 16'h6000;
32'hFFFF1DB0: romout <= 16'hFCCA;
32'hFFFF1DB2: romout <= 16'h6100;
32'hFFFF1DB4: romout <= 16'h000A;
32'hFFFF1DB6: romout <= 16'h21C9;
32'hFFFF1DB8: romout <= 16'h0800;
32'hFFFF1DBA: romout <= 16'h6000;
32'hFFFF1DBC: romout <= 16'hFCBE;
32'hFFFF1DBE: romout <= 16'h4282;
32'hFFFF1DC0: romout <= 16'h6100;
32'hFFFF1DC2: romout <= 16'h007E;
32'hFFFF1DC4: romout <= 16'h6100;
32'hFFFF1DC6: romout <= 16'hFEC0;
32'hFFFF1DC8: romout <= 16'h1401;
32'hFFFF1DCA: romout <= 16'h604A;
32'hFFFF1DCC: romout <= 16'h4282;
32'hFFFF1DCE: romout <= 16'h6100;
32'hFFFF1DD0: romout <= 16'h0070;
32'hFFFF1DD2: romout <= 16'h6100;
32'hFFFF1DD4: romout <= 16'hFEB2;
32'hFFFF1DD6: romout <= 16'h1401;
32'hFFFF1DD8: romout <= 16'h6024;
32'hFFFF1DDA: romout <= 16'h4282;
32'hFFFF1DDC: romout <= 16'h6100;
32'hFFFF1DDE: romout <= 16'h0062;
32'hFFFF1DE0: romout <= 16'h6100;
32'hFFFF1DE2: romout <= 16'hFEA4;
32'hFFFF1DE4: romout <= 16'h1401;
32'hFFFF1DE6: romout <= 16'h6100;
32'hFFFF1DE8: romout <= 16'h0058;
32'hFFFF1DEA: romout <= 16'h6100;
32'hFFFF1DEC: romout <= 16'hFE9A;
32'hFFFF1DEE: romout <= 16'hE98A;
32'hFFFF1DF0: romout <= 16'h8401;
32'hFFFF1DF2: romout <= 16'h6100;
32'hFFFF1DF4: romout <= 16'h004C;
32'hFFFF1DF6: romout <= 16'h6100;
32'hFFFF1DF8: romout <= 16'hFE8E;
32'hFFFF1DFA: romout <= 16'hE98A;
32'hFFFF1DFC: romout <= 16'h8401;
32'hFFFF1DFE: romout <= 16'h6100;
32'hFFFF1E00: romout <= 16'h0040;
32'hFFFF1E02: romout <= 16'h6100;
32'hFFFF1E04: romout <= 16'hFE82;
32'hFFFF1E06: romout <= 16'hE98A;
32'hFFFF1E08: romout <= 16'h8401;
32'hFFFF1E0A: romout <= 16'h6100;
32'hFFFF1E0C: romout <= 16'h0034;
32'hFFFF1E0E: romout <= 16'h6100;
32'hFFFF1E10: romout <= 16'hFE76;
32'hFFFF1E12: romout <= 16'hE98A;
32'hFFFF1E14: romout <= 16'h8401;
32'hFFFF1E16: romout <= 16'h6100;
32'hFFFF1E18: romout <= 16'h0028;
32'hFFFF1E1A: romout <= 16'h6100;
32'hFFFF1E1C: romout <= 16'hFE6A;
32'hFFFF1E1E: romout <= 16'hE98A;
32'hFFFF1E20: romout <= 16'h8401;
32'hFFFF1E22: romout <= 16'h6100;
32'hFFFF1E24: romout <= 16'h001C;
32'hFFFF1E26: romout <= 16'h6100;
32'hFFFF1E28: romout <= 16'hFE5E;
32'hFFFF1E2A: romout <= 16'hE98A;
32'hFFFF1E2C: romout <= 16'h8401;
32'hFFFF1E2E: romout <= 16'h6100;
32'hFFFF1E30: romout <= 16'h0010;
32'hFFFF1E32: romout <= 16'h6100;
32'hFFFF1E34: romout <= 16'hFE52;
32'hFFFF1E36: romout <= 16'hE98A;
32'hFFFF1E38: romout <= 16'h8401;
32'hFFFF1E3A: romout <= 16'h4284;
32'hFFFF1E3C: romout <= 16'h2242;
32'hFFFF1E3E: romout <= 16'h4E75;
32'hFFFF1E40: romout <= 16'h6100;
32'hFFFF1E42: romout <= 16'hF898;
32'hFFFF1E44: romout <= 16'h670C;
32'hFFFF1E46: romout <= 16'h6100;
32'hFFFF1E48: romout <= 16'hF810;
32'hFFFF1E4A: romout <= 16'h0C01;
32'hFFFF1E4C: romout <= 16'h0003;
32'hFFFF1E4E: romout <= 16'h6700;
32'hFFFF1E50: romout <= 16'hFC2A;
32'hFFFF1E52: romout <= 16'h6100;
32'hFFFF1E54: romout <= 16'h1288;
32'hFFFF1E56: romout <= 16'h67E8;
32'hFFFF1E58: romout <= 16'h1200;
32'hFFFF1E5A: romout <= 16'h4E75;
32'hFFFF1E5C: romout <= 16'h33FC;
32'hFFFF1E5E: romout <= 16'h000F;
32'hFFFF1E60: romout <= 16'hFFD4;
32'hFFFF1E62: romout <= 16'h0040;
32'hFFFF1E64: romout <= 16'h33FC;
32'hFFFF1E66: romout <= 16'h411B;
32'hFFFF1E68: romout <= 16'hFFD4;
32'hFFFF1E6A: romout <= 16'h0000;
32'hFFFF1E6C: romout <= 16'h4279;
32'hFFFF1E6E: romout <= 16'hFFD4;
32'hFFFF1E70: romout <= 16'h0002;
32'hFFFF1E72: romout <= 16'h4279;
32'hFFFF1E74: romout <= 16'hFFD4;
32'hFFFF1E76: romout <= 16'h0008;
32'hFFFF1E78: romout <= 16'h4279;
32'hFFFF1E7A: romout <= 16'hFFD4;
32'hFFFF1E7C: romout <= 16'h000A;
32'hFFFF1E7E: romout <= 16'h33FC;
32'hFFFF1E80: romout <= 16'h00FF;
32'hFFFF1E82: romout <= 16'hFFD4;
32'hFFFF1E84: romout <= 16'h000C;
32'hFFFF1E86: romout <= 16'h4279;
32'hFFFF1E88: romout <= 16'hFFD4;
32'hFFFF1E8A: romout <= 16'h000E;
32'hFFFF1E8C: romout <= 16'h33FC;
32'hFFFF1E8E: romout <= 16'h1104;
32'hFFFF1E90: romout <= 16'hFFD4;
32'hFFFF1E92: romout <= 16'h0004;
32'hFFFF1E94: romout <= 16'h203C;
32'hFFFF1E96: romout <= 16'h007A;
32'hFFFF1E98: romout <= 16'h1200;
32'hFFFF1E9A: romout <= 16'h5380;
32'hFFFF1E9C: romout <= 16'h66FC;
32'hFFFF1E9E: romout <= 16'h4279;
32'hFFFF1EA0: romout <= 16'hFFD4;
32'hFFFF1EA2: romout <= 16'h0004;
32'hFFFF1EA4: romout <= 16'h33FC;
32'hFFFF1EA6: romout <= 16'h0000;
32'hFFFF1EA8: romout <= 16'hFFD4;
32'hFFFF1EAA: romout <= 16'h0040;
32'hFFFF1EAC: romout <= 16'h4E75;
32'hFFFF1EAE: romout <= 16'h303C;
32'hFFFF1EB0: romout <= 16'h5151;
32'hFFFF1EB2: romout <= 16'h33C0;
32'hFFFF1EB4: romout <= 16'hFFDC;
32'hFFFF1EB6: romout <= 16'h0300;
32'hFFFF1EB8: romout <= 16'h0839;
32'hFFFF1EBA: romout <= 16'h0007;
32'hFFFF1EBC: romout <= 16'hFFDC;
32'hFFFF1EBE: romout <= 16'h0303;
32'hFFFF1EC0: romout <= 16'h66F6;
32'hFFFF1EC2: romout <= 16'h203C;
32'hFFFF1EC4: romout <= 16'h007A;
32'hFFFF1EC6: romout <= 16'h1200;
32'hFFFF1EC8: romout <= 16'h5380;
32'hFFFF1ECA: romout <= 16'h66FC;
32'hFFFF1ECC: romout <= 16'h303C;
32'hFFFF1ECE: romout <= 16'hACAC;
32'hFFFF1ED0: romout <= 16'h33C0;
32'hFFFF1ED2: romout <= 16'hFFDC;
32'hFFFF1ED4: romout <= 16'h0300;
32'hFFFF1ED6: romout <= 16'h0839;
32'hFFFF1ED8: romout <= 16'h0007;
32'hFFFF1EDA: romout <= 16'hFFDC;
32'hFFFF1EDC: romout <= 16'h0303;
32'hFFFF1EDE: romout <= 16'h66F6;
32'hFFFF1EE0: romout <= 16'h3039;
32'hFFFF1EE2: romout <= 16'hFFDC;
32'hFFFF1EE4: romout <= 16'h0302;
32'hFFFF1EE6: romout <= 16'h4840;
32'hFFFF1EE8: romout <= 16'h303C;
32'hFFFF1EEA: romout <= 16'hAAAA;
32'hFFFF1EEC: romout <= 16'h33C0;
32'hFFFF1EEE: romout <= 16'hFFDC;
32'hFFFF1EF0: romout <= 16'h0300;
32'hFFFF1EF2: romout <= 16'h0839;
32'hFFFF1EF4: romout <= 16'h0007;
32'hFFFF1EF6: romout <= 16'hFFDC;
32'hFFFF1EF8: romout <= 16'h0303;
32'hFFFF1EFA: romout <= 16'h66F6;
32'hFFFF1EFC: romout <= 16'h3039;
32'hFFFF1EFE: romout <= 16'hFFDC;
32'hFFFF1F00: romout <= 16'h0302;
32'hFFFF1F02: romout <= 16'h4E75;
32'hFFFF1F04: romout <= 16'h48E7;
32'hFFFF1F06: romout <= 16'hC044;
32'hFFFF1F08: romout <= 16'h2A7C;
32'hFFFF1F0A: romout <= 16'h0000;
32'hFFFF1F0C: romout <= 16'h0700;
32'hFFFF1F0E: romout <= 16'h2001;
32'hFFFF1F10: romout <= 16'h6100;
32'hFFFF1F12: romout <= 16'h122C;
32'hFFFF1F14: romout <= 16'h227C;
32'hFFFF1F16: romout <= 16'h0000;
32'hFFFF1F18: romout <= 16'h0700;
32'hFFFF1F1A: romout <= 16'h6100;
32'hFFFF1F1C: romout <= 16'hF93C;
32'hFFFF1F1E: romout <= 16'h4CDF;
32'hFFFF1F20: romout <= 16'h2203;
32'hFFFF1F22: romout <= 16'h4E75;
32'hFFFF1F24: romout <= 16'h48E7;
32'hFFFF1F26: romout <= 16'hB000;
32'hFFFF1F28: romout <= 16'h343C;
32'hFFFF1F2A: romout <= 16'h0007;
32'hFFFF1F2C: romout <= 16'h1001;
32'hFFFF1F2E: romout <= 16'h0240;
32'hFFFF1F30: romout <= 16'h000F;
32'hFFFF1F32: romout <= 16'h0C40;
32'hFFFF1F34: romout <= 16'h0009;
32'hFFFF1F36: romout <= 16'h6302;
32'hFFFF1F38: romout <= 16'h5E40;
32'hFFFF1F3A: romout <= 16'h0640;
32'hFFFF1F3C: romout <= 16'h0130;
32'hFFFF1F3E: romout <= 16'h3602;
32'hFFFF1F40: romout <= 16'hE343;
32'hFFFF1F42: romout <= 16'h3380;
32'hFFFF1F44: romout <= 16'h3000;
32'hFFFF1F46: romout <= 16'hE899;
32'hFFFF1F48: romout <= 16'h57CA;
32'hFFFF1F4A: romout <= 16'hFFE2;
32'hFFFF1F4C: romout <= 16'h4CDF;
32'hFFFF1F4E: romout <= 16'h000D;
32'hFFFF1F50: romout <= 16'h4E75;
32'hFFFF1F52: romout <= 16'h207C;
32'hFFFF1F54: romout <= 16'h0000;
32'hFFFF1F56: romout <= 16'h0008;
32'hFFFF1F58: romout <= 16'h203C;
32'hFFFF1F5A: romout <= 16'hAAAA;
32'hFFFF1F5C: romout <= 16'h5555;
32'hFFFF1F5E: romout <= 16'h43F9;
32'hFFFF1F60: romout <= 16'hFFD0;
32'hFFFF1F62: romout <= 16'h0014;
32'hFFFF1F64: romout <= 16'h2080;
32'hFFFF1F66: romout <= 16'hB098;
32'hFFFF1F68: romout <= 16'h6614;
32'hFFFF1F6A: romout <= 16'h2208;
32'hFFFF1F6C: romout <= 16'h4A41;
32'hFFFF1F6E: romout <= 16'h6606;
32'hFFFF1F70: romout <= 16'h4EB9;
32'hFFFF1F72: romout <= 16'hFFFF;
32'hFFFF1F74: romout <= 16'h1F24;
32'hFFFF1F76: romout <= 16'hB1FC;
32'hFFFF1F78: romout <= 16'h00FF;
32'hFFFF1F7A: romout <= 16'hFFFC;
32'hFFFF1F7C: romout <= 16'h65E6;
32'hFFFF1F7E: romout <= 16'h2448;
32'hFFFF1F80: romout <= 16'h207C;
32'hFFFF1F82: romout <= 16'h0000;
32'hFFFF1F84: romout <= 16'h0008;
32'hFFFF1F86: romout <= 16'h2018;
32'hFFFF1F88: romout <= 16'h2208;
32'hFFFF1F8A: romout <= 16'h4A41;
32'hFFFF1F8C: romout <= 16'h6606;
32'hFFFF1F8E: romout <= 16'h4EB9;
32'hFFFF1F90: romout <= 16'hFFFF;
32'hFFFF1F92: romout <= 16'h1F24;
32'hFFFF1F94: romout <= 16'h0C80;
32'hFFFF1F96: romout <= 16'hAAAA;
32'hFFFF1F98: romout <= 16'h5555;
32'hFFFF1F9A: romout <= 16'h67EA;
32'hFFFF1F9C: romout <= 16'hB5C8;
32'hFFFF1F9E: romout <= 16'h6668;
32'hFFFF1FA0: romout <= 16'h207C;
32'hFFFF1FA2: romout <= 16'h0000;
32'hFFFF1FA4: romout <= 16'h0008;
32'hFFFF1FA6: romout <= 16'h203C;
32'hFFFF1FA8: romout <= 16'h5555;
32'hFFFF1FAA: romout <= 16'hAAAA;
32'hFFFF1FAC: romout <= 16'h2080;
32'hFFFF1FAE: romout <= 16'hB098;
32'hFFFF1FB0: romout <= 16'h6614;
32'hFFFF1FB2: romout <= 16'h2208;
32'hFFFF1FB4: romout <= 16'h4A41;
32'hFFFF1FB6: romout <= 16'h6606;
32'hFFFF1FB8: romout <= 16'h4EB9;
32'hFFFF1FBA: romout <= 16'hFFFF;
32'hFFFF1FBC: romout <= 16'h1F24;
32'hFFFF1FBE: romout <= 16'hB1FC;
32'hFFFF1FC0: romout <= 16'h00FF;
32'hFFFF1FC2: romout <= 16'hFFFC;
32'hFFFF1FC4: romout <= 16'h65E6;
32'hFFFF1FC6: romout <= 16'h2448;
32'hFFFF1FC8: romout <= 16'h207C;
32'hFFFF1FCA: romout <= 16'h0000;
32'hFFFF1FCC: romout <= 16'h0008;
32'hFFFF1FCE: romout <= 16'h2018;
32'hFFFF1FD0: romout <= 16'h2208;
32'hFFFF1FD2: romout <= 16'h4A41;
32'hFFFF1FD4: romout <= 16'h6606;
32'hFFFF1FD6: romout <= 16'h4EB9;
32'hFFFF1FD8: romout <= 16'hFFFF;
32'hFFFF1FDA: romout <= 16'h1F24;
32'hFFFF1FDC: romout <= 16'h0C80;
32'hFFFF1FDE: romout <= 16'h5555;
32'hFFFF1FE0: romout <= 16'hAAAA;
32'hFFFF1FE2: romout <= 16'h67EA;
32'hFFFF1FE4: romout <= 16'hB5C8;
32'hFFFF1FE6: romout <= 16'h6620;
32'hFFFF1FE8: romout <= 16'h21C8;
32'hFFFF1FEA: romout <= 16'h0500;
32'hFFFF1FEC: romout <= 16'h91FC;
32'hFFFF1FEE: romout <= 16'h0000;
32'hFFFF1FF0: romout <= 16'h000C;
32'hFFFF1FF2: romout <= 16'h21C8;
32'hFFFF1FF4: romout <= 16'h0404;
32'hFFFF1FF6: romout <= 16'h21FC;
32'hFFFF1FF8: romout <= 16'h4652;
32'hFFFF1FFA: romout <= 16'h4545;
32'hFFFF1FFC: romout <= 16'h0400;
32'hFFFF1FFE: romout <= 16'h21FC;
32'hFFFF2000: romout <= 16'h0000;
32'hFFFF2002: romout <= 16'h0408;
32'hFFFF2004: romout <= 16'h0408;
32'hFFFF2006: romout <= 16'h4ED3;
32'hFFFF2008: romout <= 16'h4ED3;
32'hFFFF200A: romout <= 16'h60FC;
32'hFFFF200C: romout <= 16'h48E7;
32'hFFFF200E: romout <= 16'hF0C0;
32'hFFFF2010: romout <= 16'h43F9;
32'hFFFF2012: romout <= 16'hFFFF;
32'hFFFF2014: romout <= 16'h204E;
32'hFFFF2016: romout <= 16'h4EB9;
32'hFFFF2018: romout <= 16'hFFFF;
32'hFFFF201A: romout <= 16'h1858;
32'hFFFF201C: romout <= 16'h4CDF;
32'hFFFF201E: romout <= 16'h030F;
32'hFFFF2020: romout <= 16'h4E73;
32'hFFFF2022: romout <= 16'h48E7;
32'hFFFF2024: romout <= 16'hF0C0;
32'hFFFF2026: romout <= 16'h43F9;
32'hFFFF2028: romout <= 16'hFFFF;
32'hFFFF202A: romout <= 16'h205C;
32'hFFFF202C: romout <= 16'h4EB9;
32'hFFFF202E: romout <= 16'hFFFF;
32'hFFFF2030: romout <= 16'h1858;
32'hFFFF2032: romout <= 16'h4CDF;
32'hFFFF2034: romout <= 16'h030F;
32'hFFFF2036: romout <= 16'h4E73;
32'hFFFF2038: romout <= 16'h48E7;
32'hFFFF203A: romout <= 16'hF0C0;
32'hFFFF203C: romout <= 16'h43F9;
32'hFFFF203E: romout <= 16'hFFFF;
32'hFFFF2040: romout <= 16'h2066;
32'hFFFF2042: romout <= 16'h4EB9;
32'hFFFF2044: romout <= 16'hFFFF;
32'hFFFF2046: romout <= 16'h1858;
32'hFFFF2048: romout <= 16'h4CDF;
32'hFFFF204A: romout <= 16'h030F;
32'hFFFF204C: romout <= 16'h4E73;
32'hFFFF204E: romout <= 16'h4164;
32'hFFFF2050: romout <= 16'h6472;
32'hFFFF2052: romout <= 16'h6573;
32'hFFFF2054: romout <= 16'h7320;
32'hFFFF2056: romout <= 16'h6572;
32'hFFFF2058: romout <= 16'h726F;
32'hFFFF205A: romout <= 16'h7200;
32'hFFFF205C: romout <= 16'h4275;
32'hFFFF205E: romout <= 16'h7320;
32'hFFFF2060: romout <= 16'h6572;
32'hFFFF2062: romout <= 16'h726F;
32'hFFFF2064: romout <= 16'h7200;
32'hFFFF2066: romout <= 16'h496C;
32'hFFFF2068: romout <= 16'h6C65;
32'hFFFF206A: romout <= 16'h6761;
32'hFFFF206C: romout <= 16'h6C20;
32'hFFFF206E: romout <= 16'h696E;
32'hFFFF2070: romout <= 16'h7374;
32'hFFFF2072: romout <= 16'h7275;
32'hFFFF2074: romout <= 16'h6374;
32'hFFFF2076: romout <= 16'h696F;
32'hFFFF2078: romout <= 16'h6E00;
32'hFFFF207A: romout <= 16'h4469;
32'hFFFF207C: romout <= 16'h7669;
32'hFFFF207E: romout <= 16'h6465;
32'hFFFF2080: romout <= 16'h2062;
32'hFFFF2082: romout <= 16'h7920;
32'hFFFF2084: romout <= 16'h7A65;
32'hFFFF2086: romout <= 16'h726F;
32'hFFFF2400: romout <= 16'h6000;
32'hFFFF2402: romout <= 16'h0022;
32'hFFFF2404: romout <= 16'h6000;
32'hFFFF2406: romout <= 16'h005A;
32'hFFFF2408: romout <= 16'h6000;
32'hFFFF240A: romout <= 16'h0C96;
32'hFFFF240C: romout <= 16'h6000;
32'hFFFF240E: romout <= 16'h0CA4;
32'hFFFF2410: romout <= 16'h6000;
32'hFFFF2412: romout <= 16'h0CB8;
32'hFFFF2414: romout <= 16'h6000;
32'hFFFF2416: romout <= 16'h0CC6;
32'hFFFF2418: romout <= 16'h6000;
32'hFFFF241A: romout <= 16'h0CD8;
32'hFFFF241C: romout <= 16'h00C0;
32'hFFFF241E: romout <= 16'h0000;
32'hFFFF2420: romout <= 16'h00F0;
32'hFFFF2422: romout <= 16'h0000;
32'hFFFF2424: romout <= 16'h41F9;
32'hFFFF2426: romout <= 16'hFFFF;
32'hFFFF2428: romout <= 16'h2400;
32'hFFFF242A: romout <= 16'h21C8;
32'hFFFF242C: romout <= 16'h0600;
32'hFFFF242E: romout <= 16'h2E79;
32'hFFFF2430: romout <= 16'hFFFF;
32'hFFFF2432: romout <= 16'h2420;
32'hFFFF2434: romout <= 16'h4DF9;
32'hFFFF2436: romout <= 16'hFFFF;
32'hFFFF2438: romout <= 16'h30F8;
32'hFFFF243A: romout <= 16'h6100;
32'hFFFF243C: romout <= 16'h0C58;
32'hFFFF243E: romout <= 16'h21F9;
32'hFFFF2440: romout <= 16'hFFFF;
32'hFFFF2442: romout <= 16'h241C;
32'hFFFF2444: romout <= 16'h0624;
32'hFFFF2446: romout <= 16'h2039;
32'hFFFF2448: romout <= 16'hFFFF;
32'hFFFF244A: romout <= 16'h2420;
32'hFFFF244C: romout <= 16'h0480;
32'hFFFF244E: romout <= 16'h0000;
32'hFFFF2450: romout <= 16'h0800;
32'hFFFF2452: romout <= 16'h21C0;
32'hFFFF2454: romout <= 16'h062C;
32'hFFFF2456: romout <= 16'h0480;
32'hFFFF2458: romout <= 16'h0000;
32'hFFFF245A: romout <= 16'h1008;
32'hFFFF245C: romout <= 16'h21C0;
32'hFFFF245E: romout <= 16'h0628;
32'hFFFF2460: romout <= 16'h4280;
32'hFFFF2462: romout <= 16'h21C0;
32'hFFFF2464: romout <= 16'h0610;
32'hFFFF2466: romout <= 16'h21C0;
32'hFFFF2468: romout <= 16'h0608;
32'hFFFF246A: romout <= 16'h21C0;
32'hFFFF246C: romout <= 16'h0604;
32'hFFFF246E: romout <= 16'h2E79;
32'hFFFF2470: romout <= 16'hFFFF;
32'hFFFF2472: romout <= 16'h2420;
32'hFFFF2474: romout <= 16'h4DF9;
32'hFFFF2476: romout <= 16'hFFFF;
32'hFFFF2478: romout <= 16'h311E;
32'hFFFF247A: romout <= 16'h6100;
32'hFFFF247C: romout <= 16'h0C18;
32'hFFFF247E: romout <= 16'h103C;
32'hFFFF2480: romout <= 16'h003E;
32'hFFFF2482: romout <= 16'h6100;
32'hFFFF2484: romout <= 16'h0976;
32'hFFFF2486: romout <= 16'h6100;
32'hFFFF2488: romout <= 16'h0BA8;
32'hFFFF248A: romout <= 16'h2848;
32'hFFFF248C: romout <= 16'h41F8;
32'hFFFF248E: romout <= 16'h0630;
32'hFFFF2490: romout <= 16'h6100;
32'hFFFF2492: romout <= 16'h0B5A;
32'hFFFF2494: romout <= 16'h6100;
32'hFFFF2496: romout <= 16'h0B8E;
32'hFFFF2498: romout <= 16'h4A81;
32'hFFFF249A: romout <= 16'h6700;
32'hFFFF249C: romout <= 16'h0152;
32'hFFFF249E: romout <= 16'hB2BC;
32'hFFFF24A0: romout <= 16'h0000;
32'hFFFF24A2: romout <= 16'hFFFF;
32'hFFFF24A4: romout <= 16'h6400;
32'hFFFF24A6: romout <= 16'h094A;
32'hFFFF24A8: romout <= 16'h1101;
32'hFFFF24AA: romout <= 16'hE099;
32'hFFFF24AC: romout <= 16'h1101;
32'hFFFF24AE: romout <= 16'hE199;
32'hFFFF24B0: romout <= 16'h6100;
32'hFFFF24B2: romout <= 16'h09E8;
32'hFFFF24B4: romout <= 16'h2A49;
32'hFFFF24B6: romout <= 16'h6612;
32'hFFFF24B8: romout <= 16'h6100;
32'hFFFF24BA: romout <= 16'h0A08;
32'hFFFF24BC: romout <= 16'h244D;
32'hFFFF24BE: romout <= 16'h2678;
32'hFFFF24C0: romout <= 16'h0624;
32'hFFFF24C2: romout <= 16'h6100;
32'hFFFF24C4: romout <= 16'h0A08;
32'hFFFF24C6: romout <= 16'h21CA;
32'hFFFF24C8: romout <= 16'h0624;
32'hFFFF24CA: romout <= 16'h200C;
32'hFFFF24CC: romout <= 16'h9088;
32'hFFFF24CE: romout <= 16'hB0BC;
32'hFFFF24D0: romout <= 16'h0000;
32'hFFFF24D2: romout <= 16'h0003;
32'hFFFF24D4: romout <= 16'h67A8;
32'hFFFF24D6: romout <= 16'h2678;
32'hFFFF24D8: romout <= 16'h0624;
32'hFFFF24DA: romout <= 16'h2C4B;
32'hFFFF24DC: romout <= 16'hD7C0;
32'hFFFF24DE: romout <= 16'h2038;
32'hFFFF24E0: romout <= 16'h0628;
32'hFFFF24E2: romout <= 16'hB08B;
32'hFFFF24E4: romout <= 16'h6300;
32'hFFFF24E6: romout <= 16'h0900;
32'hFFFF24E8: romout <= 16'h21CB;
32'hFFFF24EA: romout <= 16'h0624;
32'hFFFF24EC: romout <= 16'h224E;
32'hFFFF24EE: romout <= 16'h244D;
32'hFFFF24F0: romout <= 16'h6100;
32'hFFFF24F2: romout <= 16'h09E4;
32'hFFFF24F4: romout <= 16'h2248;
32'hFFFF24F6: romout <= 16'h244D;
32'hFFFF24F8: romout <= 16'h264C;
32'hFFFF24FA: romout <= 16'h6100;
32'hFFFF24FC: romout <= 16'h09D0;
32'hFFFF24FE: romout <= 16'h6000;
32'hFFFF2500: romout <= 16'hFF7E;
32'hFFFF2502: romout <= 16'h4C49;
32'hFFFF2504: romout <= 16'h53D4;
32'hFFFF2506: romout <= 16'h4C4F;
32'hFFFF2508: romout <= 16'h41C4;
32'hFFFF250A: romout <= 16'h4E45;
32'hFFFF250C: romout <= 16'hD752;
32'hFFFF250E: romout <= 16'h55CE;
32'hFFFF2510: romout <= 16'h5341;
32'hFFFF2512: romout <= 16'h56C5;
32'hFFFF2514: romout <= 16'h434C;
32'hFFFF2516: romout <= 16'hD34E;
32'hFFFF2518: romout <= 16'h4558;
32'hFFFF251A: romout <= 16'hD44C;
32'hFFFF251C: romout <= 16'h45D4;
32'hFFFF251E: romout <= 16'h49C6;
32'hFFFF2520: romout <= 16'h474F;
32'hFFFF2522: romout <= 16'h54CF;
32'hFFFF2524: romout <= 16'h474F;
32'hFFFF2526: romout <= 16'h5355;
32'hFFFF2528: romout <= 16'hC252;
32'hFFFF252A: romout <= 16'h4554;
32'hFFFF252C: romout <= 16'h5552;
32'hFFFF252E: romout <= 16'hCE52;
32'hFFFF2530: romout <= 16'h45CD;
32'hFFFF2532: romout <= 16'h464F;
32'hFFFF2534: romout <= 16'hD249;
32'hFFFF2536: romout <= 16'h4E50;
32'hFFFF2538: romout <= 16'h55D4;
32'hFFFF253A: romout <= 16'h5052;
32'hFFFF253C: romout <= 16'h494E;
32'hFFFF253E: romout <= 16'hD450;
32'hFFFF2540: romout <= 16'h4F4B;
32'hFFFF2542: romout <= 16'hC553;
32'hFFFF2544: romout <= 16'h544F;
32'hFFFF2546: romout <= 16'hD042;
32'hFFFF2548: romout <= 16'h59C5;
32'hFFFF254A: romout <= 16'h4341;
32'hFFFF254C: romout <= 16'h4CCC;
32'hFFFF254E: romout <= 16'h4C49;
32'hFFFF2550: romout <= 16'h4EC5;
32'hFFFF2552: romout <= 16'h504F;
32'hFFFF2554: romout <= 16'h494E;
32'hFFFF2556: romout <= 16'hD450;
32'hFFFF2558: romout <= 16'h454E;
32'hFFFF255A: romout <= 16'h434F;
32'hFFFF255C: romout <= 16'h4C4F;
32'hFFFF255E: romout <= 16'hD246;
32'hFFFF2560: romout <= 16'h494C;
32'hFFFF2562: romout <= 16'h4C43;
32'hFFFF2564: romout <= 16'h4F4C;
32'hFFFF2566: romout <= 16'h4FD2;
32'hFFFF2568: romout <= 16'h0050;
32'hFFFF256A: romout <= 16'h4545;
32'hFFFF256C: romout <= 16'hCB52;
32'hFFFF256E: romout <= 16'h4EC4;
32'hFFFF2570: romout <= 16'h4142;
32'hFFFF2572: romout <= 16'hD353;
32'hFFFF2574: romout <= 16'h495A;
32'hFFFF2576: romout <= 16'hC554;
32'hFFFF2578: romout <= 16'h4943;
32'hFFFF257A: romout <= 16'hCB54;
32'hFFFF257C: romout <= 16'h454D;
32'hFFFF257E: romout <= 16'hD053;
32'hFFFF2580: romout <= 16'h47CE;
32'hFFFF2582: romout <= 16'h0054;
32'hFFFF2584: romout <= 16'hCF00;
32'hFFFF2586: romout <= 16'h5354;
32'hFFFF2588: romout <= 16'h45D0;
32'hFFFF258A: romout <= 16'h003E;
32'hFFFF258C: romout <= 16'hBD3C;
32'hFFFF258E: romout <= 16'hBEBE;
32'hFFFF2590: romout <= 16'hBD3C;
32'hFFFF2592: romout <= 16'hBDBC;
32'hFFFF2594: romout <= 16'h00FF;
32'hFFFF2596: romout <= 16'h26B4;
32'hFFFF2598: romout <= 16'h28F6;
32'hFFFF259A: romout <= 16'h264E;
32'hFFFF259C: romout <= 16'h2662;
32'hFFFF259E: romout <= 16'h295A;
32'hFFFF25A0: romout <= 16'h263C;
32'hFFFF25A2: romout <= 16'h2802;
32'hFFFF25A4: romout <= 16'h28E6;
32'hFFFF25A6: romout <= 16'h2852;
32'hFFFF25A8: romout <= 16'h26A0;
32'hFFFF25AA: romout <= 16'h274A;
32'hFFFF25AC: romout <= 16'h2772;
32'hFFFF25AE: romout <= 16'h2850;
32'hFFFF25B0: romout <= 16'h2790;
32'hFFFF25B2: romout <= 16'h2878;
32'hFFFF25B4: romout <= 16'h26E0;
32'hFFFF25B6: romout <= 16'h29DE;
32'hFFFF25B8: romout <= 16'h265A;
32'hFFFF25BA: romout <= 16'h2418;
32'hFFFF25BC: romout <= 16'h2A94;
32'hFFFF25BE: romout <= 16'h2A32;
32'hFFFF25C0: romout <= 16'h29FA;
32'hFFFF25C2: romout <= 16'h2A16;
32'hFFFF25C4: romout <= 16'h2A24;
32'hFFFF25C6: romout <= 16'h28E0;
32'hFFFF25C8: romout <= 16'h2CEE;
32'hFFFF25CA: romout <= 16'h2CFA;
32'hFFFF25CC: romout <= 16'h2D26;
32'hFFFF25CE: romout <= 16'h2D48;
32'hFFFF25D0: romout <= 16'h2D52;
32'hFFFF25D2: romout <= 16'h2D58;
32'hFFFF25D4: romout <= 16'h2D36;
32'hFFFF25D6: romout <= 16'h2BC8;
32'hFFFF25D8: romout <= 16'h27AC;
32'hFFFF25DA: romout <= 16'h2DA4;
32'hFFFF25DC: romout <= 16'h27C4;
32'hFFFF25DE: romout <= 16'h27CA;
32'hFFFF25E0: romout <= 16'h2AC0;
32'hFFFF25E2: romout <= 16'h2AC8;
32'hFFFF25E4: romout <= 16'h2AD0;
32'hFFFF25E6: romout <= 16'h2AE0;
32'hFFFF25E8: romout <= 16'h2AD8;
32'hFFFF25EA: romout <= 16'h2AEA;
32'hFFFF25EC: romout <= 16'h2AFC;
32'hFFFF25EE: romout <= 16'h43F9;
32'hFFFF25F0: romout <= 16'hFFFF;
32'hFFFF25F2: romout <= 16'h2502;
32'hFFFF25F4: romout <= 16'h45F9;
32'hFFFF25F6: romout <= 16'hFFFF;
32'hFFFF25F8: romout <= 16'h2596;
32'hFFFF25FA: romout <= 16'h6100;
32'hFFFF25FC: romout <= 16'h0A28;
32'hFFFF25FE: romout <= 16'h2648;
32'hFFFF2600: romout <= 16'h4202;
32'hFFFF2602: romout <= 16'h1018;
32'hFFFF2604: romout <= 16'h1211;
32'hFFFF2606: romout <= 16'h6604;
32'hFFFF2608: romout <= 16'h204B;
32'hFFFF260A: romout <= 16'h6024;
32'hFFFF260C: romout <= 16'h1600;
32'hFFFF260E: romout <= 16'hC602;
32'hFFFF2610: romout <= 16'hB63C;
32'hFFFF2612: romout <= 16'h002E;
32'hFFFF2614: romout <= 16'h671A;
32'hFFFF2616: romout <= 16'h0201;
32'hFFFF2618: romout <= 16'h007F;
32'hFFFF261A: romout <= 16'hB200;
32'hFFFF261C: romout <= 16'h670C;
32'hFFFF261E: romout <= 16'h548A;
32'hFFFF2620: romout <= 16'h204B;
32'hFFFF2622: romout <= 16'h4202;
32'hFFFF2624: romout <= 16'h4A19;
32'hFFFF2626: romout <= 16'h6AFC;
32'hFFFF2628: romout <= 16'h60D8;
32'hFFFF262A: romout <= 16'h74FF;
32'hFFFF262C: romout <= 16'h4A19;
32'hFFFF262E: romout <= 16'h6AD2;
32'hFFFF2630: romout <= 16'h47F9;
32'hFFFF2632: romout <= 16'hFFFF;
32'hFFFF2634: romout <= 16'h0000;
32'hFFFF2636: romout <= 16'h3452;
32'hFFFF2638: romout <= 16'h4EF3;
32'hFFFF263A: romout <= 16'hA000;
32'hFFFF263C: romout <= 16'h4EB9;
32'hFFFF263E: romout <= 16'hFFFF;
32'hFFFF2640: romout <= 16'h18E8;
32'hFFFF2642: romout <= 16'h4278;
32'hFFFF2644: romout <= 16'h0418;
32'hFFFF2646: romout <= 16'h4278;
32'hFFFF2648: romout <= 16'h041A;
32'hFFFF264A: romout <= 16'h6000;
32'hFFFF264C: romout <= 16'hFE14;
32'hFFFF264E: romout <= 16'h6100;
32'hFFFF2650: romout <= 16'h0748;
32'hFFFF2652: romout <= 16'h21F9;
32'hFFFF2654: romout <= 16'hFFFF;
32'hFFFF2656: romout <= 16'h241C;
32'hFFFF2658: romout <= 16'h0624;
32'hFFFF265A: romout <= 16'h6100;
32'hFFFF265C: romout <= 16'h073C;
32'hFFFF265E: romout <= 16'h6000;
32'hFFFF2660: romout <= 16'hFE00;
32'hFFFF2662: romout <= 16'h6100;
32'hFFFF2664: romout <= 16'h0734;
32'hFFFF2666: romout <= 16'h2079;
32'hFFFF2668: romout <= 16'hFFFF;
32'hFFFF266A: romout <= 16'h241C;
32'hFFFF266C: romout <= 16'h21C8;
32'hFFFF266E: romout <= 16'h0604;
32'hFFFF2670: romout <= 16'h4AB8;
32'hFFFF2672: romout <= 16'h0604;
32'hFFFF2674: romout <= 16'h6700;
32'hFFFF2676: romout <= 16'hFDEA;
32'hFFFF2678: romout <= 16'h4281;
32'hFFFF267A: romout <= 16'h2248;
32'hFFFF267C: romout <= 16'h6100;
32'hFFFF267E: romout <= 16'h082C;
32'hFFFF2680: romout <= 16'h6500;
32'hFFFF2682: romout <= 16'hFDDE;
32'hFFFF2684: romout <= 16'h21C9;
32'hFFFF2686: romout <= 16'h0604;
32'hFFFF2688: romout <= 16'h2049;
32'hFFFF268A: romout <= 16'h5488;
32'hFFFF268C: romout <= 16'h6100;
32'hFFFF268E: romout <= 16'h09EE;
32'hFFFF2690: romout <= 16'h43F9;
32'hFFFF2692: romout <= 16'hFFFF;
32'hFFFF2694: romout <= 16'h2517;
32'hFFFF2696: romout <= 16'h45F9;
32'hFFFF2698: romout <= 16'hFFFF;
32'hFFFF269A: romout <= 16'h25A2;
32'hFFFF269C: romout <= 16'h6000;
32'hFFFF269E: romout <= 16'hFF5C;
32'hFFFF26A0: romout <= 16'h6100;
32'hFFFF26A2: romout <= 16'h0408;
32'hFFFF26A4: romout <= 16'h6100;
32'hFFFF26A6: romout <= 16'h06F2;
32'hFFFF26A8: romout <= 16'h2200;
32'hFFFF26AA: romout <= 16'h6100;
32'hFFFF26AC: romout <= 16'h07EE;
32'hFFFF26AE: romout <= 16'h6600;
32'hFFFF26B0: romout <= 16'h0740;
32'hFFFF26B2: romout <= 16'h60D0;
32'hFFFF26B4: romout <= 16'h6100;
32'hFFFF26B6: romout <= 16'h0936;
32'hFFFF26B8: romout <= 16'h6100;
32'hFFFF26BA: romout <= 16'h06DE;
32'hFFFF26BC: romout <= 16'h6100;
32'hFFFF26BE: romout <= 16'h07DC;
32'hFFFF26C0: romout <= 16'h6500;
32'hFFFF26C2: romout <= 16'hFD9E;
32'hFFFF26C4: romout <= 16'h6100;
32'hFFFF26C6: romout <= 16'h08F0;
32'hFFFF26C8: romout <= 16'h6100;
32'hFFFF26CA: romout <= 16'h09B2;
32'hFFFF26CC: romout <= 16'h670C;
32'hFFFF26CE: romout <= 16'hB03C;
32'hFFFF26D0: romout <= 16'h0013;
32'hFFFF26D2: romout <= 16'h6606;
32'hFFFF26D4: romout <= 16'h6100;
32'hFFFF26D6: romout <= 16'h09A6;
32'hFFFF26D8: romout <= 16'h67FA;
32'hFFFF26DA: romout <= 16'h6100;
32'hFFFF26DC: romout <= 16'h07CE;
32'hFFFF26DE: romout <= 16'h60E0;
32'hFFFF26E0: romout <= 16'h780B;
32'hFFFF26E2: romout <= 16'h6100;
32'hFFFF26E4: romout <= 16'h08EE;
32'hFFFF26E6: romout <= 16'h3A07;
32'hFFFF26E8: romout <= 16'h6100;
32'hFFFF26EA: romout <= 16'h09A4;
32'hFFFF26EC: romout <= 16'h609E;
32'hFFFF26EE: romout <= 16'h6100;
32'hFFFF26F0: romout <= 16'h08E2;
32'hFFFF26F2: romout <= 16'h0D09;
32'hFFFF26F4: romout <= 16'h6100;
32'hFFFF26F6: romout <= 16'h0998;
32'hFFFF26F8: romout <= 16'h6000;
32'hFFFF26FA: romout <= 16'hFF76;
32'hFFFF26FC: romout <= 16'h6100;
32'hFFFF26FE: romout <= 16'h08D4;
32'hFFFF2700: romout <= 16'h2309;
32'hFFFF2702: romout <= 16'h6100;
32'hFFFF2704: romout <= 16'h03A6;
32'hFFFF2706: romout <= 16'h2800;
32'hFFFF2708: romout <= 16'h6016;
32'hFFFF270A: romout <= 16'h6100;
32'hFFFF270C: romout <= 16'h08C6;
32'hFFFF270E: romout <= 16'h240B;
32'hFFFF2710: romout <= 16'h6100;
32'hFFFF2712: romout <= 16'h0398;
32'hFFFF2714: romout <= 16'h6100;
32'hFFFF2716: romout <= 16'hFCF2;
32'hFFFF2718: romout <= 16'h6006;
32'hFFFF271A: romout <= 16'h6100;
32'hFFFF271C: romout <= 16'h081E;
32'hFFFF271E: romout <= 16'h6012;
32'hFFFF2720: romout <= 16'h6100;
32'hFFFF2722: romout <= 16'h08B0;
32'hFFFF2724: romout <= 16'h2C07;
32'hFFFF2726: romout <= 16'h6100;
32'hFFFF2728: romout <= 16'h0656;
32'hFFFF272A: romout <= 16'h60D0;
32'hFFFF272C: romout <= 16'h6100;
32'hFFFF272E: romout <= 16'h0960;
32'hFFFF2730: romout <= 16'h6010;
32'hFFFF2732: romout <= 16'h2F04;
32'hFFFF2734: romout <= 16'h6100;
32'hFFFF2736: romout <= 16'h0374;
32'hFFFF2738: romout <= 16'h281F;
32'hFFFF273A: romout <= 16'h2200;
32'hFFFF273C: romout <= 16'h6100;
32'hFFFF273E: romout <= 16'h083C;
32'hFFFF2740: romout <= 16'h60DE;
32'hFFFF2742: romout <= 16'h6100;
32'hFFFF2744: romout <= 16'h063A;
32'hFFFF2746: romout <= 16'h6000;
32'hFFFF2748: romout <= 16'h065C;
32'hFFFF274A: romout <= 16'h6100;
32'hFFFF274C: romout <= 16'h07AC;
32'hFFFF274E: romout <= 16'h6100;
32'hFFFF2750: romout <= 16'h035A;
32'hFFFF2752: romout <= 16'h2F08;
32'hFFFF2754: romout <= 16'h2200;
32'hFFFF2756: romout <= 16'h6100;
32'hFFFF2758: romout <= 16'h0742;
32'hFFFF275A: romout <= 16'h6600;
32'hFFFF275C: romout <= 16'h0696;
32'hFFFF275E: romout <= 16'h2F38;
32'hFFFF2760: romout <= 16'h0604;
32'hFFFF2762: romout <= 16'h2F38;
32'hFFFF2764: romout <= 16'h0608;
32'hFFFF2766: romout <= 16'h42B8;
32'hFFFF2768: romout <= 16'h0610;
32'hFFFF276A: romout <= 16'h21CF;
32'hFFFF276C: romout <= 16'h0608;
32'hFFFF276E: romout <= 16'h6000;
32'hFFFF2770: romout <= 16'hFF14;
32'hFFFF2772: romout <= 16'h6100;
32'hFFFF2774: romout <= 16'h0624;
32'hFFFF2776: romout <= 16'h2238;
32'hFFFF2778: romout <= 16'h0608;
32'hFFFF277A: romout <= 16'h6700;
32'hFFFF277C: romout <= 16'h0628;
32'hFFFF277E: romout <= 16'h2E41;
32'hFFFF2780: romout <= 16'h21DF;
32'hFFFF2782: romout <= 16'h0608;
32'hFFFF2784: romout <= 16'h21DF;
32'hFFFF2786: romout <= 16'h0604;
32'hFFFF2788: romout <= 16'h205F;
32'hFFFF278A: romout <= 16'h6100;
32'hFFFF278C: romout <= 16'h0752;
32'hFFFF278E: romout <= 16'h60B2;
32'hFFFF2790: romout <= 16'h6100;
32'hFFFF2792: romout <= 16'h0766;
32'hFFFF2794: romout <= 16'h6100;
32'hFFFF2796: romout <= 16'h05CE;
32'hFFFF2798: romout <= 16'h21CE;
32'hFFFF279A: romout <= 16'h0610;
32'hFFFF279C: romout <= 16'h43F9;
32'hFFFF279E: romout <= 16'hFFFF;
32'hFFFF27A0: romout <= 16'h2583;
32'hFFFF27A2: romout <= 16'h45F9;
32'hFFFF27A4: romout <= 16'hFFFF;
32'hFFFF27A6: romout <= 16'h25D8;
32'hFFFF27A8: romout <= 16'h6000;
32'hFFFF27AA: romout <= 16'hFE50;
32'hFFFF27AC: romout <= 16'h6100;
32'hFFFF27AE: romout <= 16'h02FC;
32'hFFFF27B0: romout <= 16'h21C0;
32'hFFFF27B2: romout <= 16'h0618;
32'hFFFF27B4: romout <= 16'h43F9;
32'hFFFF27B6: romout <= 16'hFFFF;
32'hFFFF27B8: romout <= 16'h2586;
32'hFFFF27BA: romout <= 16'h45F9;
32'hFFFF27BC: romout <= 16'hFFFF;
32'hFFFF27BE: romout <= 16'h25DC;
32'hFFFF27C0: romout <= 16'h6000;
32'hFFFF27C2: romout <= 16'hFE38;
32'hFFFF27C4: romout <= 16'h6100;
32'hFFFF27C6: romout <= 16'h02E4;
32'hFFFF27C8: romout <= 16'h6002;
32'hFFFF27CA: romout <= 16'h7001;
32'hFFFF27CC: romout <= 16'h21C0;
32'hFFFF27CE: romout <= 16'h0614;
32'hFFFF27D0: romout <= 16'h21F8;
32'hFFFF27D2: romout <= 16'h0604;
32'hFFFF27D4: romout <= 16'h061C;
32'hFFFF27D6: romout <= 16'h21C8;
32'hFFFF27D8: romout <= 16'h0620;
32'hFFFF27DA: romout <= 16'h2C4F;
32'hFFFF27DC: romout <= 16'h6006;
32'hFFFF27DE: romout <= 16'hDDFC;
32'hFFFF27E0: romout <= 16'h0000;
32'hFFFF27E2: romout <= 16'h0014;
32'hFFFF27E4: romout <= 16'h2016;
32'hFFFF27E6: romout <= 16'h6716;
32'hFFFF27E8: romout <= 16'hB0B8;
32'hFFFF27EA: romout <= 16'h0610;
32'hFFFF27EC: romout <= 16'h66F0;
32'hFFFF27EE: romout <= 16'h244F;
32'hFFFF27F0: romout <= 16'h224E;
32'hFFFF27F2: romout <= 16'h47F8;
32'hFFFF27F4: romout <= 16'h0014;
32'hFFFF27F6: romout <= 16'hD7C9;
32'hFFFF27F8: romout <= 16'h6100;
32'hFFFF27FA: romout <= 16'h06DC;
32'hFFFF27FC: romout <= 16'h2E4B;
32'hFFFF27FE: romout <= 16'h6000;
32'hFFFF2800: romout <= 16'hFF42;
32'hFFFF2802: romout <= 16'h6100;
32'hFFFF2804: romout <= 16'h03F2;
32'hFFFF2806: romout <= 16'h6500;
32'hFFFF2808: romout <= 16'h059C;
32'hFFFF280A: romout <= 16'h2240;
32'hFFFF280C: romout <= 16'h2038;
32'hFFFF280E: romout <= 16'h0610;
32'hFFFF2810: romout <= 16'h6700;
32'hFFFF2812: romout <= 16'h0592;
32'hFFFF2814: romout <= 16'hB3C0;
32'hFFFF2816: romout <= 16'h6706;
32'hFFFF2818: romout <= 16'h6100;
32'hFFFF281A: romout <= 16'h06C4;
32'hFFFF281C: romout <= 16'h60EE;
32'hFFFF281E: romout <= 16'h2011;
32'hFFFF2820: romout <= 16'hD0B8;
32'hFFFF2822: romout <= 16'h0614;
32'hFFFF2824: romout <= 16'h6900;
32'hFFFF2826: romout <= 16'h05CA;
32'hFFFF2828: romout <= 16'h2280;
32'hFFFF282A: romout <= 16'h2238;
32'hFFFF282C: romout <= 16'h0618;
32'hFFFF282E: romout <= 16'h4AB8;
32'hFFFF2830: romout <= 16'h0614;
32'hFFFF2832: romout <= 16'h6A02;
32'hFFFF2834: romout <= 16'hC141;
32'hFFFF2836: romout <= 16'hB280;
32'hFFFF2838: romout <= 16'h6D0E;
32'hFFFF283A: romout <= 16'h21F8;
32'hFFFF283C: romout <= 16'h061C;
32'hFFFF283E: romout <= 16'h0604;
32'hFFFF2840: romout <= 16'h2078;
32'hFFFF2842: romout <= 16'h0620;
32'hFFFF2844: romout <= 16'h6000;
32'hFFFF2846: romout <= 16'hFEFC;
32'hFFFF2848: romout <= 16'h6100;
32'hFFFF284A: romout <= 16'h0694;
32'hFFFF284C: romout <= 16'h6000;
32'hFFFF284E: romout <= 16'hFEF4;
32'hFFFF2850: romout <= 16'h600A;
32'hFFFF2852: romout <= 16'h6100;
32'hFFFF2854: romout <= 16'h0256;
32'hFFFF2856: romout <= 16'h4A80;
32'hFFFF2858: romout <= 16'h6600;
32'hFFFF285A: romout <= 16'hFE32;
32'hFFFF285C: romout <= 16'h2248;
32'hFFFF285E: romout <= 16'h4281;
32'hFFFF2860: romout <= 16'h6100;
32'hFFFF2862: romout <= 16'h0662;
32'hFFFF2864: romout <= 16'h6400;
32'hFFFF2866: romout <= 16'hFE1E;
32'hFFFF2868: romout <= 16'h6000;
32'hFFFF286A: romout <= 16'hFBF6;
32'hFFFF286C: romout <= 16'h2E78;
32'hFFFF286E: romout <= 16'h060C;
32'hFFFF2870: romout <= 16'h21DF;
32'hFFFF2872: romout <= 16'h0604;
32'hFFFF2874: romout <= 16'h588F;
32'hFFFF2876: romout <= 16'h205F;
32'hFFFF2878: romout <= 16'h2F08;
32'hFFFF287A: romout <= 16'h6100;
32'hFFFF287C: romout <= 16'h06BE;
32'hFFFF287E: romout <= 16'h600A;
32'hFFFF2880: romout <= 16'h6100;
32'hFFFF2882: romout <= 16'h0374;
32'hFFFF2884: romout <= 16'h654C;
32'hFFFF2886: romout <= 16'h2440;
32'hFFFF2888: romout <= 16'h601A;
32'hFFFF288A: romout <= 16'h2F08;
32'hFFFF288C: romout <= 16'h6100;
32'hFFFF288E: romout <= 16'h0368;
32'hFFFF2890: romout <= 16'h6500;
32'hFFFF2892: romout <= 16'h0512;
32'hFFFF2894: romout <= 16'h2440;
32'hFFFF2896: romout <= 16'h1410;
32'hFFFF2898: romout <= 16'h4200;
32'hFFFF289A: romout <= 16'h1080;
32'hFFFF289C: romout <= 16'h225F;
32'hFFFF289E: romout <= 16'h6100;
32'hFFFF28A0: romout <= 16'h067E;
32'hFFFF28A2: romout <= 16'h1082;
32'hFFFF28A4: romout <= 16'h2F08;
32'hFFFF28A6: romout <= 16'h2F38;
32'hFFFF28A8: romout <= 16'h0604;
32'hFFFF28AA: romout <= 16'h21FC;
32'hFFFF28AC: romout <= 16'hFFFF;
32'hFFFF28AE: romout <= 16'hFFFF;
32'hFFFF28B0: romout <= 16'h0604;
32'hFFFF28B2: romout <= 16'h21CF;
32'hFFFF28B4: romout <= 16'h060C;
32'hFFFF28B6: romout <= 16'h2F0A;
32'hFFFF28B8: romout <= 16'h103C;
32'hFFFF28BA: romout <= 16'h003A;
32'hFFFF28BC: romout <= 16'h6100;
32'hFFFF28BE: romout <= 16'h053C;
32'hFFFF28C0: romout <= 16'h41F8;
32'hFFFF28C2: romout <= 16'h0630;
32'hFFFF28C4: romout <= 16'h6100;
32'hFFFF28C6: romout <= 16'h01E4;
32'hFFFF28C8: romout <= 16'h245F;
32'hFFFF28CA: romout <= 16'h2480;
32'hFFFF28CC: romout <= 16'h21DF;
32'hFFFF28CE: romout <= 16'h0604;
32'hFFFF28D0: romout <= 16'h205F;
32'hFFFF28D2: romout <= 16'h588F;
32'hFFFF28D4: romout <= 16'h6100;
32'hFFFF28D6: romout <= 16'h06FC;
32'hFFFF28D8: romout <= 16'h2C03;
32'hFFFF28DA: romout <= 16'h609C;
32'hFFFF28DC: romout <= 16'h6000;
32'hFFFF28DE: romout <= 16'hFE64;
32'hFFFF28E0: romout <= 16'h0C10;
32'hFFFF28E2: romout <= 16'h000D;
32'hFFFF28E4: romout <= 16'h670C;
32'hFFFF28E6: romout <= 16'h6100;
32'hFFFF28E8: romout <= 16'h047C;
32'hFFFF28EA: romout <= 16'h6100;
32'hFFFF28EC: romout <= 16'h06E6;
32'hFFFF28EE: romout <= 16'h2C03;
32'hFFFF28F0: romout <= 16'h60F4;
32'hFFFF28F2: romout <= 16'h6000;
32'hFFFF28F4: romout <= 16'hFE4E;
32'hFFFF28F6: romout <= 16'h2079;
32'hFFFF28F8: romout <= 16'hFFFF;
32'hFFFF28FA: romout <= 16'h241C;
32'hFFFF28FC: romout <= 16'h103C;
32'hFFFF28FE: romout <= 16'h000D;
32'hFFFF2900: romout <= 16'h6100;
32'hFFFF2902: romout <= 16'hFB0E;
32'hFFFF2904: romout <= 16'h6100;
32'hFFFF2906: romout <= 16'hFB0E;
32'hFFFF2908: romout <= 16'h67FA;
32'hFFFF290A: romout <= 16'hB03C;
32'hFFFF290C: romout <= 16'h0040;
32'hFFFF290E: romout <= 16'h6722;
32'hFFFF2910: romout <= 16'hB03C;
32'hFFFF2912: romout <= 16'h003A;
32'hFFFF2914: romout <= 16'h66EE;
32'hFFFF2916: romout <= 16'h6100;
32'hFFFF2918: romout <= 16'h0022;
32'hFFFF291A: romout <= 16'h10C1;
32'hFFFF291C: romout <= 16'h6100;
32'hFFFF291E: romout <= 16'h001C;
32'hFFFF2920: romout <= 16'h10C1;
32'hFFFF2922: romout <= 16'h6100;
32'hFFFF2924: romout <= 16'hFAF0;
32'hFFFF2926: romout <= 16'h67FA;
32'hFFFF2928: romout <= 16'h10C0;
32'hFFFF292A: romout <= 16'hB03C;
32'hFFFF292C: romout <= 16'h000D;
32'hFFFF292E: romout <= 16'h66F2;
32'hFFFF2930: romout <= 16'h60D2;
32'hFFFF2932: romout <= 16'h21C8;
32'hFFFF2934: romout <= 16'h0624;
32'hFFFF2936: romout <= 16'h6000;
32'hFFFF2938: romout <= 16'hFB28;
32'hFFFF293A: romout <= 16'h7401;
32'hFFFF293C: romout <= 16'h4281;
32'hFFFF293E: romout <= 16'h6100;
32'hFFFF2940: romout <= 16'hFAD4;
32'hFFFF2942: romout <= 16'h67FA;
32'hFFFF2944: romout <= 16'hB03C;
32'hFFFF2946: romout <= 16'h0041;
32'hFFFF2948: romout <= 16'h6502;
32'hFFFF294A: romout <= 16'h5F00;
32'hFFFF294C: romout <= 16'h0200;
32'hFFFF294E: romout <= 16'h000F;
32'hFFFF2950: romout <= 16'hE909;
32'hFFFF2952: romout <= 16'h8200;
32'hFFFF2954: romout <= 16'h51CA;
32'hFFFF2956: romout <= 16'hFFE8;
32'hFFFF2958: romout <= 16'h4E75;
32'hFFFF295A: romout <= 16'h2079;
32'hFFFF295C: romout <= 16'hFFFF;
32'hFFFF295E: romout <= 16'h241C;
32'hFFFF2960: romout <= 16'h2278;
32'hFFFF2962: romout <= 16'h0624;
32'hFFFF2964: romout <= 16'h103C;
32'hFFFF2966: romout <= 16'h000D;
32'hFFFF2968: romout <= 16'h6100;
32'hFFFF296A: romout <= 16'hFAA6;
32'hFFFF296C: romout <= 16'h103C;
32'hFFFF296E: romout <= 16'h000A;
32'hFFFF2970: romout <= 16'h6100;
32'hFFFF2972: romout <= 16'hFA9E;
32'hFFFF2974: romout <= 16'hB3C8;
32'hFFFF2976: romout <= 16'h6322;
32'hFFFF2978: romout <= 16'h103C;
32'hFFFF297A: romout <= 16'h003A;
32'hFFFF297C: romout <= 16'h6100;
32'hFFFF297E: romout <= 16'hFA92;
32'hFFFF2980: romout <= 16'h1218;
32'hFFFF2982: romout <= 16'h6100;
32'hFFFF2984: romout <= 16'h003A;
32'hFFFF2986: romout <= 16'h1218;
32'hFFFF2988: romout <= 16'h6100;
32'hFFFF298A: romout <= 16'h0034;
32'hFFFF298C: romout <= 16'h1018;
32'hFFFF298E: romout <= 16'hB03C;
32'hFFFF2990: romout <= 16'h000D;
32'hFFFF2992: romout <= 16'h67D0;
32'hFFFF2994: romout <= 16'h6100;
32'hFFFF2996: romout <= 16'hFA7A;
32'hFFFF2998: romout <= 16'h60F2;
32'hFFFF299A: romout <= 16'h103C;
32'hFFFF299C: romout <= 16'h0040;
32'hFFFF299E: romout <= 16'h6100;
32'hFFFF29A0: romout <= 16'hFA70;
32'hFFFF29A2: romout <= 16'h103C;
32'hFFFF29A4: romout <= 16'h000D;
32'hFFFF29A6: romout <= 16'h6100;
32'hFFFF29A8: romout <= 16'hFA68;
32'hFFFF29AA: romout <= 16'h103C;
32'hFFFF29AC: romout <= 16'h000A;
32'hFFFF29AE: romout <= 16'h6100;
32'hFFFF29B0: romout <= 16'hFA60;
32'hFFFF29B2: romout <= 16'h103C;
32'hFFFF29B4: romout <= 16'h001A;
32'hFFFF29B6: romout <= 16'h6100;
32'hFFFF29B8: romout <= 16'hFA58;
32'hFFFF29BA: romout <= 16'h6000;
32'hFFFF29BC: romout <= 16'hFAA4;
32'hFFFF29BE: romout <= 16'h7401;
32'hFFFF29C0: romout <= 16'hE919;
32'hFFFF29C2: romout <= 16'h1001;
32'hFFFF29C4: romout <= 16'h0200;
32'hFFFF29C6: romout <= 16'h000F;
32'hFFFF29C8: romout <= 16'h0600;
32'hFFFF29CA: romout <= 16'h0030;
32'hFFFF29CC: romout <= 16'hB03C;
32'hFFFF29CE: romout <= 16'h0039;
32'hFFFF29D0: romout <= 16'h6302;
32'hFFFF29D2: romout <= 16'h5E00;
32'hFFFF29D4: romout <= 16'h6100;
32'hFFFF29D6: romout <= 16'hFA3A;
32'hFFFF29D8: romout <= 16'h51CA;
32'hFFFF29DA: romout <= 16'hFFE6;
32'hFFFF29DC: romout <= 16'h4E75;
32'hFFFF29DE: romout <= 16'h6100;
32'hFFFF29E0: romout <= 16'h00CA;
32'hFFFF29E2: romout <= 16'h6100;
32'hFFFF29E4: romout <= 16'h05EE;
32'hFFFF29E6: romout <= 16'h2C0F;
32'hFFFF29E8: romout <= 16'h2F00;
32'hFFFF29EA: romout <= 16'h6100;
32'hFFFF29EC: romout <= 16'h00BE;
32'hFFFF29EE: romout <= 16'h225F;
32'hFFFF29F0: romout <= 16'h1280;
32'hFFFF29F2: romout <= 16'h6000;
32'hFFFF29F4: romout <= 16'hFD4E;
32'hFFFF29F6: romout <= 16'h6000;
32'hFFFF29F8: romout <= 16'h03AC;
32'hFFFF29FA: romout <= 16'h6100;
32'hFFFF29FC: romout <= 16'h00AE;
32'hFFFF29FE: romout <= 16'h6100;
32'hFFFF2A00: romout <= 16'h05D2;
32'hFFFF2A02: romout <= 16'h2CF3;
32'hFFFF2A04: romout <= 16'h2F00;
32'hFFFF2A06: romout <= 16'h6100;
32'hFFFF2A08: romout <= 16'h00A2;
32'hFFFF2A0A: romout <= 16'h221F;
32'hFFFF2A0C: romout <= 16'h2400;
32'hFFFF2A0E: romout <= 16'h6100;
32'hFFFF2A10: romout <= 16'hEAEE;
32'hFFFF2A12: romout <= 16'h6000;
32'hFFFF2A14: romout <= 16'hFD2E;
32'hFFFF2A16: romout <= 16'h6100;
32'hFFFF2A18: romout <= 16'h0092;
32'hFFFF2A1A: romout <= 16'h23C0;
32'hFFFF2A1C: romout <= 16'hFFDA;
32'hFFFF2A1E: romout <= 16'hE000;
32'hFFFF2A20: romout <= 16'h6000;
32'hFFFF2A22: romout <= 16'hFD20;
32'hFFFF2A24: romout <= 16'h6100;
32'hFFFF2A26: romout <= 16'h0084;
32'hFFFF2A28: romout <= 16'h23C0;
32'hFFFF2A2A: romout <= 16'hFFDA;
32'hFFFF2A2C: romout <= 16'hE004;
32'hFFFF2A2E: romout <= 16'h6000;
32'hFFFF2A30: romout <= 16'hFD12;
32'hFFFF2A32: romout <= 16'h6100;
32'hFFFF2A34: romout <= 16'h0076;
32'hFFFF2A36: romout <= 16'h6100;
32'hFFFF2A38: romout <= 16'h059A;
32'hFFFF2A3A: romout <= 16'h2C49;
32'hFFFF2A3C: romout <= 16'h2F00;
32'hFFFF2A3E: romout <= 16'h6100;
32'hFFFF2A40: romout <= 16'h006A;
32'hFFFF2A42: romout <= 16'h6100;
32'hFFFF2A44: romout <= 16'h058E;
32'hFFFF2A46: romout <= 16'h2C41;
32'hFFFF2A48: romout <= 16'h2F00;
32'hFFFF2A4A: romout <= 16'h6100;
32'hFFFF2A4C: romout <= 16'h005E;
32'hFFFF2A4E: romout <= 16'h6100;
32'hFFFF2A50: romout <= 16'h0582;
32'hFFFF2A52: romout <= 16'h2C3B;
32'hFFFF2A54: romout <= 16'h2F00;
32'hFFFF2A56: romout <= 16'h6100;
32'hFFFF2A58: romout <= 16'h0052;
32'hFFFF2A5A: romout <= 16'h33C0;
32'hFFFF2A5C: romout <= 16'hFFDA;
32'hFFFF2A5E: romout <= 16'hE00E;
32'hFFFF2A60: romout <= 16'h201F;
32'hFFFF2A62: romout <= 16'h33C0;
32'hFFFF2A64: romout <= 16'hFFDA;
32'hFFFF2A66: romout <= 16'hE00C;
32'hFFFF2A68: romout <= 16'h201F;
32'hFFFF2A6A: romout <= 16'h33C0;
32'hFFFF2A6C: romout <= 16'hFFDA;
32'hFFFF2A6E: romout <= 16'hE00A;
32'hFFFF2A70: romout <= 16'h201F;
32'hFFFF2A72: romout <= 16'h33C0;
32'hFFFF2A74: romout <= 16'hFFDA;
32'hFFFF2A76: romout <= 16'hE008;
32'hFFFF2A78: romout <= 16'h33FC;
32'hFFFF2A7A: romout <= 16'h0002;
32'hFFFF2A7C: romout <= 16'hFFDA;
32'hFFFF2A7E: romout <= 16'hE01E;
32'hFFFF2A80: romout <= 16'h6000;
32'hFFFF2A82: romout <= 16'hFCC0;
32'hFFFF2A84: romout <= 16'h6000;
32'hFFFF2A86: romout <= 16'h031E;
32'hFFFF2A88: romout <= 16'h588F;
32'hFFFF2A8A: romout <= 16'h6000;
32'hFFFF2A8C: romout <= 16'h0318;
32'hFFFF2A8E: romout <= 16'h508F;
32'hFFFF2A90: romout <= 16'h6000;
32'hFFFF2A92: romout <= 16'h0312;
32'hFFFF2A94: romout <= 16'h6100;
32'hFFFF2A96: romout <= 16'h0014;
32'hFFFF2A98: romout <= 16'h4A80;
32'hFFFF2A9A: romout <= 16'h6700;
32'hFFFF2A9C: romout <= 16'h0354;
32'hFFFF2A9E: romout <= 16'h2F08;
32'hFFFF2AA0: romout <= 16'h2240;
32'hFFFF2AA2: romout <= 16'h4E91;
32'hFFFF2AA4: romout <= 16'h205F;
32'hFFFF2AA6: romout <= 16'h6000;
32'hFFFF2AA8: romout <= 16'hFC9A;
32'hFFFF2AAA: romout <= 16'h6100;
32'hFFFF2AAC: romout <= 16'h0066;
32'hFFFF2AAE: romout <= 16'h2F00;
32'hFFFF2AB0: romout <= 16'h43F9;
32'hFFFF2AB2: romout <= 16'hFFFF;
32'hFFFF2AB4: romout <= 16'h258B;
32'hFFFF2AB6: romout <= 16'h45F9;
32'hFFFF2AB8: romout <= 16'hFFFF;
32'hFFFF2ABA: romout <= 16'h25E0;
32'hFFFF2ABC: romout <= 16'h6000;
32'hFFFF2ABE: romout <= 16'hFB3C;
32'hFFFF2AC0: romout <= 16'h6100;
32'hFFFF2AC2: romout <= 16'h003E;
32'hFFFF2AC4: romout <= 16'h6D2E;
32'hFFFF2AC6: romout <= 16'h6030;
32'hFFFF2AC8: romout <= 16'h6100;
32'hFFFF2ACA: romout <= 16'h0036;
32'hFFFF2ACC: romout <= 16'h6726;
32'hFFFF2ACE: romout <= 16'h6028;
32'hFFFF2AD0: romout <= 16'h6100;
32'hFFFF2AD2: romout <= 16'h002E;
32'hFFFF2AD4: romout <= 16'h6F1E;
32'hFFFF2AD6: romout <= 16'h6020;
32'hFFFF2AD8: romout <= 16'h6100;
32'hFFFF2ADA: romout <= 16'h0026;
32'hFFFF2ADC: romout <= 16'h6E16;
32'hFFFF2ADE: romout <= 16'h6018;
32'hFFFF2AE0: romout <= 16'h6100;
32'hFFFF2AE2: romout <= 16'h001E;
32'hFFFF2AE4: romout <= 16'h660E;
32'hFFFF2AE6: romout <= 16'h6010;
32'hFFFF2AE8: romout <= 16'h4E75;
32'hFFFF2AEA: romout <= 16'h6100;
32'hFFFF2AEC: romout <= 16'h0014;
32'hFFFF2AEE: romout <= 16'h6C04;
32'hFFFF2AF0: romout <= 16'h6006;
32'hFFFF2AF2: romout <= 16'h4E75;
32'hFFFF2AF4: romout <= 16'h4280;
32'hFFFF2AF6: romout <= 16'h4E75;
32'hFFFF2AF8: romout <= 16'h7001;
32'hFFFF2AFA: romout <= 16'h4E75;
32'hFFFF2AFC: romout <= 16'h201F;
32'hFFFF2AFE: romout <= 16'h4E75;
32'hFFFF2B00: romout <= 16'h201F;
32'hFFFF2B02: romout <= 16'h221F;
32'hFFFF2B04: romout <= 16'h2F00;
32'hFFFF2B06: romout <= 16'h2F01;
32'hFFFF2B08: romout <= 16'h6100;
32'hFFFF2B0A: romout <= 16'h0008;
32'hFFFF2B0C: romout <= 16'h221F;
32'hFFFF2B0E: romout <= 16'hB280;
32'hFFFF2B10: romout <= 16'h4E75;
32'hFFFF2B12: romout <= 16'h6100;
32'hFFFF2B14: romout <= 16'h04BE;
32'hFFFF2B16: romout <= 16'h2D05;
32'hFFFF2B18: romout <= 16'h4280;
32'hFFFF2B1A: romout <= 16'h603C;
32'hFFFF2B1C: romout <= 16'h6100;
32'hFFFF2B1E: romout <= 16'h04B4;
32'hFFFF2B20: romout <= 16'h2111;
32'hFFFF2B22: romout <= 16'h4280;
32'hFFFF2B24: romout <= 16'h2F00;
32'hFFFF2B26: romout <= 16'h6100;
32'hFFFF2B28: romout <= 16'h0062;
32'hFFFF2B2A: romout <= 16'h4680;
32'hFFFF2B2C: romout <= 16'h4EF9;
32'hFFFF2B2E: romout <= 16'hFFFF;
32'hFFFF2B30: romout <= 16'h2B48;
32'hFFFF2B32: romout <= 16'h6100;
32'hFFFF2B34: romout <= 16'h049E;
32'hFFFF2B36: romout <= 16'h2B01;
32'hFFFF2B38: romout <= 16'h6100;
32'hFFFF2B3A: romout <= 16'h0050;
32'hFFFF2B3C: romout <= 16'h6100;
32'hFFFF2B3E: romout <= 16'h0494;
32'hFFFF2B40: romout <= 16'h2B11;
32'hFFFF2B42: romout <= 16'h2F00;
32'hFFFF2B44: romout <= 16'h6100;
32'hFFFF2B46: romout <= 16'h0044;
32'hFFFF2B48: romout <= 16'h221F;
32'hFFFF2B4A: romout <= 16'hD081;
32'hFFFF2B4C: romout <= 16'h6900;
32'hFFFF2B4E: romout <= 16'h02A2;
32'hFFFF2B50: romout <= 16'h60EA;
32'hFFFF2B52: romout <= 16'h6100;
32'hFFFF2B54: romout <= 16'h047E;
32'hFFFF2B56: romout <= 16'h2D0F;
32'hFFFF2B58: romout <= 16'h2F00;
32'hFFFF2B5A: romout <= 16'h6100;
32'hFFFF2B5C: romout <= 16'h002E;
32'hFFFF2B5E: romout <= 16'h4480;
32'hFFFF2B60: romout <= 16'h4EF9;
32'hFFFF2B62: romout <= 16'hFFFF;
32'hFFFF2B64: romout <= 16'h2B48;
32'hFFFF2B66: romout <= 16'h6100;
32'hFFFF2B68: romout <= 16'h046A;
32'hFFFF2B6A: romout <= 16'h260D;
32'hFFFF2B6C: romout <= 16'h2F00;
32'hFFFF2B6E: romout <= 16'h6100;
32'hFFFF2B70: romout <= 16'h001A;
32'hFFFF2B72: romout <= 16'h221F;
32'hFFFF2B74: romout <= 16'hC081;
32'hFFFF2B76: romout <= 16'h60C4;
32'hFFFF2B78: romout <= 16'h6100;
32'hFFFF2B7A: romout <= 16'h0458;
32'hFFFF2B7C: romout <= 16'h7C73;
32'hFFFF2B7E: romout <= 16'h2F00;
32'hFFFF2B80: romout <= 16'h6100;
32'hFFFF2B82: romout <= 16'h0008;
32'hFFFF2B84: romout <= 16'h221F;
32'hFFFF2B86: romout <= 16'h8081;
32'hFFFF2B88: romout <= 16'h60B2;
32'hFFFF2B8A: romout <= 16'h6100;
32'hFFFF2B8C: romout <= 16'h002C;
32'hFFFF2B8E: romout <= 16'h6100;
32'hFFFF2B90: romout <= 16'h0442;
32'hFFFF2B92: romout <= 16'h2A0F;
32'hFFFF2B94: romout <= 16'h2F00;
32'hFFFF2B96: romout <= 16'h6100;
32'hFFFF2B98: romout <= 16'h0020;
32'hFFFF2B9A: romout <= 16'h221F;
32'hFFFF2B9C: romout <= 16'h6100;
32'hFFFF2B9E: romout <= 16'h00D2;
32'hFFFF2BA0: romout <= 16'h60EC;
32'hFFFF2BA2: romout <= 16'h6100;
32'hFFFF2BA4: romout <= 16'h042E;
32'hFFFF2BA6: romout <= 16'h2F49;
32'hFFFF2BA8: romout <= 16'h2F00;
32'hFFFF2BAA: romout <= 16'h6100;
32'hFFFF2BAC: romout <= 16'h000C;
32'hFFFF2BAE: romout <= 16'h221F;
32'hFFFF2BB0: romout <= 16'hC141;
32'hFFFF2BB2: romout <= 16'h6100;
32'hFFFF2BB4: romout <= 16'h00FE;
32'hFFFF2BB6: romout <= 16'h60D6;
32'hFFFF2BB8: romout <= 16'h43F9;
32'hFFFF2BBA: romout <= 16'hFFFF;
32'hFFFF2BBC: romout <= 16'h2569;
32'hFFFF2BBE: romout <= 16'h45F9;
32'hFFFF2BC0: romout <= 16'hFFFF;
32'hFFFF2BC2: romout <= 16'h25C8;
32'hFFFF2BC4: romout <= 16'h6000;
32'hFFFF2BC6: romout <= 16'hFA34;
32'hFFFF2BC8: romout <= 16'h6100;
32'hFFFF2BCA: romout <= 16'h002C;
32'hFFFF2BCC: romout <= 16'h6508;
32'hFFFF2BCE: romout <= 16'h2240;
32'hFFFF2BD0: romout <= 16'h4280;
32'hFFFF2BD2: romout <= 16'h2011;
32'hFFFF2BD4: romout <= 16'h4E75;
32'hFFFF2BD6: romout <= 16'h6100;
32'hFFFF2BD8: romout <= 16'h0414;
32'hFFFF2BDA: romout <= 16'h2001;
32'hFFFF2BDC: romout <= 16'h4A82;
32'hFFFF2BDE: romout <= 16'h66F4;
32'hFFFF2BE0: romout <= 16'h6100;
32'hFFFF2BE2: romout <= 16'h03F0;
32'hFFFF2BE4: romout <= 16'h280D;
32'hFFFF2BE6: romout <= 16'h6100;
32'hFFFF2BE8: romout <= 16'hFEC2;
32'hFFFF2BEA: romout <= 16'h6100;
32'hFFFF2BEC: romout <= 16'h03E6;
32'hFFFF2BEE: romout <= 16'h2903;
32'hFFFF2BF0: romout <= 16'h4E75;
32'hFFFF2BF2: romout <= 16'h6000;
32'hFFFF2BF4: romout <= 16'h01B0;
32'hFFFF2BF6: romout <= 16'h6100;
32'hFFFF2BF8: romout <= 16'h042C;
32'hFFFF2BFA: romout <= 16'h4280;
32'hFFFF2BFC: romout <= 16'h1010;
32'hFFFF2BFE: romout <= 16'h0400;
32'hFFFF2C00: romout <= 16'h0040;
32'hFFFF2C02: romout <= 16'h6554;
32'hFFFF2C04: romout <= 16'h6628;
32'hFFFF2C06: romout <= 16'h5288;
32'hFFFF2C08: romout <= 16'h6100;
32'hFFFF2C0A: romout <= 16'hFFD6;
32'hFFFF2C0C: romout <= 16'hD080;
32'hFFFF2C0E: romout <= 16'h6500;
32'hFFFF2C10: romout <= 16'h01E0;
32'hFFFF2C12: romout <= 16'hD080;
32'hFFFF2C14: romout <= 16'h6500;
32'hFFFF2C16: romout <= 16'h01DA;
32'hFFFF2C18: romout <= 16'h2F00;
32'hFFFF2C1A: romout <= 16'h6100;
32'hFFFF2C1C: romout <= 16'h012C;
32'hFFFF2C1E: romout <= 16'h221F;
32'hFFFF2C20: romout <= 16'hB081;
32'hFFFF2C22: romout <= 16'h6300;
32'hFFFF2C24: romout <= 16'h01C2;
32'hFFFF2C26: romout <= 16'h2038;
32'hFFFF2C28: romout <= 16'h0628;
32'hFFFF2C2A: romout <= 16'h9081;
32'hFFFF2C2C: romout <= 16'h4E75;
32'hFFFF2C2E: romout <= 16'hB03C;
32'hFFFF2C30: romout <= 16'h001B;
32'hFFFF2C32: romout <= 16'h0A3C;
32'hFFFF2C34: romout <= 16'h0001;
32'hFFFF2C36: romout <= 16'h6520;
32'hFFFF2C38: romout <= 16'h5288;
32'hFFFF2C3A: romout <= 16'h4281;
32'hFFFF2C3C: romout <= 16'h1210;
32'hFFFF2C3E: romout <= 16'h6100;
32'hFFFF2C40: romout <= 16'h001A;
32'hFFFF2C42: romout <= 16'h0C01;
32'hFFFF2C44: romout <= 16'h00FF;
32'hFFFF2C46: romout <= 16'h6706;
32'hFFFF2C48: romout <= 16'h5288;
32'hFFFF2C4A: romout <= 16'hEB81;
32'hFFFF2C4C: romout <= 16'hD081;
32'hFFFF2C4E: romout <= 16'hD080;
32'hFFFF2C50: romout <= 16'hD080;
32'hFFFF2C52: romout <= 16'h2238;
32'hFFFF2C54: romout <= 16'h0628;
32'hFFFF2C56: romout <= 16'hD081;
32'hFFFF2C58: romout <= 16'h4E75;
32'hFFFF2C5A: romout <= 16'h0C01;
32'hFFFF2C5C: romout <= 16'h0041;
32'hFFFF2C5E: romout <= 16'h650C;
32'hFFFF2C60: romout <= 16'h0C01;
32'hFFFF2C62: romout <= 16'h005A;
32'hFFFF2C64: romout <= 16'h6206;
32'hFFFF2C66: romout <= 16'h0401;
32'hFFFF2C68: romout <= 16'h0041;
32'hFFFF2C6A: romout <= 16'h4E75;
32'hFFFF2C6C: romout <= 16'h72FF;
32'hFFFF2C6E: romout <= 16'h4E75;
32'hFFFF2C70: romout <= 16'h2801;
32'hFFFF2C72: romout <= 16'hB184;
32'hFFFF2C74: romout <= 16'h4A80;
32'hFFFF2C76: romout <= 16'h6A02;
32'hFFFF2C78: romout <= 16'h4480;
32'hFFFF2C7A: romout <= 16'h4A81;
32'hFFFF2C7C: romout <= 16'h6A02;
32'hFFFF2C7E: romout <= 16'h4481;
32'hFFFF2C80: romout <= 16'hB2BC;
32'hFFFF2C82: romout <= 16'h0000;
32'hFFFF2C84: romout <= 16'hFFFF;
32'hFFFF2C86: romout <= 16'h630C;
32'hFFFF2C88: romout <= 16'hC141;
32'hFFFF2C8A: romout <= 16'hB2BC;
32'hFFFF2C8C: romout <= 16'h0000;
32'hFFFF2C8E: romout <= 16'hFFFF;
32'hFFFF2C90: romout <= 16'h6200;
32'hFFFF2C92: romout <= 16'h015E;
32'hFFFF2C94: romout <= 16'h2400;
32'hFFFF2C96: romout <= 16'hC4C1;
32'hFFFF2C98: romout <= 16'h4840;
32'hFFFF2C9A: romout <= 16'hC0C1;
32'hFFFF2C9C: romout <= 16'h4840;
32'hFFFF2C9E: romout <= 16'h4A80;
32'hFFFF2CA0: romout <= 16'h6600;
32'hFFFF2CA2: romout <= 16'h014E;
32'hFFFF2CA4: romout <= 16'hD082;
32'hFFFF2CA6: romout <= 16'h6B00;
32'hFFFF2CA8: romout <= 16'h0148;
32'hFFFF2CAA: romout <= 16'h4A84;
32'hFFFF2CAC: romout <= 16'h6A02;
32'hFFFF2CAE: romout <= 16'h4480;
32'hFFFF2CB0: romout <= 16'h4E75;
32'hFFFF2CB2: romout <= 16'h4A81;
32'hFFFF2CB4: romout <= 16'h6700;
32'hFFFF2CB6: romout <= 16'h013A;
32'hFFFF2CB8: romout <= 16'h2401;
32'hFFFF2CBA: romout <= 16'h2801;
32'hFFFF2CBC: romout <= 16'hB184;
32'hFFFF2CBE: romout <= 16'h4A80;
32'hFFFF2CC0: romout <= 16'h6A02;
32'hFFFF2CC2: romout <= 16'h4480;
32'hFFFF2CC4: romout <= 16'h4A81;
32'hFFFF2CC6: romout <= 16'h6A02;
32'hFFFF2CC8: romout <= 16'h4481;
32'hFFFF2CCA: romout <= 16'h761F;
32'hFFFF2CCC: romout <= 16'h2200;
32'hFFFF2CCE: romout <= 16'h4280;
32'hFFFF2CD0: romout <= 16'hD281;
32'hFFFF2CD2: romout <= 16'hD180;
32'hFFFF2CD4: romout <= 16'h6708;
32'hFFFF2CD6: romout <= 16'hB082;
32'hFFFF2CD8: romout <= 16'h6B04;
32'hFFFF2CDA: romout <= 16'h5281;
32'hFFFF2CDC: romout <= 16'h9082;
32'hFFFF2CDE: romout <= 16'h51CB;
32'hFFFF2CE0: romout <= 16'hFFF0;
32'hFFFF2CE2: romout <= 16'hC141;
32'hFFFF2CE4: romout <= 16'h4A84;
32'hFFFF2CE6: romout <= 16'h6A04;
32'hFFFF2CE8: romout <= 16'h4480;
32'hFFFF2CEA: romout <= 16'h4481;
32'hFFFF2CEC: romout <= 16'h4E75;
32'hFFFF2CEE: romout <= 16'h6100;
32'hFFFF2CF0: romout <= 16'hFEF0;
32'hFFFF2CF2: romout <= 16'h2240;
32'hFFFF2CF4: romout <= 16'h4280;
32'hFFFF2CF6: romout <= 16'h1011;
32'hFFFF2CF8: romout <= 16'h4E75;
32'hFFFF2CFA: romout <= 16'h6100;
32'hFFFF2CFC: romout <= 16'hFEE4;
32'hFFFF2CFE: romout <= 16'h4A80;
32'hFFFF2D00: romout <= 16'h6700;
32'hFFFF2D02: romout <= 16'h00EE;
32'hFFFF2D04: romout <= 16'h6B00;
32'hFFFF2D06: romout <= 16'h00EA;
32'hFFFF2D08: romout <= 16'h2200;
32'hFFFF2D0A: romout <= 16'h3039;
32'hFFFF2D0C: romout <= 16'hFFDC;
32'hFFFF2D0E: romout <= 16'h0C02;
32'hFFFF2D10: romout <= 16'h4840;
32'hFFFF2D12: romout <= 16'h3039;
32'hFFFF2D14: romout <= 16'hFFDC;
32'hFFFF2D16: romout <= 16'h0C00;
32'hFFFF2D18: romout <= 16'h0880;
32'hFFFF2D1A: romout <= 16'h001F;
32'hFFFF2D1C: romout <= 16'h6100;
32'hFFFF2D1E: romout <= 16'hFF94;
32'hFFFF2D20: romout <= 16'h2001;
32'hFFFF2D22: romout <= 16'h5280;
32'hFFFF2D24: romout <= 16'h4E75;
32'hFFFF2D26: romout <= 16'h6100;
32'hFFFF2D28: romout <= 16'hFEB8;
32'hFFFF2D2A: romout <= 16'h4A80;
32'hFFFF2D2C: romout <= 16'h6A06;
32'hFFFF2D2E: romout <= 16'h4480;
32'hFFFF2D30: romout <= 16'h6B00;
32'hFFFF2D32: romout <= 16'h00BE;
32'hFFFF2D34: romout <= 16'h4E75;
32'hFFFF2D36: romout <= 16'h6100;
32'hFFFF2D38: romout <= 16'hFEA8;
32'hFFFF2D3A: romout <= 16'h4A80;
32'hFFFF2D3C: romout <= 16'h6704;
32'hFFFF2D3E: romout <= 16'h6B04;
32'hFFFF2D40: romout <= 16'h7001;
32'hFFFF2D42: romout <= 16'h4E75;
32'hFFFF2D44: romout <= 16'h70FF;
32'hFFFF2D46: romout <= 16'h4E75;
32'hFFFF2D48: romout <= 16'h2038;
32'hFFFF2D4A: romout <= 16'h0628;
32'hFFFF2D4C: romout <= 16'h90B8;
32'hFFFF2D4E: romout <= 16'h0624;
32'hFFFF2D50: romout <= 16'h4E75;
32'hFFFF2D52: romout <= 16'h2038;
32'hFFFF2D54: romout <= 16'h0400;
32'hFFFF2D56: romout <= 16'h4E75;
32'hFFFF2D58: romout <= 16'h6100;
32'hFFFF2D5A: romout <= 16'hF154;
32'hFFFF2D5C: romout <= 16'h0280;
32'hFFFF2D5E: romout <= 16'h0000;
32'hFFFF2D60: romout <= 16'hFFFF;
32'hFFFF2D62: romout <= 16'h4E75;
32'hFFFF2D64: romout <= 16'h6100;
32'hFFFF2D66: romout <= 16'hFE90;
32'hFFFF2D68: romout <= 16'h653A;
32'hFFFF2D6A: romout <= 16'h2F00;
32'hFFFF2D6C: romout <= 16'h6100;
32'hFFFF2D6E: romout <= 16'h0264;
32'hFFFF2D70: romout <= 16'h3D0B;
32'hFFFF2D72: romout <= 16'h6100;
32'hFFFF2D74: romout <= 16'hFD36;
32'hFFFF2D76: romout <= 16'h2C5F;
32'hFFFF2D78: romout <= 16'h2C80;
32'hFFFF2D7A: romout <= 16'h4E75;
32'hFFFF2D7C: romout <= 16'h6026;
32'hFFFF2D7E: romout <= 16'h6100;
32'hFFFF2D80: romout <= 16'h0252;
32'hFFFF2D82: romout <= 16'h3A07;
32'hFFFF2D84: romout <= 16'h588F;
32'hFFFF2D86: romout <= 16'h6000;
32'hFFFF2D88: romout <= 16'hF904;
32'hFFFF2D8A: romout <= 16'h6100;
32'hFFFF2D8C: romout <= 16'h0246;
32'hFFFF2D8E: romout <= 16'h0D07;
32'hFFFF2D90: romout <= 16'h588F;
32'hFFFF2D92: romout <= 16'h6000;
32'hFFFF2D94: romout <= 16'hF8DC;
32'hFFFF2D96: romout <= 16'h4E75;
32'hFFFF2D98: romout <= 16'h6100;
32'hFFFF2D9A: romout <= 16'h028A;
32'hFFFF2D9C: romout <= 16'h0C10;
32'hFFFF2D9E: romout <= 16'h000D;
32'hFFFF2DA0: romout <= 16'h6602;
32'hFFFF2DA2: romout <= 16'h4E75;
32'hFFFF2DA4: romout <= 16'h2F08;
32'hFFFF2DA6: romout <= 16'h4DF9;
32'hFFFF2DA8: romout <= 16'hFFFF;
32'hFFFF2DAA: romout <= 16'h312C;
32'hFFFF2DAC: romout <= 16'h6100;
32'hFFFF2DAE: romout <= 16'h02E6;
32'hFFFF2DB0: romout <= 16'h205F;
32'hFFFF2DB2: romout <= 16'h2038;
32'hFFFF2DB4: romout <= 16'h0604;
32'hFFFF2DB6: romout <= 16'h6700;
32'hFFFF2DB8: romout <= 16'hF6A8;
32'hFFFF2DBA: romout <= 16'hB0BC;
32'hFFFF2DBC: romout <= 16'hFFFF;
32'hFFFF2DBE: romout <= 16'hFFFF;
32'hFFFF2DC0: romout <= 16'h6700;
32'hFFFF2DC2: romout <= 16'hFAAA;
32'hFFFF2DC4: romout <= 16'h1F10;
32'hFFFF2DC6: romout <= 16'h4210;
32'hFFFF2DC8: romout <= 16'h2278;
32'hFFFF2DCA: romout <= 16'h0604;
32'hFFFF2DCC: romout <= 16'h6100;
32'hFFFF2DCE: romout <= 16'h01E8;
32'hFFFF2DD0: romout <= 16'h109F;
32'hFFFF2DD2: romout <= 16'h103C;
32'hFFFF2DD4: romout <= 16'h003F;
32'hFFFF2DD6: romout <= 16'h6100;
32'hFFFF2DD8: romout <= 16'hF630;
32'hFFFF2DDA: romout <= 16'h4280;
32'hFFFF2DDC: romout <= 16'h5389;
32'hFFFF2DDE: romout <= 16'h6100;
32'hFFFF2DE0: romout <= 16'h013E;
32'hFFFF2DE2: romout <= 16'h6000;
32'hFFFF2DE4: romout <= 16'hF67C;
32'hFFFF2DE6: romout <= 16'h2F08;
32'hFFFF2DE8: romout <= 16'h4DF9;
32'hFFFF2DEA: romout <= 16'hFFFF;
32'hFFFF2DEC: romout <= 16'h3134;
32'hFFFF2DEE: romout <= 16'h60BC;
32'hFFFF2DF0: romout <= 16'h2F08;
32'hFFFF2DF2: romout <= 16'h4DF9;
32'hFFFF2DF4: romout <= 16'hFFFF;
32'hFFFF2DF6: romout <= 16'h3125;
32'hFFFF2DF8: romout <= 16'h60B2;
32'hFFFF2DFA: romout <= 16'h6100;
32'hFFFF2DFC: romout <= 16'hF60C;
32'hFFFF2DFE: romout <= 16'h103C;
32'hFFFF2E00: romout <= 16'h0020;
32'hFFFF2E02: romout <= 16'h6100;
32'hFFFF2E04: romout <= 16'hF604;
32'hFFFF2E06: romout <= 16'h41F8;
32'hFFFF2E08: romout <= 16'h0630;
32'hFFFF2E0A: romout <= 16'h6100;
32'hFFFF2E0C: romout <= 16'h0270;
32'hFFFF2E0E: romout <= 16'h67FA;
32'hFFFF2E10: romout <= 16'hB03C;
32'hFFFF2E12: romout <= 16'h0008;
32'hFFFF2E14: romout <= 16'h6726;
32'hFFFF2E16: romout <= 16'hB03C;
32'hFFFF2E18: romout <= 16'h0018;
32'hFFFF2E1A: romout <= 16'h6744;
32'hFFFF2E1C: romout <= 16'hB03C;
32'hFFFF2E1E: romout <= 16'h000D;
32'hFFFF2E20: romout <= 16'h6706;
32'hFFFF2E22: romout <= 16'hB03C;
32'hFFFF2E24: romout <= 16'h0020;
32'hFFFF2E26: romout <= 16'h65E2;
32'hFFFF2E28: romout <= 16'h10C0;
32'hFFFF2E2A: romout <= 16'h6100;
32'hFFFF2E2C: romout <= 16'hF5DC;
32'hFFFF2E2E: romout <= 16'hB03C;
32'hFFFF2E30: romout <= 16'h000D;
32'hFFFF2E32: romout <= 16'h675C;
32'hFFFF2E34: romout <= 16'hB1FC;
32'hFFFF2E36: romout <= 16'h0000;
32'hFFFF2E38: romout <= 16'h067F;
32'hFFFF2E3A: romout <= 16'h65CE;
32'hFFFF2E3C: romout <= 16'h103C;
32'hFFFF2E3E: romout <= 16'h0008;
32'hFFFF2E40: romout <= 16'h6100;
32'hFFFF2E42: romout <= 16'hF5C6;
32'hFFFF2E44: romout <= 16'h103C;
32'hFFFF2E46: romout <= 16'h0020;
32'hFFFF2E48: romout <= 16'h6100;
32'hFFFF2E4A: romout <= 16'hF5BE;
32'hFFFF2E4C: romout <= 16'hB1FC;
32'hFFFF2E4E: romout <= 16'h0000;
32'hFFFF2E50: romout <= 16'h0630;
32'hFFFF2E52: romout <= 16'h63B6;
32'hFFFF2E54: romout <= 16'h103C;
32'hFFFF2E56: romout <= 16'h0008;
32'hFFFF2E58: romout <= 16'h6100;
32'hFFFF2E5A: romout <= 16'hF5AE;
32'hFFFF2E5C: romout <= 16'h5388;
32'hFFFF2E5E: romout <= 16'h60AA;
32'hFFFF2E60: romout <= 16'h2208;
32'hFFFF2E62: romout <= 16'h0481;
32'hFFFF2E64: romout <= 16'h0000;
32'hFFFF2E66: romout <= 16'h0630;
32'hFFFF2E68: romout <= 16'h671E;
32'hFFFF2E6A: romout <= 16'h5381;
32'hFFFF2E6C: romout <= 16'h103C;
32'hFFFF2E6E: romout <= 16'h0008;
32'hFFFF2E70: romout <= 16'h6100;
32'hFFFF2E72: romout <= 16'hF596;
32'hFFFF2E74: romout <= 16'h103C;
32'hFFFF2E76: romout <= 16'h0020;
32'hFFFF2E78: romout <= 16'h6100;
32'hFFFF2E7A: romout <= 16'hF58E;
32'hFFFF2E7C: romout <= 16'h103C;
32'hFFFF2E7E: romout <= 16'h0008;
32'hFFFF2E80: romout <= 16'h6100;
32'hFFFF2E82: romout <= 16'hF586;
32'hFFFF2E84: romout <= 16'h51C9;
32'hFFFF2E86: romout <= 16'hFFE6;
32'hFFFF2E88: romout <= 16'h41F8;
32'hFFFF2E8A: romout <= 16'h0630;
32'hFFFF2E8C: romout <= 16'h6000;
32'hFFFF2E8E: romout <= 16'hFF7C;
32'hFFFF2E90: romout <= 16'h103C;
32'hFFFF2E92: romout <= 16'h000A;
32'hFFFF2E94: romout <= 16'h6100;
32'hFFFF2E96: romout <= 16'hF572;
32'hFFFF2E98: romout <= 16'h4E75;
32'hFFFF2E9A: romout <= 16'hB2BC;
32'hFFFF2E9C: romout <= 16'h0000;
32'hFFFF2E9E: romout <= 16'hFFFF;
32'hFFFF2EA0: romout <= 16'h6400;
32'hFFFF2EA2: romout <= 16'hFF4E;
32'hFFFF2EA4: romout <= 16'h2279;
32'hFFFF2EA6: romout <= 16'hFFFF;
32'hFFFF2EA8: romout <= 16'h241C;
32'hFFFF2EAA: romout <= 16'h2478;
32'hFFFF2EAC: romout <= 16'h0624;
32'hFFFF2EAE: romout <= 16'h538A;
32'hFFFF2EB0: romout <= 16'hB5C9;
32'hFFFF2EB2: romout <= 16'h650C;
32'hFFFF2EB4: romout <= 16'h1411;
32'hFFFF2EB6: romout <= 16'hE14A;
32'hFFFF2EB8: romout <= 16'h1429;
32'hFFFF2EBA: romout <= 16'h0001;
32'hFFFF2EBC: romout <= 16'hB441;
32'hFFFF2EBE: romout <= 16'h6502;
32'hFFFF2EC0: romout <= 16'h4E75;
32'hFFFF2EC2: romout <= 16'h5489;
32'hFFFF2EC4: romout <= 16'h0C19;
32'hFFFF2EC6: romout <= 16'h000D;
32'hFFFF2EC8: romout <= 16'h66FA;
32'hFFFF2ECA: romout <= 16'h60DE;
32'hFFFF2ECC: romout <= 16'hB7C9;
32'hFFFF2ECE: romout <= 16'h6704;
32'hFFFF2ED0: romout <= 16'h14D9;
32'hFFFF2ED2: romout <= 16'h60F8;
32'hFFFF2ED4: romout <= 16'h4E75;
32'hFFFF2ED6: romout <= 16'hB5C9;
32'hFFFF2ED8: romout <= 16'h67FA;
32'hFFFF2EDA: romout <= 16'h1721;
32'hFFFF2EDC: romout <= 16'h60F8;
32'hFFFF2EDE: romout <= 16'h2C5F;
32'hFFFF2EE0: romout <= 16'h21DF;
32'hFFFF2EE2: romout <= 16'h0610;
32'hFFFF2EE4: romout <= 16'h6710;
32'hFFFF2EE6: romout <= 16'h21DF;
32'hFFFF2EE8: romout <= 16'h0614;
32'hFFFF2EEA: romout <= 16'h21DF;
32'hFFFF2EEC: romout <= 16'h0618;
32'hFFFF2EEE: romout <= 16'h21DF;
32'hFFFF2EF0: romout <= 16'h061C;
32'hFFFF2EF2: romout <= 16'h21DF;
32'hFFFF2EF4: romout <= 16'h0620;
32'hFFFF2EF6: romout <= 16'h4ED6;
32'hFFFF2EF8: romout <= 16'h2238;
32'hFFFF2EFA: romout <= 16'h062C;
32'hFFFF2EFC: romout <= 16'h928F;
32'hFFFF2EFE: romout <= 16'h6400;
32'hFFFF2F00: romout <= 16'hFEE6;
32'hFFFF2F02: romout <= 16'h2C5F;
32'hFFFF2F04: romout <= 16'h2238;
32'hFFFF2F06: romout <= 16'h0610;
32'hFFFF2F08: romout <= 16'h6710;
32'hFFFF2F0A: romout <= 16'h2F38;
32'hFFFF2F0C: romout <= 16'h0620;
32'hFFFF2F0E: romout <= 16'h2F38;
32'hFFFF2F10: romout <= 16'h061C;
32'hFFFF2F12: romout <= 16'h2F38;
32'hFFFF2F14: romout <= 16'h0618;
32'hFFFF2F16: romout <= 16'h2F38;
32'hFFFF2F18: romout <= 16'h0614;
32'hFFFF2F1A: romout <= 16'h2F01;
32'hFFFF2F1C: romout <= 16'h4ED6;
32'hFFFF2F1E: romout <= 16'h1200;
32'hFFFF2F20: romout <= 16'h1019;
32'hFFFF2F22: romout <= 16'hB200;
32'hFFFF2F24: romout <= 16'h6712;
32'hFFFF2F26: romout <= 16'h6100;
32'hFFFF2F28: romout <= 16'hF4E0;
32'hFFFF2F2A: romout <= 16'hB03C;
32'hFFFF2F2C: romout <= 16'h000D;
32'hFFFF2F2E: romout <= 16'h66F0;
32'hFFFF2F30: romout <= 16'h103C;
32'hFFFF2F32: romout <= 16'h000A;
32'hFFFF2F34: romout <= 16'h6100;
32'hFFFF2F36: romout <= 16'hF4D2;
32'hFFFF2F38: romout <= 16'h4E75;
32'hFFFF2F3A: romout <= 16'h6100;
32'hFFFF2F3C: romout <= 16'h0096;
32'hFFFF2F3E: romout <= 16'h221B;
32'hFFFF2F40: romout <= 16'h103C;
32'hFFFF2F42: romout <= 16'h0022;
32'hFFFF2F44: romout <= 16'h2248;
32'hFFFF2F46: romout <= 16'h6100;
32'hFFFF2F48: romout <= 16'hFFD6;
32'hFFFF2F4A: romout <= 16'h2049;
32'hFFFF2F4C: romout <= 16'h225F;
32'hFFFF2F4E: romout <= 16'hB03C;
32'hFFFF2F50: romout <= 16'h000A;
32'hFFFF2F52: romout <= 16'h6700;
32'hFFFF2F54: romout <= 16'hF71C;
32'hFFFF2F56: romout <= 16'h5489;
32'hFFFF2F58: romout <= 16'h4ED1;
32'hFFFF2F5A: romout <= 16'h6100;
32'hFFFF2F5C: romout <= 16'h0076;
32'hFFFF2F5E: romout <= 16'h2707;
32'hFFFF2F60: romout <= 16'h103C;
32'hFFFF2F62: romout <= 16'h0027;
32'hFFFF2F64: romout <= 16'h60DE;
32'hFFFF2F66: romout <= 16'h6100;
32'hFFFF2F68: romout <= 16'h006A;
32'hFFFF2F6A: romout <= 16'h5F0D;
32'hFFFF2F6C: romout <= 16'h103C;
32'hFFFF2F6E: romout <= 16'h000D;
32'hFFFF2F70: romout <= 16'h6100;
32'hFFFF2F72: romout <= 16'hF496;
32'hFFFF2F74: romout <= 16'h225F;
32'hFFFF2F76: romout <= 16'h60DE;
32'hFFFF2F78: romout <= 16'h4E75;
32'hFFFF2F7A: romout <= 16'h48E7;
32'hFFFF2F7C: romout <= 16'hC844;
32'hFFFF2F7E: romout <= 16'h4BF8;
32'hFFFF2F80: romout <= 16'h0700;
32'hFFFF2F82: romout <= 16'h2001;
32'hFFFF2F84: romout <= 16'h4EB9;
32'hFFFF2F86: romout <= 16'hFFFF;
32'hFFFF2F88: romout <= 16'h313E;
32'hFFFF2F8A: romout <= 16'h4BF8;
32'hFFFF2F8C: romout <= 16'h0700;
32'hFFFF2F8E: romout <= 16'h101D;
32'hFFFF2F90: romout <= 16'h6704;
32'hFFFF2F92: romout <= 16'h51CC;
32'hFFFF2F94: romout <= 16'hFFFA;
32'hFFFF2F96: romout <= 16'h4A44;
32'hFFFF2F98: romout <= 16'h6B0C;
32'hFFFF2F9A: romout <= 16'h103C;
32'hFFFF2F9C: romout <= 16'h0020;
32'hFFFF2F9E: romout <= 16'h6100;
32'hFFFF2FA0: romout <= 16'hF468;
32'hFFFF2FA2: romout <= 16'h51CC;
32'hFFFF2FA4: romout <= 16'hFFF2;
32'hFFFF2FA6: romout <= 16'h43F8;
32'hFFFF2FA8: romout <= 16'h0700;
32'hFFFF2FAA: romout <= 16'h4EB9;
32'hFFFF2FAC: romout <= 16'hFFFF;
32'hFFFF2FAE: romout <= 16'h1858;
32'hFFFF2FB0: romout <= 16'h4CDF;
32'hFFFF2FB2: romout <= 16'h2213;
32'hFFFF2FB4: romout <= 16'h4E75;
32'hFFFF2FB6: romout <= 16'h4281;
32'hFFFF2FB8: romout <= 16'h1219;
32'hFFFF2FBA: romout <= 16'hE189;
32'hFFFF2FBC: romout <= 16'h1219;
32'hFFFF2FBE: romout <= 16'h7805;
32'hFFFF2FC0: romout <= 16'h6100;
32'hFFFF2FC2: romout <= 16'hFFB8;
32'hFFFF2FC4: romout <= 16'h103C;
32'hFFFF2FC6: romout <= 16'h0020;
32'hFFFF2FC8: romout <= 16'h6100;
32'hFFFF2FCA: romout <= 16'hF43E;
32'hFFFF2FCC: romout <= 16'h4280;
32'hFFFF2FCE: romout <= 16'h6000;
32'hFFFF2FD0: romout <= 16'hFF4E;
32'hFFFF2FD2: romout <= 16'h6100;
32'hFFFF2FD4: romout <= 16'h0050;
32'hFFFF2FD6: romout <= 16'h225F;
32'hFFFF2FD8: romout <= 16'h1219;
32'hFFFF2FDA: romout <= 16'hB210;
32'hFFFF2FDC: romout <= 16'h6708;
32'hFFFF2FDE: romout <= 16'h4281;
32'hFFFF2FE0: romout <= 16'h1211;
32'hFFFF2FE2: romout <= 16'hD3C1;
32'hFFFF2FE4: romout <= 16'h4ED1;
32'hFFFF2FE6: romout <= 16'h5288;
32'hFFFF2FE8: romout <= 16'h5289;
32'hFFFF2FEA: romout <= 16'h4ED1;
32'hFFFF2FEC: romout <= 16'h4281;
32'hFFFF2FEE: romout <= 16'h4282;
32'hFFFF2FF0: romout <= 16'h6100;
32'hFFFF2FF2: romout <= 16'h0032;
32'hFFFF2FF4: romout <= 16'h0C10;
32'hFFFF2FF6: romout <= 16'h0030;
32'hFFFF2FF8: romout <= 16'h6528;
32'hFFFF2FFA: romout <= 16'h0C10;
32'hFFFF2FFC: romout <= 16'h0039;
32'hFFFF2FFE: romout <= 16'h6222;
32'hFFFF3000: romout <= 16'hB2BC;
32'hFFFF3002: romout <= 16'h0CCC;
32'hFFFF3004: romout <= 16'hCCCC;
32'hFFFF3006: romout <= 16'h6400;
32'hFFFF3008: romout <= 16'hFDE8;
32'hFFFF300A: romout <= 16'h2001;
32'hFFFF300C: romout <= 16'hD281;
32'hFFFF300E: romout <= 16'hD281;
32'hFFFF3010: romout <= 16'hD280;
32'hFFFF3012: romout <= 16'hD281;
32'hFFFF3014: romout <= 16'h1018;
32'hFFFF3016: romout <= 16'h0280;
32'hFFFF3018: romout <= 16'h0000;
32'hFFFF301A: romout <= 16'h000F;
32'hFFFF301C: romout <= 16'hD280;
32'hFFFF301E: romout <= 16'h5282;
32'hFFFF3020: romout <= 16'h60D2;
32'hFFFF3022: romout <= 16'h4E75;
32'hFFFF3024: romout <= 16'h0C10;
32'hFFFF3026: romout <= 16'h0020;
32'hFFFF3028: romout <= 16'h6604;
32'hFFFF302A: romout <= 16'h5288;
32'hFFFF302C: romout <= 16'h60F6;
32'hFFFF302E: romout <= 16'h4E75;
32'hFFFF3030: romout <= 16'h41F8;
32'hFFFF3032: romout <= 16'h0630;
32'hFFFF3034: romout <= 16'h4201;
32'hFFFF3036: romout <= 16'h1018;
32'hFFFF3038: romout <= 16'hB03C;
32'hFFFF303A: romout <= 16'h000D;
32'hFFFF303C: romout <= 16'h671A;
32'hFFFF303E: romout <= 16'hB03C;
32'hFFFF3040: romout <= 16'h0022;
32'hFFFF3042: romout <= 16'h6716;
32'hFFFF3044: romout <= 16'hB03C;
32'hFFFF3046: romout <= 16'h0027;
32'hFFFF3048: romout <= 16'h6710;
32'hFFFF304A: romout <= 16'h4A01;
32'hFFFF304C: romout <= 16'h66E8;
32'hFFFF304E: romout <= 16'h6100;
32'hFFFF3050: romout <= 16'h001A;
32'hFFFF3052: romout <= 16'h1100;
32'hFFFF3054: romout <= 16'h5288;
32'hFFFF3056: romout <= 16'h60DE;
32'hFFFF3058: romout <= 16'h4E75;
32'hFFFF305A: romout <= 16'h4A01;
32'hFFFF305C: romout <= 16'h6604;
32'hFFFF305E: romout <= 16'h1200;
32'hFFFF3060: romout <= 16'h60D4;
32'hFFFF3062: romout <= 16'hB200;
32'hFFFF3064: romout <= 16'h66D0;
32'hFFFF3066: romout <= 16'h4201;
32'hFFFF3068: romout <= 16'h60CC;
32'hFFFF306A: romout <= 16'hB03C;
32'hFFFF306C: romout <= 16'h0061;
32'hFFFF306E: romout <= 16'h650A;
32'hFFFF3070: romout <= 16'hB03C;
32'hFFFF3072: romout <= 16'h007A;
32'hFFFF3074: romout <= 16'h6204;
32'hFFFF3076: romout <= 16'h0400;
32'hFFFF3078: romout <= 16'h0020;
32'hFFFF307A: romout <= 16'h4E75;
32'hFFFF307C: romout <= 16'h6100;
32'hFFFF307E: romout <= 16'hF38E;
32'hFFFF3080: romout <= 16'h670A;
32'hFFFF3082: romout <= 16'hB03C;
32'hFFFF3084: romout <= 16'h0003;
32'hFFFF3086: romout <= 16'h6604;
32'hFFFF3088: romout <= 16'h6000;
32'hFFFF308A: romout <= 16'hF3D6;
32'hFFFF308C: romout <= 16'h4E75;
32'hFFFF308E: romout <= 16'h4DF9;
32'hFFFF3090: romout <= 16'hFFFF;
32'hFFFF3092: romout <= 16'h313A;
32'hFFFF3094: romout <= 16'h101E;
32'hFFFF3096: romout <= 16'h6706;
32'hFFFF3098: romout <= 16'h6100;
32'hFFFF309A: romout <= 16'hF36E;
32'hFFFF309C: romout <= 16'h60F6;
32'hFFFF309E: romout <= 16'h4E75;
32'hFFFF30A0: romout <= 16'h48E7;
32'hFFFF30A2: romout <= 16'hC000;
32'hFFFF30A4: romout <= 16'h2200;
32'hFFFF30A6: romout <= 16'h4EB9;
32'hFFFF30A8: romout <= 16'hFFFF;
32'hFFFF30AA: romout <= 16'h1732;
32'hFFFF30AC: romout <= 16'h4CDF;
32'hFFFF30AE: romout <= 16'h0003;
32'hFFFF30B0: romout <= 16'h4E75;
32'hFFFF30B2: romout <= 16'h3039;
32'hFFFF30B4: romout <= 16'hFFDC;
32'hFFFF30B6: romout <= 16'h0000;
32'hFFFF30B8: romout <= 16'h6A0C;
32'hFFFF30BA: romout <= 16'h4279;
32'hFFFF30BC: romout <= 16'hFFDC;
32'hFFFF30BE: romout <= 16'h0002;
32'hFFFF30C0: romout <= 16'h0240;
32'hFFFF30C2: romout <= 16'h00FF;
32'hFFFF30C4: romout <= 16'h4E75;
32'hFFFF30C6: romout <= 16'h7000;
32'hFFFF30C8: romout <= 16'h4E75;
32'hFFFF30CA: romout <= 16'h0839;
32'hFFFF30CC: romout <= 16'h0005;
32'hFFFF30CE: romout <= 16'hFFDC;
32'hFFFF30D0: romout <= 16'h0A01;
32'hFFFF30D2: romout <= 16'h67F6;
32'hFFFF30D4: romout <= 16'h13C0;
32'hFFFF30D6: romout <= 16'hFFDC;
32'hFFFF30D8: romout <= 16'h0A00;
32'hFFFF30DA: romout <= 16'h4E75;
32'hFFFF30DC: romout <= 16'h0839;
32'hFFFF30DE: romout <= 16'h0000;
32'hFFFF30E0: romout <= 16'hFFDC;
32'hFFFF30E2: romout <= 16'h0A01;
32'hFFFF30E4: romout <= 16'h670A;
32'hFFFF30E6: romout <= 16'h1039;
32'hFFFF30E8: romout <= 16'hFFDC;
32'hFFFF30EA: romout <= 16'h0A00;
32'hFFFF30EC: romout <= 16'h0200;
32'hFFFF30EE: romout <= 16'h007F;
32'hFFFF30F0: romout <= 16'h4E75;
32'hFFFF30F2: romout <= 16'h4EF9;
32'hFFFF30F4: romout <= 16'hFFFF;
32'hFFFF30F6: romout <= 16'h1A7A;
32'hFFFF30F8: romout <= 16'h0D0A;
32'hFFFF30FA: romout <= 16'h476F;
32'hFFFF30FC: romout <= 16'h7264;
32'hFFFF30FE: romout <= 16'h6F27;
32'hFFFF3100: romout <= 16'h7320;
32'hFFFF3102: romout <= 16'h4D43;
32'hFFFF3104: romout <= 16'h3638;
32'hFFFF3106: romout <= 16'h3030;
32'hFFFF3108: romout <= 16'h3020;
32'hFFFF310A: romout <= 16'h5469;
32'hFFFF310C: romout <= 16'h6E79;
32'hFFFF310E: romout <= 16'h2042;
32'hFFFF3110: romout <= 16'h4153;
32'hFFFF3112: romout <= 16'h4943;
32'hFFFF3114: romout <= 16'h2C20;
32'hFFFF3116: romout <= 16'h7631;
32'hFFFF3118: romout <= 16'h2E33;
32'hFFFF311A: romout <= 16'h0D0A;
32'hFFFF311C: romout <= 16'h0A00;
32'hFFFF311E: romout <= 16'h0D0A;
32'hFFFF3120: romout <= 16'h4F4B;
32'hFFFF3122: romout <= 16'h0D0A;
32'hFFFF3124: romout <= 16'h0048;
32'hFFFF3126: romout <= 16'h6F77;
32'hFFFF3128: romout <= 16'h3F0D;
32'hFFFF312A: romout <= 16'h0A00;
32'hFFFF312C: romout <= 16'h5768;
32'hFFFF312E: romout <= 16'h6174;
32'hFFFF3130: romout <= 16'h3F0D;
32'hFFFF3132: romout <= 16'h0A00;
32'hFFFF3134: romout <= 16'h536F;
32'hFFFF3136: romout <= 16'h7272;
32'hFFFF3138: romout <= 16'h792E;
32'hFFFF313A: romout <= 16'h0D0A;
32'hFFFF313C: romout <= 16'h00FF;
32'hFFFF313E: romout <= 16'h48E7;
32'hFFFF3140: romout <= 16'h7F00;
32'hFFFF3142: romout <= 16'h2E00;
32'hFFFF3144: romout <= 16'h6A08;
32'hFFFF3146: romout <= 16'h4487;
32'hFFFF3148: romout <= 16'h6B4E;
32'hFFFF314A: romout <= 16'h1AFC;
32'hFFFF314C: romout <= 16'h002D;
32'hFFFF314E: romout <= 16'h4244;
32'hFFFF3150: romout <= 16'h7C0A;
32'hFFFF3152: romout <= 16'h7401;
32'hFFFF3154: romout <= 16'h2206;
32'hFFFF3156: romout <= 16'h5381;
32'hFFFF3158: romout <= 16'h671A;
32'hFFFF315A: romout <= 16'h3602;
32'hFFFF315C: romout <= 16'hC6FC;
32'hFFFF315E: romout <= 16'h000A;
32'hFFFF3160: romout <= 16'h4842;
32'hFFFF3162: romout <= 16'hC4FC;
32'hFFFF3164: romout <= 16'h000A;
32'hFFFF3166: romout <= 16'h4843;
32'hFFFF3168: romout <= 16'hD443;
32'hFFFF316A: romout <= 16'h4842;
32'hFFFF316C: romout <= 16'h4843;
32'hFFFF316E: romout <= 16'h3403;
32'hFFFF3170: romout <= 16'h5381;
32'hFFFF3172: romout <= 16'h66E6;
32'hFFFF3174: romout <= 16'h4280;
32'hFFFF3176: romout <= 16'hBE82;
32'hFFFF3178: romout <= 16'h6D06;
32'hFFFF317A: romout <= 16'h5280;
32'hFFFF317C: romout <= 16'h9E82;
32'hFFFF317E: romout <= 16'h60F6;
32'hFFFF3180: romout <= 16'h4A00;
32'hFFFF3182: romout <= 16'h6604;
32'hFFFF3184: romout <= 16'h4A44;
32'hFFFF3186: romout <= 16'h6708;
32'hFFFF3188: romout <= 16'h0600;
32'hFFFF318A: romout <= 16'h0030;
32'hFFFF318C: romout <= 16'h1AC0;
32'hFFFF318E: romout <= 16'h1800;
32'hFFFF3190: romout <= 16'h5386;
32'hFFFF3192: romout <= 16'h66BE;
32'hFFFF3194: romout <= 16'h4A44;
32'hFFFF3196: romout <= 16'h6604;
32'hFFFF3198: romout <= 16'h1AFC;
32'hFFFF319A: romout <= 16'h0030;
32'hFFFF319C: romout <= 16'h1ABC;
32'hFFFF319E: romout <= 16'h0000;
32'hFFFF31A0: romout <= 16'h4CDF;
32'hFFFF31A2: romout <= 16'h00FE;
32'hFFFF31A4: romout <= 16'h4E75;
default: romout <= 16'h0000;
endcase
always @(posedge clk)
romo <= romout;
endmodule
/trunk/rtl/verilog/rtfGraphicsAccelerator.v
0,0 → 1,240
`define NULL 8'd0
`define DRAW_PIXEL 8'd1
`define DRAW_LINE 8'd2
`define LINETO 8'd3
`define RECTANGLE 8'd4
`define RECTANGLE2 8'd5
`define RECTANGLE3 8'd6
`define RECTANGLE4 8'd7
 
module rtfGraphicsAccelerator (
rst_i,
clk_i,
 
s_cyc_i,
s_stb_i,
s_we_i,
s_ack_o,
s_sel_i,
s_adr_i,
s_dat_i,
s_dat_o,
 
m_cyc_o,
m_stb_o,
m_we_o,
m_ack_i,
m_sel_o,
m_adr_o,
m_dat_i,
m_dat_o
);
parameter PPL = 16'd416; // pixels per line
parameter IDLE = 8'd0;
parameter DRAWPIXEL = 8'd1;
parameter DL_SETPIXEL = 8'd2;
parameter DL_CALCE2 = 8'd3;
parameter DL_TEST = 8'd4;
parameter DL_TEST2 = 8'd5;
 
input rst_i;
input clk_i;
 
input s_cyc_i;
input s_stb_i;
output s_ack_o;
input s_we_i;
input [1:0] s_sel_i;
input [31:0] s_adr_i;
input [15:0] s_dat_i;
output [15:0] s_dat_o;
 
output m_cyc_o;
reg m_cyc_o;
output m_stb_o;
reg m_stb_o;
output m_we_o;
reg m_we_o;
input m_ack_i;
output [1:0] m_sel_o;
reg [1:0] m_sel_o;
output [31:0] m_adr_o;
reg [31:0] m_adr_o;
input [15:0] m_dat_i;
output [15:0] m_dat_o;
reg [15:0] m_dat_o;
 
reg [7:0] cmd;
reg ps; // pen select
reg [7:0] PenColor8;
reg [7:0] FillColor8;
reg [31:0] PenColor;
reg [31:0] FillColor;
reg [15:0] x0,y0,x1,y1;
reg [15:0] x0a,y0a,x1a,y1a;
 
reg [15:0] cx,cy; // graphics cursor position
wire [31:0] ma = 32'h020000 + cy * PPL + cx;
reg signed [15:0] dx,dy;
reg signed [15:0] sx,sy;
reg signed [15:0] err;
wire signed [15:0] e2 = err << 1;
reg [7:0] state;
 
wire cs = s_cyc_i && s_stb_i && (s_adr_i[31:8]==24'hFFDA_E0);
assign s_ack_o = cs;
 
always @(posedge clk_i)
if (rst_i) begin
x0 <= 16'd0;
y0 <= 16'd0;
x1 <= 16'd0;
y1 <= 16'd0;
cx <= 16'd0;
cy <= 16'd0;
state <= IDLE;
end
else begin
if (cs & s_we_i) begin
case(s_adr_i[4:1])
8'd0: begin PenColor[31:16] <= s_dat_i; PenColor8[7:5] <= s_dat_i[7:5]; end
8'd1: begin PenColor[15: 0] <= s_dat_i; PenColor8[4:2] <= s_dat_i[15:13]; PenColor8[1:0] <= s_dat_i[7:6]; end
8'd2: begin FillColor[31:16] <= s_dat_i; FillColor8[7:5] <= s_dat_i[7:5]; end
8'd3: begin FillColor[15: 0] <= s_dat_i; FillColor8[4:2] <= s_dat_i[15:13]; FillColor8[1:0] <= s_dat_i[7:6]; end
8'd4: x0 <= s_dat_i;
8'd5: y0 <= s_dat_i;
8'd6: x1 <= s_dat_i;
8'd7: y1 <= s_dat_i;
8'd15: cmd <= s_dat_i;
endcase
end
 
case(state)
IDLE:
begin
cx <= x0;
cy <= y0;
dx <= x1 < x0 ? x0-x1 : x1-x0;
dy <= y1 < y0 ? y0-y1 : y1-y0;
sx <= x0 < x1 ? 1 : -1;
sy <= y0 < y1 ? 1 : -1;
err <= dx-dy;
if (cmd==`DRAW_PIXEL) begin
state <= DRAWPIXEL;
cmd <= `NULL;
end
else if (cmd==`DRAW_LINE) begin
state <= DL_SETPIXEL;
cmd <= `NULL;
end
else if (cmd==`LINETO) begin
x1 <= x0;
y1 <= y0;
x0 <= cx;
y0 <= cy;
cmd <= `DRAW_LINE;
end
else if (cmd==`RECTANGLE) begin
x0a <= x0;
y0a <= y0;
x1a <= x1;
y1a <= y1;
y1 <= y0;
cmd <= `RECTANGLE2;
state <= DL_SETPIXEL;
end
else if (cmd==`RECTANGLE2) begin
x0 <= x1a;
y0 <= y0a;
x1 <= x1a;
y1 <= y1a;
cmd <= `RECTANGLE3;
state <= DL_SETPIXEL;
end
else if (cmd==`RECTANGLE3) begin
y0 <= y1a;
x0 <= x1a;
x1 <= x0a;
y1 <= y1a;
cmd <= `RECTANGLE4;
state <= DL_SETPIXEL;
end
else if (cmd==`RECTANGLE4) begin
x0 <= x0a;
y0 <= y1a;
x1 <= x0a;
y1 <= y0a;
cmd <= `NULL;
state <= DL_SETPIXEL;
end
end
 
DRAWPIXEL:
if (!m_cyc_o) begin
m_cyc_o <= 1'b1;
m_stb_o <= 1'b1;
m_we_o <= 1'b1;
m_sel_o <= {cx[0],~cx[0]};
m_adr_o <= ma;
m_dat_o <= {2{PenColor8}};
end
else if (m_ack_i) begin
m_cyc_o <= 1'b0;
m_stb_o <= 1'b0;
m_sel_o <= 2'b00;
m_we_o <= 1'b0;
state <= IDLE;
end
 
DL_SETPIXEL:
if (!m_cyc_o) begin
m_cyc_o <= 1'b1;
m_stb_o <= 1'b1;
m_we_o <= 1'b1;
m_sel_o <= {cx[0],~cx[0]};
m_adr_o <= ma;
m_dat_o <= {2{PenColor8}};
end
else if (m_ack_i) begin
m_cyc_o <= 1'b0;
m_stb_o <= 1'b0;
m_sel_o <= 2'b00;
m_we_o <= 1'b0;
if (cx==x1 && cy==y1)
state <= IDLE;
else
state <= DL_TEST;
end
DL_TEST:
begin
err <= err - ((e2 > -dy) ? dy : 16'd0) + ((e2 < dx) ? dx : 16'd0);
cx <= (e2 > -dy) ? cx + sx : cx;
cy <= (e2 < dx) ? cy + sy : cy;
state <= DL_SETPIXEL;
end
 
endcase
end
 
endmodule
 
//function line(x0, y0, x1, y1)
// dx := abs(x1-x0)
// dy := abs(y1-y0)
//; if x0 < x1 then sx := 1 else sx := -1
//; if y0 < y1 then sy := 1 else sy := -1
//; err := dx-dy
//;
//;// loop
//; setPixel(x0,y0)
//; if x0 = x1 and y0 = y1 exit loop
//; e2 := 2*err
//; if e2 > -dy then
//; err := err - dy
//; x0 := x0 + sx
//; end if
//; if e2 < dx then
//; err := err + dx
//; y0 := y0 + sy
//; end if
//; end loop
/trunk/rtl/verilog/rtfSpriteRam.v
0,0 → 1,85
// ============================================================================
// Sprite RAM
//
// (C) 2005,2011 Robert Finch
// robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
 
//`define VENDOR_ANY
`define VENDOR_XILINX
`define SPARTAN3
 
module rtfSpriteRam(
clka, adra, dia, doa, cea, wea, rsta,
clkb, adrb, dib, dob, ceb, web, rstb);
parameter pAw = 10;
parameter pDw = 16;
input clka;
input [pAw:1] adra;
input [pDw:1] dia;
output [pDw:1] doa;
input cea; // clock enable a
input wea;
input rsta;
input clkb;
input [pAw:1] adrb;
input [pDw:1] dib;
output [pDw:1] dob;
input ceb; // clock enable b
input web;
input rstb;
 
`ifdef VENDOR_XILINX
 
`ifdef SPARTAN3
// could use an S16_S32
RAMB16_S18_S18 ram0(
.CLKA(clka), .ADDRA(adra), .DIA(dia), .DIPA(2'b11), .DOA(doa), .ENA(cea), .WEA(wea), .SSRA(rsta),
.CLKB(clkb), .ADDRB(adrb), .DIB(dib), .DIPB(2'b11), .DOB(dob), .ENB(ceb), .WEB(web), .SSRB(rstb) );
`else
// could use an S8_S16
RAMB4_S8_S8 ram0(
.CLKA(clka), .ADDRA(adra), .DIA(dia), .DOA(doa), .ENA(cea), .WEA(wea), .RSTA(rsta),
.CLKB(clkb), .ADDRB(adrb), .DIB(dib), .DOB(dob), .ENB(ceb), .WEB(web), .RSTB(rstb) );
`endif
`endif
 
`ifdef VENDOR_ALTERA
`endif
 
`ifdef VENDOR_ANY
 
reg [15:0] mem [(1<<pAw):1];
reg [pAw:1] radra;
reg [pAw:1] radrb;
 
// register read addresses
always @(posedge clka)
if (cea)
radra <= adra;
 
always @(posedge clkb)
if (ceb)
if (web)
mem[adrb] <= dib;
 
assign doa = mem[radra];
 
`endif
 
endmodule
/trunk/rtl/verilog/VT163.v
0,0 → 1,50
// ============================================================================
// 2007 Robert Finch
// robfinch@<remove>sympatico.ca
//
// VT163 - 74LS163 counter
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// Webpack 9.1i xc3s1000-4ft256
// 4 slices / 8 LUTs / 324.675 MHz
 
module VT163(clk, clr_n, ent, enp, ld_n, d, q, rco);
parameter WID=4;
input clk;
input clr_n; // clear active low
input ent; // clock enable
input enp; // clock enable
input ld_n; // load active low
input [WID:1] d;
output [WID:1] q;
reg [WID:1] q;
output rco;
 
assign rco = &{q[WID:1],ent};
 
always @(posedge clk)
begin
if (!clr_n)
q <= {WID{1'b0}};
else if (!ld_n)
q <= d;
else if (enp & ent)
q <= q + {{WID-1{1'b0}},1'b1};
end
 
endmodule
/trunk/rtl/verilog/PS2ScanToAscii.v
0,0 → 1,246
// ============================================================================
// Scan Code Converter
// - Convert PS2 style scancodes to ascii
//
// 2010 Robert Finch
// robfinch<remove>@FPGAfield.ca
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// Convert a PS2 scancode to ascii
//
// Verilog 1995
// Webpack 9.2i xc3s1200-4fg320
// 86 slices / 151 LUTs / 13.164 ns
//
// ============================================================================
 
module PS2ScanToAscii(shift, ctrl, alt, extend, sc, ascii);
input shift; // shift indicator
input ctrl;
input alt;
input extend; // extended scancode
input [7:0] sc; // scan code
output [7:0] ascii; // acsii equivalent
reg [7:0] ascii;
 
 
always @(sc or shift or ctrl or extend)
begin
if (extend) begin
case (sc)
8'h75: ascii <= 8'h90; // up
8'h74: ascii <= 8'h91; // right
8'h72: ascii <= 8'h92; // down
8'h6b: ascii <= 8'h93; // left
8'h6c: ascii <= 8'h94; // home
8'h69: ascii <= 8'h95; // end
8'h7d: ascii <= 8'h96; // pg up
8'h7a: ascii <= 8'h97; // pg down
8'h70: ascii <= 8'h98; // insert
8'h71: ascii <= 8'h99; // delete
8'h05: ascii <= 8'ha1; // F1
8'h06: ascii <= 8'ha2; // F2
8'h04: ascii <= 8'ha3; // F3
default: ascii <= 8'h2e;
endcase
end
else if (ctrl) begin
case (sc)
8'h0d: ascii <= 8'h09;
8'h0e: ascii <= 8'h7e; // ~
8'h15: ascii <= 8'h11; // Q
8'h16: ascii <= 8'h21; // !
8'h1b: ascii <= 8'h13; // S
8'h1a: ascii <= 8'h1a; // Z
8'h1c: ascii <= 8'h01; // A
8'h1d: ascii <= 8'h17; // W
8'h1e: ascii <= 8'h40; // @
8'h21: ascii <= 8'h03; // C
8'h22: ascii <= 8'h18; // X
8'h23: ascii <= 8'h04; // D
8'h24: ascii <= 8'h05; // E
8'h25: ascii <= 8'h24; // $
8'h26: ascii <= 8'h23; // #
8'h29: ascii <= 8'h20; // space
8'h2a: ascii <= 8'h16; // V
8'h2b: ascii <= 8'h06; // F
8'h2c: ascii <= 8'h14; // T
8'h2d: ascii <= 8'h12; // R
8'h2e: ascii <= 8'h25; // %
8'h31: ascii <= 8'h0e; // N
8'h32: ascii <= 8'h02; // B
8'h33: ascii <= 8'h08; // H
8'h34: ascii <= 8'h07; // G
8'h35: ascii <= 8'h19; // Y
8'h36: ascii <= 8'h5e; // ^
8'h3a: ascii <= 8'h0d; // M
8'h3b: ascii <= 8'h0a; // J
8'h3c: ascii <= 8'h15; // U
8'h3d: ascii <= 8'h26; // &
8'h3e: ascii <= 8'h2a; // *
8'h41: ascii <= 8'h3c; // <
8'h42: ascii <= 8'h0b; // K
8'h43: ascii <= 8'h09; // I
8'h44: ascii <= 8'h0f; // O
8'h45: ascii <= 8'h29; // )
8'h46: ascii <= 8'h28; // (
8'h49: ascii <= 8'h3e; // >
8'h4a: ascii <= 8'h3f; // ?
8'h4b: ascii <= 8'h0c; // L
8'h4c: ascii <= 8'h3a; // :
8'h4d: ascii <= 8'h10; // P
8'h4e: ascii <= 8'h5f; // _
8'h52: ascii <= 8'h22; // "
8'h54: ascii <= 8'h7b; // {
8'h55: ascii <= 8'h2b; // +
8'h5a: ascii <= 8'h0d;
8'h5b: ascii <= 8'h7d; // }
8'h5d: ascii <= 8'h7c; // |
8'h66: ascii <= 8'h08;
8'h76: ascii <= 8'h1b;
8'h71: ascii <= 8'h7f; // del
default: ascii <= 8'h2e;
endcase
end
else if (shift) begin
case (sc)
8'h0d: ascii <= 8'h09;
8'h0e: ascii <= 8'h7e; // ~
8'h15: ascii <= 8'h51; // Q
8'h16: ascii <= 8'h21; // !
8'h1b: ascii <= 8'h53; // S
8'h1a: ascii <= 8'h5a; // Z
8'h1c: ascii <= 8'h41; // A
8'h1d: ascii <= 8'h57; // W
8'h1e: ascii <= 8'h40; // @
8'h21: ascii <= 8'h43; // C
8'h22: ascii <= 8'h58; // X
8'h23: ascii <= 8'h44; // D
8'h24: ascii <= 8'h45; // E
8'h25: ascii <= 8'h24; // $
8'h26: ascii <= 8'h23; // #
8'h29: ascii <= 8'h20; // space
8'h2a: ascii <= 8'h56; // V
8'h2b: ascii <= 8'h46; // F
8'h2c: ascii <= 8'h54; // T
8'h2d: ascii <= 8'h52; // R
8'h2e: ascii <= 8'h25; // %
8'h31: ascii <= 8'h4e; // N
8'h32: ascii <= 8'h42; // B
8'h33: ascii <= 8'h48; // H
8'h34: ascii <= 8'h47; // G
8'h35: ascii <= 8'h59; // Y
8'h36: ascii <= 8'h5e; // ^
8'h3a: ascii <= 8'h4d; // M
8'h3b: ascii <= 8'h4a; // J
8'h3c: ascii <= 8'h55; // U
8'h3d: ascii <= 8'h26; // &
8'h3e: ascii <= 8'h2a; // *
8'h41: ascii <= 8'h3c; // <
8'h42: ascii <= 8'h4b; // K
8'h43: ascii <= 8'h49; // I
8'h44: ascii <= 8'h4f; // O
8'h45: ascii <= 8'h29; // )
8'h46: ascii <= 8'h28; // (
8'h49: ascii <= 8'h3e; // >
8'h4a: ascii <= 8'h3f; // ?
8'h4b: ascii <= 8'h4c; // L
8'h4c: ascii <= 8'h3a; // :
8'h4d: ascii <= 8'h50; // P
8'h4e: ascii <= 8'h5f; // _
8'h52: ascii <= 8'h22; // "
8'h54: ascii <= 8'h7b; // {
8'h55: ascii <= 8'h2b; // +
8'h5a: ascii <= 8'h0d;
8'h5b: ascii <= 8'h7d; // }
8'h5d: ascii <= 8'h7c; // |
8'h66: ascii <= 8'h08;
8'h76: ascii <= 8'h1b;
8'h71: ascii <= 8'h7f; // del
default: ascii <= 8'h2e;
endcase
end
else begin
case (sc)
8'h0d: ascii <= 8'h09; // tab
8'h0e: ascii <= 8'h60; // `
8'h15: ascii <= 8'h71; // q
8'h16: ascii <= 8'h31; // 1
8'h1a: ascii <= 8'h7a; // z
8'h1b: ascii <= 8'h73; // s
8'h1c: ascii <= 8'h61; // a
8'h1d: ascii <= 8'h77; // w
8'h1e: ascii <= 8'h32; // 2
8'h21: ascii <= 8'h63; // c
8'h22: ascii <= 8'h78; // x
8'h23: ascii <= 8'h64; // d
8'h24: ascii <= 8'h65; // e
8'h25: ascii <= 8'h34; // 4
8'h26: ascii <= 8'h33; // 3
8'h29: ascii <= 8'h20; // space
8'h2a: ascii <= 8'h76; // v
8'h2b: ascii <= 8'h66; // f
8'h2c: ascii <= 8'h74; // t
8'h2d: ascii <= 8'h72; // r
8'h2e: ascii <= 8'h35; // 5
8'h31: ascii <= 8'h6e; // n
8'h32: ascii <= 8'h62; // b
8'h33: ascii <= 8'h68; // h
8'h34: ascii <= 8'h67; // g
8'h35: ascii <= 8'h79; // y
8'h36: ascii <= 8'h36; // 6
8'h3a: ascii <= 8'h6d; // m
8'h3b: ascii <= 8'h6a; // j
8'h3c: ascii <= 8'h75; // u
8'h3d: ascii <= 8'h37; // 7
8'h3e: ascii <= 8'h38; // 8
8'h41: ascii <= 8'h2c; // ,
8'h42: ascii <= 8'h6b; // k
8'h43: ascii <= 8'h69; // i
8'h44: ascii <= 8'h6f; // o
8'h45: ascii <= 8'h30; // 0
8'h46: ascii <= 8'h39; // 9
8'h49: ascii <= 8'h2e; // .
8'h4a: ascii <= 8'h2f; // /
8'h4b: ascii <= 8'h6c; // l
8'h4c: ascii <= 8'h3b; // ;
8'h4d: ascii <= 8'h70; // p
8'h4e: ascii <= 8'h2d; // -
8'h52: ascii <= 8'h27; // '
8'h54: ascii <= 8'h5b; // [
8'h55: ascii <= 8'h3d; // =
8'h5a: ascii <= 8'h0d; // carriage return
8'h5b: ascii <= 8'h5d; // ]
8'h5d: ascii <= 8'h5c; // \
8'h63: ascii <= 8'h90; // up {set 3}
8'h66: ascii <= 8'h08; // backspace
8'h71: ascii <= 8'h7f; // del
8'h76: ascii <= 8'h1b; // escape
default: ascii <= 8'h2e; // '.' used for unlisted characters.
endcase
end
end
 
endmodule
/trunk/rtl/verilog/rtfSpriteController.v
0,0 → 1,869
/* ===============================================================
(C) 2005 Robert Finch
All rights reserved.
robfinch@opencores.org
 
rtfSpriteController.v
sprite / hardware cursor controller
 
This source code is free for use and modification for
non-commercial or evaluation purposes, provided this
copyright statement and disclaimer remains present in
the file.
 
If you do modify the code, please state the origin and
note that you have modified the code.
 
NO WARRANTY.
THIS Work, IS PROVIDED "AS IS" WITH NO WARRANTIES OF
ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
the entire risk of using the Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
USE.
 
 
Sprite Controller
 
FEATURES
- parameterized number of sprites
- eight sprite image cache buffers
- each image cache is capable of holding multiple
sprite images
- cache may be accessed like a memory by the processor
- an embedded DMA controller may also be used for
sprite reload
- programmable image offset within cache
- programmable sprite width,height, and pixel size
- sprite width and height may vary from 1 to 64 as long
as the product doesn't exceed 1024.
- pixels may be programmed to be 1,2,3 or 4 video clocks
both height and width are programmable
- programmable sprite position
- 16 bits for color
eg 32k color + 1 bit alpha blending indicator (1,5,5,5)
- fixed display and DMA priority
sprite 0 highest, sprite 7 lowest
 
This core requires an external timing generator to
provide horizontal and vertical sync signals, but
otherwise can be used as a display controller on it's
own. However, normally this core would be embedded
within another core such as a VGA controller. Sprite
positions are referenced to the rising edge of the
vertical and horizontal sync pulses.
The core includes an embedded dual port RAM to hold the
sprite images. The image RAM is updated using a built in DMA
controller. The DMA controller uses 16 bit accesses to fill
the sprite buffers, as the sprite buffers are only 16 bits
wide. The circuit features an automatic bus transaction
timeout; if the system bus hasn't responded within 20 clock
cycles, the DMA controller moves onto the next address.
The controller uses a ram underlay to cache the values
of the registers. This is a lot cheaper resource wise than
using a 32 to 1 multiplexor (well at least for an FPGA).
 
All registers are 16 bits wide
 
These registers repeat in incrementing block of four registers
and pertain to each sprite
0: HPOS - position register
[15: 0] horizontal position (hctr value)
1: VPOS [15:0] vertical position (vctr value)
 
2: SZ - size register
bits
[ 5: 0] width of sprite in pixels - 1
[ 7: 6] size of horizontal pixels - 1 in clock cycles
[13: 8] height of sprite in pixels -1
[15:14] size of vertical pixels in scan-lines - 1
* the product of width * height cannot exceed 1024 !
if it does, the display will begin repeating
3: OFFS [9:0] image offset
offset of the sprite image within the sprite image cache
typically zero
 
4: ADRH [15:0] sprite image address bits [42:27]
5: ADRL [15:0] sprite image address bits [26:11]
These registers contain the location of the sprite image
in system memory.
The low order 11 bits are fixed at zero. The DMA
controller will assign the low order 11 bits
during DMA.
6: TC [15:0] transparent color
This register identifies which color of the sprite
is transparent
 
 
8-63: registers for seven other sprites
 
Global status and control
116: BTC [23:0] background transparent color
117: BTC
118: BC [23:0] background color
119: BC
120: EN [15:0] sprite enable register
121: IE [15:0] sprite interrupt enable / status
122: SCOL [15:0] sprite-sprite collision register
123: BCOL [15:0] sprite-background collision register
124: DT [ 7:0] sprite DMA trigger
 
 
1635 LUTs/ 1112 slices/ 82MHz - Spartan3e-4
3 8x8 multipliers (for alpha blending)
8 block rams
=============================================================== */
 
`define VENDOR_XILINX // block ram vendor (only one defined for now)
 
module rtfSpriteController(
// Bus Slave interface
//------------------------------
// Slave signals
input rst_i, // reset
input clk_i, // clock
input s_cyc_i, // cycle valid
input s_stb_i, // data transfer
output s_ack_o, // transfer acknowledge
input s_we_i, // write
input [ 1:0] s_sel_i, // byte select
input [43:0] s_adr_i, // address
input [15:0] s_dat_i, // data input
output reg [15:0] s_dat_o, // data output
output vol_o, // volatile register
//------------------------------
// Bus Master Signals
output reg m_soc_o, // start of cycle
output m_cyc_o, // cycle is valid
output m_stb_o, // strobe output
input m_ack_i, // input data is ready
output m_we_o, // write (always inactive)
output [ 1:0] m_sel_o, // byte select
output [43:0] m_adr_o, // DMA address
input [15:0] m_dat_i, // data input
output [15:0] m_dat_o, // data output (always zero)
//--------------------------
input vclk, // video dot clock
input hSync, // horizontal sync pulse
input vSync, // vertical sync pulse
input blank, // blanking signal
input [24:0] rgbIn, // input pixel stream
output reg [23:0] rgbOut, // output pixel stream
output irq // interrupt request
);
 
//--------------------------------------------------------------------
// Core Parameters
//--------------------------------------------------------------------
parameter pnSpr = 8; // number of sprites
parameter phBits = 11; // number of bits in horizontal timing counter
parameter pvBits = 11; // number of bits in vertical timing counter
parameter pColorBits = 16; // number of bits used for color data
localparam pnSprm = pnSpr-1;
 
 
//--------------------------------------------------------------------
// Variable Declarations
//--------------------------------------------------------------------
 
wire [2:0] sprN = s_adr_i[6:4];
 
reg [phBits-1:0] hctr; // horizontal reference counter (counts dots since hSync)
reg [pvBits-1:0] vctr; // vertical reference counter (counts scanlines since vSync)
reg sprSprIRQ;
reg sprBkIRQ;
 
reg [15:0] out; // sprite output
reg outact; // sprite output is active
wire bkCollision; // sprite-background collision
reg [23:0] bgTc; // background transparent color
reg [23:0] bkColor; // background color
 
 
reg [7:0] sprWe; // block ram write enable for image cache update
reg [7:0] sprRe; // block ram read enable for image cache update
 
// Global control registers
reg [7:0] sprEn; // enable sprite
reg [7:0] sprCollision; // sprite-sprite collision
reg sprSprIe; // sprite-sprite interrupt enable
reg sprBkIe; // sprite-background interrupt enable
reg sprSprIRQPending; // sprite-sprite collision interrupt pending
reg sprBkIRQPending; // sprite-background collision interrupt pending
reg sprSprIRQPending1; // sprite-sprite collision interrupt pending
reg sprBkIRQPending1; // sprite-background collision interrupt pending
reg sprSprIRQ1; // vclk domain regs
reg sprBkIRQ1;
 
// Sprite control registers
reg [7:0] sprSprCollision;
reg [7:0] sprSprCollision1;
reg [7:0] sprBkCollision;
reg [7:0] sprBkCollision1;
reg [pColorBits-1:0] sprTc [pnSprm:0]; // sprite transparent color code
// How big the pixels are:
// 1,2,3,or 4 video clocks
reg [1:0] hSprRes [pnSprm:0]; // sprite horizontal resolution
reg [1:0] vSprRes [pnSprm:0]; // sprite vertical resolution
reg [5:0] sprWidth [pnSprm:0]; // number of pixels in X direction
reg [5:0] sprHeight [pnSprm:0]; // number of vertical pixels
 
// display and timing signals
reg [7:0] hSprReset; // horizontal reset
reg [7:0] vSprReset; // vertical reset
reg [7:0] hSprDe; // sprite horizontal display enable
reg [7:0] vSprDe; // sprite vertical display enable
reg [7:0] sprDe; // display enable
reg [phBits-1:0] hSprPos [7:0]; // sprite horizontal position
reg [pvBits-1:0] vSprPos [7:0]; // sprite vertical position
reg [5:0] hSprCnt [7:0]; // sprite horizontal display counter
reg [5:0] vSprCnt [7:0]; // vertical display counter
reg [9:0] sprImageOffs [7:0]; // offset within sprite memory
reg [9:0] sprAddr [7:0]; // index into sprite memory
reg [9:0] sprAddrB [7:0]; // backup address cache for rescan
wire [pColorBits-1:0] sprOut [7:0]; // sprite image data output
 
// DMA access
reg [26:11] sprSysAddrL [7:0]; // system memory address of sprite image (low bits)
reg [42:27] sprSysAddrH [7:0]; // system memory address of sprite image (high bits)
reg [2:0] dmaOwner; // which sprite has the DMA channel
reg [7:0] sprDt; // DMA trigger register
wire dmaDone; // DMA is finished
reg [10:0] dmaCount; // this counter forms the low order 11 bits of the system address for DMA
reg [10:0] dmaCountNext; // next value dmaCount will be loaded with
reg [10:0] updAdr; // this counter is used to index the sprite image cache
reg [10:0] updAdrNext;
reg dmaStart; // this flag pulses high for a single cycle at the start of a DMA
reg dmaActive; // this flag indicates that a block DMA transfer is active
 
integer n;
 
//--------------------------------------------------------------------
// DMA control / bus interfacing
//--------------------------------------------------------------------
wire cs_ram = s_cyc_i && s_stb_i && (s_adr_i[43:16]==28'hFFF_FFD8);
wire cs_regs = s_cyc_i && s_stb_i && (s_adr_i[43:8]==36'hFFF_FFDA_D0);
 
reg sprRamRdy;
always @(posedge clk_i)
sprRamRdy = cs_ram;
 
 
assign m_stb_o = m_cyc_o;
assign s_ack_o = cs_regs ? 1'b1 : cs_ram ? (s_we_i ? 1 : sprRamRdy) : 0;
assign vol_o = cs_regs & s_adr_i[7:2]>6'd59;
assign irq = sprSprIRQ|sprBkIRQ;
 
//--------------------------------------------------------------------
// DMA control / bus interfacing
//--------------------------------------------------------------------
 
wire btout;
wire sbi_rdy1 = m_ack_i|btout;
busTimeoutCtr #(20) br0(
.rst(rst_i),
.crst(1'b0),
.clk(clk_i),
.ce(1'b1),
.req(m_soc_o),
.rdy(m_ack_i),
.timeout(btout)
);
 
assign m_we_o = 1'b0;
assign m_sel_o = 2'b11;
assign m_adr_o = {1'b0,sprSysAddrH[dmaOwner],sprSysAddrL[dmaOwner],dmaCount[9:0],1'b0};
assign m_dat_o = 32'd0;
 
// DMA address generator goes based on the requests that have been acknowledged
assign dmaDone = dmaCountNext[10] & sbi_rdy1;
 
always @(dmaCount)
dmaCountNext = dmaCount + 1;
 
always @(posedge clk_i)
if (rst_i)
dmaCount = 0;
else begin
if (dmaStart)
dmaCount = 0;
else if (sbi_rdy1 && !dmaDone)
dmaCount = dmaCountNext;
end
 
// sprite cache address generator goes based on the responses that are ready
wire updDone = updAdrNext[10] & sbi_rdy1;
 
always @(updAdr)
updAdrNext = updAdr + 1;
 
always @(posedge clk_i)
if (rst_i)
updAdr = 0;
else begin
if (dmaStart)
updAdr = 0;
else if (sbi_rdy1 && !updDone)
updAdr = updAdrNext;
end
 
// Arbitrate access to DMA channel - priority ordered
always @(posedge clk_i)
if (rst_i) begin
dmaActive <= 1'b0;
dmaOwner <= 3'd0;
dmaStart <= 1'b0;
m_soc_o <= 1'b0;
end
else begin
dmaStart <= 1'b0;
m_soc_o <= 1'b0;
if (!dmaActive || updDone) begin
dmaStart <= |sprDt;
dmaActive <= |sprDt;
m_soc_o <= |sprDt;
dmaOwner <= 0;
for (n = 7; n >= 0; n = n - 1)
if (sprDt[n]) dmaOwner <= n;
end
if (sbi_rdy1 && !updDone)
m_soc_o <= 1'b1;
end
 
assign m_cyc_o = dmaActive & !dmaDone;
 
// generate a write enable strobe for the sprite image memory
always @(dmaOwner, dmaActive, s_adr_i, cs_ram, s_we_i)
for (n = 0; n < 8; n = n + 1)
sprWe[n] = (dmaOwner==n && dmaActive)||(cs_ram & s_we_i & s_adr_i[13:11]==n);
 
always @(cs_ram, s_adr_i)
for (n = 0; n < 8; n = n + 1)
sprRe[n] = cs_ram & s_adr_i[13:11]==n;
 
wire [15:0] sr_dout [7:0];
wire [15:0] sr_dout_all = sr_dout[0]|sr_dout[1]|sr_dout[2]|sr_dout[3]|sr_dout[4]|sr_dout[5]|sr_dout[6]|sr_dout[7];
 
// register/sprite memory output mux
always @*
if (cs_ram)
s_dat_o <= sr_dout_all;
else if (cs_regs)
case (s_adr_i[7:1]) // synopsys full_case parallel_case
7'd120: s_dat_o <= {8'b0,sprEn};
7'd121: s_dat_o <= {sprBkIRQPending|sprSprIRQPending,5'b0,sprBkIRQPending,sprSprIRQPending,6'b0,sprBkIe,sprSprIe};
7'd122: s_dat_o <= {8'b0,sprSprCollision};
7'd123: s_dat_o <= sprBkCollision;
7'd124: s_dat_o <= sprDt;
default: s_dat_o <= 0;
endcase
else
s_dat_o <= 32'd0;
 
 
// vclk -> clk_i
always @(posedge clk_i)
begin
sprSprIRQ <= sprSprIRQ1;
sprBkIRQ <= sprBkIRQ1;
sprSprIRQPending <= sprSprIRQPending1;
sprBkIRQPending <= sprBkIRQPending1;
sprSprCollision <= sprSprCollision1;
sprBkCollision <= sprBkCollision1;
end
 
 
// register updates
// on the clk_i domain
always @(posedge clk_i)
if (rst_i) begin
sprEn <= 8'hFF;
sprDt <= 0;
for (n = 0; n < pnSpr; n = n + 1) begin
sprSysAddrL[n] <= 5'b0100_0 + n; //xxxx_4000
sprSysAddrH[n] <= 16'h0000; //0000_xxxx
end
sprSprIe <= 0;
sprBkIe <= 0;
 
// Set reasonable starting positions on the screen
// so that the sprites might be visible for testing
for (n = 0; n < pnSpr; n = n + 1) begin
hSprPos[n] <= 440 + n * 40;
vSprPos[n] <= 200;
sprTc[n] <= 16'h6739;
sprWidth[n] <= 31; // 32x32 sprites
sprHeight[n] <= 31;
hSprRes[n] <= 0; // our standard display
vSprRes[n] <= 1;
sprImageOffs[n] <= 0;
end
hSprPos[0] <= 290;
vSprPos[0] <= 72;
 
bgTc <= 24'h00_00_00;
bkColor <= 24'hFF_FF_60;
end
else begin
// clear DMA trigger bit once DMA is recognized
if (dmaStart)
sprDt[dmaOwner] <= 1'b0;
 
if (cs_regs & s_we_i) begin
 
casex (s_adr_i[7:1])
 
7'b0xxx000:
begin
if (s_sel_i[0]) hSprPos[sprN][ 7:0] <= s_dat_i[ 7:0];
if (s_sel_i[1]) hSprPos[sprN][10:8] <= s_dat_i[10:8];
end
7'b0xxx001:
begin
if (s_sel_i[0]) vSprPos[sprN][ 7:0] <= s_dat_i[ 7:0];
if (s_sel_i[1]) vSprPos[sprN][10:8] <= s_dat_i[10:8];
end
7'b0xxx010:
begin
if (s_sel_i[0]) begin
sprWidth[sprN] <= s_dat_i[5:0];
hSprRes[sprN] <= s_dat_i[7:6];
end
if (s_sel_i[1]) begin
sprHeight[sprN] <= s_dat_i[13:8];
vSprRes[sprN] <= s_dat_i[15:14];
end
end
7'b0xxx011:
begin
if (s_sel_i[0]) sprImageOffs[sprN][ 7:0] <= s_dat_i[ 7:0];
if (s_sel_i[1]) sprImageOffs[sprN][ 9:8] <= s_dat_i[ 9:8];
end
7'b0xxx100:
begin // DMA address set on clk_i domain
if (s_sel_i[0]) sprSysAddrH[sprN][34:27] <= s_dat_i[ 7:0];
if (s_sel_i[1]) sprSysAddrH[sprN][42:35] <= s_dat_i[15:8];
end
7'b0xxx101:
begin // DMA address set on clk_i domain
if (s_sel_i[0]) sprSysAddrL[sprN][18:11] <= s_dat_i[ 7:0];
if (s_sel_i[1]) sprSysAddrL[sprN][26:19] <= s_dat_i[15:0];
end
7'b0xxx110:
begin
if (s_sel_i[0]) sprTc[sprN][ 7:0] <= s_dat_i[ 7:0];
if (s_sel_i[1]) sprTc[sprN][15:8] <= s_dat_i[15:8];
end
 
7'd116:
begin
if (s_sel_i[0]) bgTc[7:0] <= s_dat_i[7:0];
if (s_sel_i[1]) bgTc[15:8] <= s_dat_i[15:8];
end
7'd117:
begin
if (s_sel_i[0]) bgTc[23:16] <= s_dat_i[7:0];
end
7'd118:
begin
if (s_sel_i[0]) bkColor[23:16] <= s_dat_i[7:0];
end
7'd119:
begin
if (s_sel_i[0]) bkColor[7:0] <= s_dat_i[7:0];
if (s_sel_i[1]) bkColor[15:8] <= s_dat_i[15:8];
end
7'd120:
begin
if (s_sel_i[0]) sprEn <= s_dat_i;
end
7'd121:
begin
if (s_sel_i[0]) begin
sprSprIe <= s_dat_i[0];
sprBkIe <= s_dat_i[1];
end
end
// update DMA trigger
// s_dat_i[7:0] indicates which triggers to set (1=set,0=ignore)
// s_dat_i[7:0] indicates which triggers to clear (1=clear,0=ignore)
7'd124:
begin
if (s_sel_i[0])
sprDt <= sprDt | s_dat_i[7:0];
end
7'd125:
begin
if (s_sel_i[0])
sprDt <= sprDt & ~s_dat_i[7:0];
end
default: ;
endcase
end
end
 
//-------------------------------------------------------------
// Sprite Image Cache RAM
// This RAM is dual ported with an SoC side and a display
// controller side.
//-------------------------------------------------------------
wire [10:1] sr_adr = m_cyc_o ? m_adr_o[10:1] : s_adr_i[10:1];
wire [15:0] sr_din = m_cyc_o ? m_dat_i[15:0] : s_dat_i[15:0];
wire sr_ce = m_cyc_o ? sbi_rdy1 : cs_ram;
 
// Note: the sprite output can't be zeroed out using the rst input!!!
// We need to know what the output is to determine if it's the
// transparent color.
genvar g;
generate
for (g = 0; g < 8; g = g + 1)
begin : genSpriteRam
rtfSpriteRam #(.pDw(pColorBits)) sprRam0
(
.clka(vclk),
.adra(sprAddr[g]),
.dia(16'hFFFF),
.doa(sprOut[g]),
.cea(1'b1),
.wea(1'b0),
.rsta(1'b0),
.clkb(clk_i),
.adrb(sr_adr),
.dib(sr_din),
.dob(sr_dout[g]),
.ceb(sr_ce),
.web(sprWe[g]),
.rstb(!sprRe[g])
);
end
endgenerate
 
 
 
//-------------------------------------------------------------
// Timing counters and addressing
// Sprites are like miniature bitmapped displays, they need
// all the same timing controls.
//-------------------------------------------------------------
 
// Create a timing reference using horizontal and vertical
// soc
wire hSyncEdge, vSyncEdge;
edge_det ed0(.rst(rst_i), .clk(vclk), .ce(1'b1), .i(hSync), .pe(hSyncEdge), .ne(), .ee() );
edge_det ed1(.rst(rst_i), .clk(vclk), .ce(1'b1), .i(vSync), .pe(vSyncEdge), .ne(), .ee() );
 
always @(posedge vclk)
if (rst_i) hctr <= 0;
else if (hSyncEdge) hctr <= 0;
else hctr <= hctr + 1;
 
always @(posedge vclk)
if (rst_i) vctr <= 0;
else if (vSyncEdge) vctr <= 0;
else if (hSyncEdge) vctr <= vctr + 1;
 
// track sprite horizontal reset
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1)
hSprReset[n] <= hctr==hSprPos[n];
 
// track sprite vertical reset
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1)
vSprReset[n] <= vctr==vSprPos[n];
 
always @(hSprDe, vSprDe)
for (n = 0; n < 8; n = n + 1)
sprDe[n] <= hSprDe[n] & vSprDe[n];
 
 
// take care of sprite size scaling
// video clock division
reg [7:0] hSprNextPixel;
reg [7:0] vSprNextPixel;
reg [1:0] hSprPt [7:0]; // horizontal pixel toggle
reg [1:0] vSprPt [7:0]; // vertical pixel toggle
always @(n)
for (n = 0; n < 8; n = n + 1)
hSprNextPixel[n] = hSprPt[n]==hSprRes[n];
always @(n)
for (n = 0; n < 8; n = n + 1)
vSprNextPixel[n] = vSprPt[n]==vSprRes[n];
 
// horizontal pixel toggle counter
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1)
if (hSprReset[n])
hSprPt[n] <= 0;
else if (hSprNextPixel[n])
hSprPt[n] <= 0;
else
hSprPt[n] <= hSprPt[n] + 1;
 
// vertical pixel toggle counter
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1)
if (hSprReset[n]) begin
if (vSprReset[n])
vSprPt[n] <= 0;
else if (vSprNextPixel[n])
vSprPt[n] <= 0;
else
vSprPt[n] <= vSprPt[n] + 1;
end
 
 
// clock sprite image address counters
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1) begin
// hReset and vReset - top left of sprite,
// reset address to image offset
if (hSprReset[n] & vSprReset[n]) begin
sprAddr[n] <= sprImageOffs[n];
sprAddrB[n] <= sprImageOffs[n];
end
// hReset:
// If the next vertical pixel
// set backup address to current address
// else
// set current address to backup address
// in order to rescan the line
else if (hSprReset[n]) begin
if (vSprNextPixel[n])
sprAddrB[n] <= sprAddr[n];
else
sprAddr[n] <= sprAddrB[n];
end
// Not hReset or vReset - somewhere on the sprite scan line
// just advance the address when the next pixel should be
// fetched
else if (sprDe[n] & hSprNextPixel[n])
sprAddr[n] <= sprAddr[n] + 1;
end
 
 
// clock sprite column (X) counter
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1)
if (hSprReset[n])
hSprCnt[n] <= 0;
else if (hSprNextPixel[n])
hSprCnt[n] <= hSprCnt[n] + 1;
 
 
// clock sprite horizontal display enable
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1) begin
if (hSprReset[n])
hSprDe[n] <= 1;
else if (hSprNextPixel[n]) begin
if (hSprCnt[n] == sprWidth[n])
hSprDe[n] <= 0;
end
end
 
 
// clock the sprite row (Y) counter
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1)
if (hSprReset[n]) begin
if (vSprReset[n])
vSprCnt[n] <= 0;
else if (vSprNextPixel[n])
vSprCnt[n] <= vSprCnt[n] + 1;
end
 
 
// clock sprite vertical display enable
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1) begin
if (hSprReset[n]) begin
if (vSprReset[n])
vSprDe[n] <= 1;
else if (vSprNextPixel[n]) begin
if (vSprCnt[n] == sprHeight[n])
vSprDe[n] <= 0;
end
end
end
 
 
//-------------------------------------------------------------
// Output stage
//-------------------------------------------------------------
 
// function used for color blending
// given an alpha and a color component, determine the resulting color
// this blends towards black or white
// alpha is eight bits ranging between 0 and 1.999...
// 1 bit whole, 7 bits fraction
function [7:0] fnBlend;
input [7:0] alpha;
input [7:0] colorbits;
 
begin
fnBlend = (({8'b0,colorbits} * alpha) >> 7);
end
endfunction
 
 
// pipeline delays for display enable
reg [7:0] sprDe1;
reg [7:0] sproact;
always @(posedge vclk)
for (n = 0; n < 8; n = n + 1) begin
sprDe1[n] <= sprDe[n];
end
 
 
// Detect which sprite outputs are active
// The sprite output is active if the current display pixel
// address is within the sprite's area, the sprite is enabled,
// and it's not a transparent pixel that's being displayed.
always @(n, sprEn, sprDe1)
for (n = 0; n < 8; n = n + 1)
sproact[n] <= sprEn[n] && sprDe1[n] && sprTc[n]!=sprOut[n];
 
// register sprite activity flag
// The image combiner uses this flag to know what to do with
// the sprite output.
always @(posedge vclk)
outact = |sproact;
 
// Display data comes from the active sprite with the
// highest display priority.
// Make sure that alpha blending is turned off when
// no sprite is active.
always @(posedge vclk)
begin
out = 16'h0080; // alpha blend max (and off)
for (n = 7; n >= 0; n = n - 1)
if (sproact[n]) out = sprOut[n];
end
 
 
// combine the text / graphics color output with sprite color output
// blend color output
wire [23:0] blendedColor = {
fnBlend(out[7:0],rgbIn[23:16]), // R
fnBlend(out[7:0],rgbIn[15: 8]), // G
fnBlend(out[7:0],rgbIn[ 7: 0])}; // B
 
 
// display color priority bit [24] 1=display is over sprite
always @(posedge vclk)
if (blank)
rgbOut <= 0;
else begin
if (rgbIn[24] && rgbIn[23:0] != bgTc) // color is in front of sprite
rgbOut <= rgbIn[23:0];
else if (outact) begin
if (!out[15]) // a sprite is displayed without alpha blending
rgbOut <= {out[14:10],3'b0,out[9:5],3'b0,out[4:0],3'b0};
else
rgbOut <= blendedColor;
end else
rgbOut <= rgbIn[23:0];
end
 
 
//--------------------------------------------------------------------
// Collision logic
//--------------------------------------------------------------------
 
// Detect when a sprite-sprite collision has occurred. The criteria
// for this is that a pixel from the sprite is being displayed, while
// there is a pixel from another sprite that could be displayed at the
// same time.
always @(sproact)
case (sproact)
8'b00000000,
8'b00000001,
8'b00000010,
8'b00000100,
8'b00001000,
8'b00010000,
8'b00100000,
8'b01000000,
8'b10000000: sprCollision = 0;
default: sprCollision = 1;
endcase
 
// Detect when a sprite-background collision has occurred
assign bkCollision = (rgbIn[24] && rgbIn[23:0] != bgTc) ? 0 :
outact && rgbIn[23:0] != bkColor;
 
// Load the sprite collision register. This register continually
// accumulates collision bits until reset by reading the register.
// Set the collision IRQ on the first collision and don't set it
// again until after the collision register has been read.
always @(posedge vclk)
if (rst_i) begin
sprSprIRQPending1 <= 0;
sprSprCollision1 <= 0;
sprSprIRQ1 <= 0;
end
else if (sprCollision) begin
// isFirstCollision
if ((sprSprCollision1==0)||(cs_regs && s_sel_i[0] && s_adr_i[7:1]==7'd122)) begin
sprSprIRQPending1 <= 1;
sprSprIRQ1 <= sprSprIe;
sprSprCollision1 <= sproact;
end
else
sprSprCollision1 <= sprSprCollision1|sproact;
end
else if (cs_regs && s_sel_i[0] && s_adr_i[7:1]==7'd122) begin
sprSprCollision1 <= 0;
sprSprIRQPending1 <= 0;
sprSprIRQ1 <= 0;
end
 
 
// Load the sprite background collision register. This register
// continually accumulates collision bits until reset by reading
// the register.
// Set the collision IRQ on the first collision and don't set it
// again until after the collision register has been read.
// Note the background collision indicator is externally supplied,
// it will come from the color processing logic.
always @(posedge vclk)
if (rst_i) begin
sprBkIRQPending1 <= 0;
sprBkCollision1 <= 0;
sprBkIRQ1 <= 0;
end
else if (bkCollision) begin
// Is the register being cleared at the same time
// a collision occurss ?
// isFirstCollision
if ((sprBkCollision1==0) || (cs_regs && s_sel_i[0] && s_adr_i[7:1]==7'd123)) begin
sprBkIRQ1 <= sprBkIe;
sprBkCollision1 <= sproact;
sprBkIRQPending1 <= 1;
end
else
sprBkCollision1 <= sprBkCollision1|sproact;
end
else if (cs_regs && s_sel_i[0] && s_adr_i[7:1]==7'd123) begin
sprBkCollision1 <= 0;
sprBkIRQPending1 <= 0;
sprBkIRQ1 <= 0;
end
 
endmodule
/trunk/rtl/verilog/VT148.v
0,0 → 1,64
// ============================================================================
// (C) 2007 Robert Finch
// robfinch@<remove>sympatico.ca
//
// VT148 - 74LS148 priority encoder
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// Webpack 9.1i xc3s1000-4ft256
// 6 slices / 11 LUTs / 10.860 MHz
 
module VT148(en, i0, i1, i2, i3, i4, i5, i6, i7, o, gs, eo);
input en; // enable - active low
input i0; // input - active low
input i1;
input i2;
input i3;
input i4;
input i5;
input i6;
input i7;
output [2:0] o;
reg [2:0] o;
output gs;
output eo;
 
always @(en or i1 or i2 or i3 or i4 or i5 or i6 or i7)
if (en)
o = 3'd7;
else if (!i7)
o = 3'd0;
else if (!i6)
o = 3'd1;
else if (!i5)
o = 3'd2;
else if (!i4)
o = 3'd3;
else if (!i3)
o = 3'd4;
else if (!i2)
o = 3'd5;
else if (!i1)
o = 3'd6;
else
o = 3'd7;
 
nand(eo, i0,i1,i2,i3,i4,i5,i6,i7,!en);
or(gs, en,!eo);
 
endmodule
/trunk/rtl/verilog/rtf68kSys.ucf
0,0 → 1,784
 
NET "xclk" TNM_NET = "xclk";
NET "gclk1" TNM_NET = "gclk1";
#NET "clk" TNM_NET = "clk";
#NET "ifclk" TNM_NET = "ifclk";
NET "video_clk" TNM_NET = "video_clk";
TIMEGRP "video_clk_grp" = "video_clk";
 
NET "clk25" TNM_NET = "clk25";
TIMEGRP "clk25_grp" = "clk25";
 
TIMESPEC "TS_clk" = PERIOD "xclk" 20.00 ns HIGH 50 %;
#TIMESPEC "TS_ifclk" = PERIOD "ifclk" 41.67 ns HIGH 50 %;
TIMESPEC "TS_gclk1" = PERIOD "gclk1" 50.83 ns HIGH 50 %;
TIMESPEC "TS_video_clk_clk25" = FROM "video_clk_grp" TO "clk25_grp" TIG;
TIMESPEC "TS_clk25_video_clk" = FROM "clk25_grp" TO "video_clk_grp" TIG;
 
NET "xclk" LOC = "B8" | IOSTANDARD = LVCMOS33;
#NET "ifclk" LOC = "R11";
NET "gclk1" LOC = "U9";
 
# buttons
NET "btn<0>" LOC= "B18" | IOSTANDARD = LVCMOS33;
NET "btn<1>" LOC= "D18" | IOSTANDARD = LVCMOS33;
NET "btn<2>" LOC= "E18" | IOSTANDARD = LVCMOS33;
NET "btn<3>" LOC= "H13" | IOSTANDARD = LVCMOS33;
 
# Pin assignment for Switches
# Connected to Nexys 2
NET "swt<0>" LOC= "G18" | IOSTANDARD = LVCMOS33; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW0
NET "swt<1>" LOC= "H18" | IOSTANDARD = LVCMOS33; # Bank = 1 , Pin name = IP/VREF_1 , Type = VREF , Sch name = SW1
NET "swt<2>" LOC= "K18" | IOSTANDARD = LVCMOS33; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW2
NET "swt<3>" LOC= "K17" | IOSTANDARD = LVCMOS33; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW3
NET "swt<4>" LOC= "L14" | IOSTANDARD = LVCMOS33; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW4
NET "swt<5>" LOC= "L13" | IOSTANDARD = LVCMOS33; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW5
NET "swt<6>" LOC= "N17" | IOSTANDARD = LVCMOS33; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW6
NET "swt<7>" LOC= "R17" | IOSTANDARD = LVCMOS33; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW7
 
#Keyboard - Nexys2
NET "kclk" LOC= "R12" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "kd" LOC= "P11" | IOSTANDARD = LVCMOS33 | PULLUP;
 
# JC1 Bottom
NET "dac_sync" LOC = "G15" | IOSTANDARD = LVCMOS33;
NET "dac_d" LOC = "J16" | IOSTANDARD = LVCMOS33;
#G13
NET "dac_sclk" LOC = "H16" | IOSTANDARD = LVCMOS33;
 
NET "eppAstb" LOC = "V14" | IOSTANDARD = LVCMOS33; # FlagA
NET "eppDstb" LOC = "U14" | IOSTANDARD = LVCMOS33; # FlagB
NET "eppWr" LOC = "V16" | IOSTANDARD = LVCMOS33; # FlagC
#NET "eppRst" LOC = "";
NET "eppDB<0>" LOC = "R14" | IOSTANDARD = LVCMOS33; # UFD0
NET "eppDB<1>" LOC = "R13" | IOSTANDARD = LVCMOS33; #...
NET "eppDB<2>" LOC = "P13" | IOSTANDARD = LVCMOS33;
NET "eppDB<3>" LOC = "T12" | IOSTANDARD = LVCMOS33;
NET "eppDB<4>" LOC = "N11" | IOSTANDARD = LVCMOS33;
NET "eppDB<5>" LOC = "R11" | IOSTANDARD = LVCMOS33;
NET "eppDB<6>" LOC = "P10" | IOSTANDARD = LVCMOS33;
NET "eppDB<7>" LOC = "R10" | IOSTANDARD = LVCMOS33; # UFD7
NET "eppWait" LOC = "N9" | IOSTANDARD = LVCMOS33; # Ack?
 
# Pin assignment for Switches
# Connected to Nexys 2
 
# seven segment display - Nexys2
NET "ssg<0>" LOC= "L18" | IOSTANDARD = LVCMOS33;
NET "ssg<1>" LOC= "F18" | IOSTANDARD = LVCMOS33;
NET "ssg<2>" LOC= "D17" | IOSTANDARD = LVCMOS33;
NET "ssg<3>" LOC= "D16" | IOSTANDARD = LVCMOS33;
NET "ssg<4>" LOC= "G14" | IOSTANDARD = LVCMOS33;
NET "ssg<5>" LOC= "J17" | IOSTANDARD = LVCMOS33;
NET "ssg<6>" LOC= "H14" | IOSTANDARD = LVCMOS33;
NET "ssg<7>" LOC= "C17" | IOSTANDARD = LVCMOS33;
 
NET "an<0>" LOC= "F17" | IOSTANDARD = LVCMOS33;
NET "an<1>" LOC= "H17" | IOSTANDARD = LVCMOS33;
NET "an<2>" LOC= "C18" | IOSTANDARD = LVCMOS33;
NET "an<3>" LOC= "F15" | IOSTANDARD = LVCMOS33;
 
# Leds
NET "led<0>" LOC = "J14" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
NET "led<1>" LOC = "J15" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
NET "led<2>" LOC = "K15" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
NET "led<3>" LOC = "K14" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
NET "led<4>" LOC = "E16" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
NET "led<5>" LOC = "P16" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
NET "led<6>" LOC = "E4" | IOSTANDARD = LVCMOS33; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
NET "led<7>" LOC = "P4" | IOSTANDARD = LVCMOS33; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
 
// PSRAM - Nexys2
NET "ram_a<1>" LOC= "J1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<2>" LOC= "J2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<3>" LOC= "H4" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<4>" LOC= "H1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<5>" LOC= "H2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<6>" LOC= "J5" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<7>" LOC= "H3" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<8>" LOC= "H6" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<9>" LOC= "F1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<10>" LOC= "G3" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<11>" LOC= "G6" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<12>" LOC= "G5" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<13>" LOC= "G4" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<14>" LOC= "F2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<15>" LOC= "E1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<16>" LOC= "M5" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<17>" LOC= "E2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<18>" LOC= "C2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<19>" LOC= "C1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<20>" LOC= "D2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<21>" LOC= "K3" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<22>" LOC= "D1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_a<23>" LOC= "K6" | IOSTANDARD = LVCMOS33 | DRIVE=2;
 
NET "ram_d<0>" LOC= "L1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<1>" LOC= "L4" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<2>" LOC= "L6" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<3>" LOC= "M4" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<4>" LOC= "N5" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<5>" LOC= "P1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<6>" LOC= "P2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<7>" LOC= "R2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<8>" LOC= "L3" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<9>" LOC= "L5" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<10>" LOC= "M3" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<11>" LOC= "M6" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<12>" LOC= "L2" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<13>" LOC= "N4" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<14>" LOC= "R3" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_d<15>" LOC= "T1" | IOSTANDARD = LVCMOS33 | DRIVE=2;
 
NET "ram_d<0>" FAST;
NET "ram_d<1>" FAST;
NET "ram_d<2>" FAST;
NET "ram_d<3>" FAST;
NET "ram_d<4>" FAST;
NET "ram_d<5>" FAST;
NET "ram_d<6>" FAST;
NET "ram_d<7>" FAST;
NET "ram_d<8>" FAST;
NET "ram_d<9>" FAST;
NET "ram_d<10>" FAST;
NET "ram_d<11>" FAST;
NET "ram_d<12>" FAST;
NET "ram_d<13>" FAST;
NET "ram_d<14>" FAST;
NET "ram_d<15>" FAST;
 
#active low
NET "ram_ce" LOC = "R6" | IOSTANDARD = LVCMOS33;
NET "ram_ce" FAST;
 
NET "ram_oe" LOC = "T2" | IOSTANDARD = LVCMOS33 | DRIVE=2 | PULLUP;
NET "ram_oe" FAST;
 
NET "ram_we" LOC = "N7" | IOSTANDARD = LVCMOS33 | DRIVE=2;
NET "ram_we" FAST;
 
NET "flash_ce" LOC = "R5" | IOSTANDARD = LVCMOS33;
NET "flash_rp" LOC = "T5" | IOSTANDARD = LVCMOS33;
NET "flash_st" LOC = "D3" | IOSTANDARD = LVCMOS33 | DRIVE=2 | PULLUP;
 
#active low
NET "ram_ub" LOC = "K4" | IOSTANDARD = LVCMOS33 | DRIVE=2 | PULLDOWN;
NET "ram_lb" LOC = "K5" | IOSTANDARD = LVCMOS33 | DRIVE=2 | PULLDOWN;
NET "ram_adv" LOC = "J4" | IOSTANDARD = LVCMOS33;
NET "ram_clk" LOC = "H5" | IOSTANDARD = LVCMOS33;
NET "ram_cre" LOC = "P7" | IOSTANDARD = LVCMOS33;
NET "ram_wait" LOC = "F5" | IOSTANDARD = LVCMOS33;
 
# VGA - Nexys 2
NET "red<0>" LOC= "R9" | IOSTANDARD = LVCMOS33;
NET "red<1>" LOC= "T8" | IOSTANDARD = LVCMOS33;
NET "red<2>" LOC= "R8" | IOSTANDARD = LVCMOS33;
NET "green<0>" LOC= "N8" | IOSTANDARD = LVCMOS33;
NET "green<1>" LOC= "P8" | IOSTANDARD = LVCMOS33;
NET "green<2>" LOC= "P6" | IOSTANDARD = LVCMOS33;
NET "blue<0>" LOC= "U5" | IOSTANDARD = LVCMOS33;
NET "blue<1>" LOC= "U4" | IOSTANDARD = LVCMOS33;
NET "hSync" LOC= "T4" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "vSync" LOC= "U3" | IOSTANDARD = LVCMOS33 | PULLUP;
 
NET "rxd" LOC = "U6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "txd" LOC = "P9" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
 
// JB1 bottom
#NET "rst1626" LOC = "P17" | IOSTANDARD = LVCMOS33;
#NET "clk1626" LOC = "U18" | IOSTANDARD = LVCMOS33;
#NET "dq1626" LOC = "R16" | IOSTANDARD = LVCMOS33;
 
#INST BOOTROM0 INIT_00=FFD1207C00CE303C07D0323CFFFC57C930C00000FFD0207C0020303C07D0323C;
#INST BOOTROM0 INIT_01=0100064010194240670C4A110000FFD041F900CEFFFF43F9FFFC57C930C00000;
#INST BOOTROM0 INIT_02=203C66E60078B03C0006FFD013C001000640007F02000000FFDC103960F030C0;
#INST BOOTROM0 INIT_03=538030C201A2FFFF4EB922081234343C0000FFD043F90000000241F900000006;
#INST BOOTROM0 INIT_04=20000000207C4E6010000000207C66FA5380425800000000207C2000303C66F2;
#INST BOOTROM0 INIT_05=103900CEFFFF43F9000E103C04100000FFD021FC00BC21C800DAFFFF41F92E48;
#INST BOOTROM0 INIT_06=67340006B03C2E002E2E472E494E4F54424F4ED00004FFDD20796AF80000FFDD;
#INST BOOTROM0 INIT_07=007F02016AF80000FFDC12394E7367100007B03C67080005B03C675E000EB03C;
#INST BOOTROM0 INIT_08=FFD0B1FC30C1041020782F084E7342014E730001123C6A060000FFDC12394E73;
#INST BOOTROM0 INIT_09=103C205F0176FFFF4EB9041021C80034000091FC4E73205F041021C864080C98;
#INST BOOTROM0 INIT_0A=65EA0C98FFD0B1FC041021C830C01019424067244A11041020782F004E730006;
#INST BOOTROM0 INIT_0B=FFD041F90618303C2F004E73201F60D80176FFFF4EB9041021C80034000091FC;
#INST BOOTROM0 INIT_0C=201FFFFC57C830C10C30FFD041F90034303C0020323CFFFA57C8003430E80000;
#INST BOOTROM0 INIT_0D=3602013006400011064063040009B07C000F024010010007343CB00048E74E75;
#INST BOOTROM0 INIT_0E=43F95555AAAA203C00080000207C4E75000D4CDFFFE057CAE89930003380E343;
#INST BOOTROM0 INIT_0F=0000207C244866EAFFFC00FFB1FC01A2FFFF4EB922086610B09820800006FFD0;
#INST BOOTROM0 INIT_10=203C00080000207C6660B5C867EE5555AAAA0C8001A2FFFF4EB9220820180008;
#INST BOOTROM0 INIT_11=0000207C244866EAFFFC00FFB1FC01A2FFFF4EB922086610B0982080AAAA5555;
#INST BOOTROM0 INIT_12=000091FC041421C86620B5C867EEAAAA55550C8001A2FFFF4EB9220820180008;
#INST BOOTROM0 INIT_13=000091FF60FC4ED34ED304080408000021FC04004545465221FC040421C8000C;
 
# Character Glyphs
# 512 Ascii characters
# C64
#
INST tc1/charRam0/ram0 INIT_00=003C66060606663C003E66663E66663E006666667E663C18003C46067676663C;
INST tc1/charRam0/ram0 INIT_01=003C66667606663C000606061E06067E007E06061E06067E001E36666666361E;
INST tc1/charRam0/ram0 INIT_02=0066361E0E1E3666001C363030303078003C18181818183C006666667E666666;
INST tc1/charRam0/ram0 INIT_03=003C66666666663C006666767E7E6E6600C6C6C6D6FEEEC6007E060606060606;
INST tc1/charRam0/ram0 INIT_04=003C66603C06663C0066361E3E66663E00703C666666663C000606063E66663E;
INST tc1/charRam0/ram0 INIT_05=00C6EEFED6C6C6C600183C6666666666003C666666666666001818181818187E;
INST tc1/charRam0/ram0 INIT_06=003C0C0C0C0C0C3C007E060C1830607E001818183C6666660066663C183C6666;
INST tc1/charRam0/ram0 INIT_07=00080CFEFE0C0800181818187E3C1800003C30303030303C003F460C3E0C4830;
INST tc1/charRam0/ram0 INIT_08=006666FF66FF6666000000000066666600180000181818180000000000000000;
INST tc1/charRam0/ram0 INIT_09=000000000018306000FC66E61C3C663C0062660C1830664600183E603C067C18;
INST tc1/charRam0/ram0 INIT_0A=000018187E1818000000663CFF3C6600000C18303030180C0030180C0C0C1830;
INST tc1/charRam0/ram0 INIT_0B=00060C183060C0000018180000000000000000007E0000000C18180000000000;
INST tc1/charRam0/ram0 INIT_0C=003C66603860663C007E060C3060663C007E1818181C1818003C66666E76663C;
INST tc1/charRam0/ram0 INIT_0D=001818181830667E003C66663E06663C003C6660603E067E006060FE66787060;
INST tc1/charRam0/ram0 INIT_0E=0C181800001800000000180000180000003C66607C66663C003C66663C66663C;
INST tc1/charRam0/ram0 INIT_0F=001800183060663C000E18306030180E0000007E007E00000070180C060C1870;
INST tc1/charRam0/ram0 INIT_10=000000FFFF0000001818181818181818007C38FEFE7C3810000000FFFF000000;
INST tc1/charRam0/ram0 INIT_11=0C0C0C0C0C0C0C0C0000FFFF000000000000000000FFFF0000000000FFFF0000;
INST tc1/charRam0/ram0 INIT_12=000000070F1C1818000000E0F038181818181C0F070000003030303030303030;
INST tc1/charRam0/ram0 INIT_13=030303030303FFFF03070E1C3870E0C0C0E070381C0E0703FFFF030303030303;
INST tc1/charRam0/ram0 INIT_14=0010387CFEFEFE6C00FFFF0000000000003C7E7E7E7E3C00C0C0C0C0C0C0FFFF;
INST tc1/charRam0/ram0 INIT_15=003C7E66667E3C00C3E77E3C3C7EE7C3181838F0E00000000606060606060606;
INST tc1/charRam0/ram0 INIT_16=181818FFFF1818180010387CFE7C38106060606060606060003C181866661818;
INST tc1/charRam0/ram0 INIT_17=80C0E0F0F8FCFEFF006C6C6E7CC0000018181818181818180C0C03030C0C0303;
INST tc1/charRam0/ram0 INIT_18=00000000000000FFFFFFFFFF000000000F0F0F0F0F0F0F0F0000000000000000;
INST tc1/charRam0/ram0 INIT_19=C0C0C0C0C0C0C0C0CCCC3333CCCC33330303030303030303FF00000000000000;
INST tc1/charRam0/ram0 INIT_1A=181818F8F8181818C0C0C0C0C0C0C0C00103070F1F3F7FFFCCCC333300000000;
INST tc1/charRam0/ram0 INIT_1B=FFFF0000000000001818181F1F000000000000F8F8181818F0F0F0F000000000;
INST tc1/charRam0/ram0 INIT_1C=1818181F1F181818181818FFFF000000000000FFFF181818181818F8F8000000;
INST tc1/charRam0/ram0 INIT_1D=000000000000FFFFE0E0E0E0E0E0E0E007070707070707070303030303030303;
INST tc1/charRam0/ram0 INIT_1E=0F0F0F0F00000000FFFFC0C0C0C0C0C0FFFFFF00000000000000000000FFFFFF;
INST tc1/charRam0/ram0 INIT_1F=F0F0F0F00F0F0F0F000000000F0F0F0F0000001F1F18181800000000F0F0F0F0;
INST tc1/charRam0/ram0 INIT_20=FFC399F9F9F999C3FFC19999C19999C1FF9999998199C3E7FFC399F9898999C3;
INST tc1/charRam0/ram0 INIT_21=FFC3999989F999C3FFF9F9F9E1F9F981FF81F9F9E1F9F981FFE1C9999999C9E1;
INST tc1/charRam0/ram0 INIT_22=FF99C9E1F1E1C999FFE3C9CFCFCFCF87FFC3E7E7E7E7E7C3FF99999981999999;
INST tc1/charRam0/ram0 INIT_23=FFC39999999999C3FF99998981819199FF39393929011139FF81F9F9F9F9F9F9;
INST tc1/charRam0/ram0 INIT_24=FFC3999FC3F999C3FF99C9E1C19999C1FF8FC399999999C3FFF9F9F9C19999C1;
INST tc1/charRam0/ram0 INIT_25=FF39110129393939FFE7C39999999999FFC3999999999999FFE7E7E7E7E7E781;
INST tc1/charRam0/ram0 INIT_26=FFC3F3F3F3F3F3C3FF81F9F3E7CF9F81FFE7E7E7C3999999FF9999C3E7C39999;
INST tc1/charRam0/ram0 INIT_27=FFF7F30101F3F7FFE7E7E7E781C3E7FFFFC3CFCFCFCFCFC3FFC0B9F3C1F3B7CF;
INST tc1/charRam0/ram0 INIT_28=FF99990099009999FFFFFFFFFF999999FFE7FFFFE7E7E7E7FFFFFFFFFFFFFFFF;
INST tc1/charRam0/ram0 INIT_29=FFFFFFFFFFE7CF9FFF039919E3C399C3FF9D99F3E7CF99B9FFE7C19FC3F983E7;
INST tc1/charRam0/ram0 INIT_2A=FFFFE7E781E7E7FFFFFF99C300C399FFFFF3E7CFCFCFE7F3FFCFE7F3F3F3E7CF;
INST tc1/charRam0/ram0 INIT_2B=FFF9F3E7CF9F3FFFFFE7E7FFFFFFFFFFFFFFFFFF81FFFFFFF3E7E7FFFFFFFFFF;
INST tc1/charRam0/ram0 INIT_2C=FFC3999FC79F99C3FF81F9F3CF9F99C3FF81E7E7E7E3E7E7FFC39999918999C3;
INST tc1/charRam0/ram0 INIT_2D=FFE7E7E7E7CF9981FFC39999C1F999C3FFC3999F9FC1F981FF9F9F0199878F9F;
INST tc1/charRam0/ram0 INIT_2E=F3E7E7FFFFE7FFFFFFFFE7FFFFE7FFFFFFC3999F839999C3FFC39999C39999C3;
INST tc1/charRam0/ram0 INIT_2F=FFE7FFE7CF9F99C3FFF1E7CF9FCFE7F1FFFFFF81FF81FFFFFF8FE7F3F9F3E78F;
INST tc1/charRam0/ram0 INIT_30=FFFFFF0000FFFFFFE7E7E7E7E7E7E7E7FF83C7010183C7EFFFFFFF0000FFFFFF;
INST tc1/charRam0/ram0 INIT_31=F3F3F3F3F3F3F3F3FFFF0000FFFFFFFFFFFFFFFFFF0000FFFFFFFFFF0000FFFF;
INST tc1/charRam0/ram0 INIT_32=FFFFFFF8F0E3E7E7FFFFFF1F0FC7E7E7E7E7E3F0F8FFFFFFCFCFCFCFCFCFCFCF;
INST tc1/charRam0/ram0 INIT_33=FCFCFCFCFCFC0000FCF8F1E3C78F1F3F3F1F8FC7E3F1F8FC0000FCFCFCFCFCFC;
INST tc1/charRam0/ram0 INIT_34=FFEFC78301010193FF0000FFFFFFFFFFFFC381818181C3FF3F3F3F3F3F3F0000;
INST tc1/charRam0/ram0 INIT_35=FFC381999981C3FF3C1881C3C381183CE7E7C70F1FFFFFFFF9F9F9F9F9F9F9F9;
INST tc1/charRam0/ram0 INIT_36=E7E7E70000E7E7E7FFEFC7830183C7EF9F9F9F9F9F9F9F9FFFC3E7E79999E7E7;
INST tc1/charRam0/ram0 INIT_37=7F3F1F0F07030100FF939391833FFFFFE7E7E7E7E7E7E7E7F3F3FCFCF3F3FCFC;
INST tc1/charRam0/ram0 INIT_38=FFFFFFFFFFFFFF0000000000FFFFFFFFF0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFF;
INST tc1/charRam0/ram0 INIT_39=3F3F3F3F3F3F3F3F3333CCCC3333CCCCFCFCFCFCFCFCFCFC00FFFFFFFFFFFFFF;
INST tc1/charRam0/ram0 INIT_3A=E7E7E70707E7E7E73F3F3F3F3F3F3F3FFEFCF8F0E0C080003333CCCCFFFFFFFF;
INST tc1/charRam0/ram0 INIT_3B=0000FFFFFFFFFFFFE7E7E7E0E0FFFFFFFFFFFF0707E7E7E70F0F0F0FFFFFFFFF;
INST tc1/charRam0/ram0 INIT_3C=E7E7E7E0E0E7E7E7E7E7E70000FFFFFFFFFFFF0000E7E7E7E7E7E70707FFFFFF;
INST tc1/charRam0/ram0 INIT_3D=FFFFFFFFFFFF00001F1F1F1F1F1F1F1FF8F8F8F8F8F8F8F8FCFCFCFCFCFCFCFC;
INST tc1/charRam0/ram0 INIT_3E=F0F0F0F0FFFFFFFF00003F3F3F3F3F3F000000FFFFFFFFFFFFFFFFFFFF000000;
INST tc1/charRam0/ram0 INIT_3F=0F0F0F0FF0F0F0F0FFFFFFFFF0F0F0F0FFFFFFE0E0E7E7E7FFFFFFFF0F0F0F0F;
 
INST tc1/charRam0/ram1 INIT_00=003C0606063C0000003E66663E060600007C667C603C0000003C46067676663C;
INST tc1/charRam0/ram1 INIT_01=3E607C66667C0000001818187C187000003C067E663C0000007C66667C606000;
INST tc1/charRam0/ram1 INIT_02=0066361E360606003C60606060006000003C18181C001800006666663E060600;
INST tc1/charRam0/ram1 INIT_03=003C6666663C000000666666663E000000C6D6FEFE660000003C181818181C00;
INST tc1/charRam0/ram1 INIT_04=003E603C067C000000060606663E000060607C66667C000006063E66663E0000;
INST tc1/charRam0/ram1 INIT_05=006C7CFED6C6000000183C6666660000007C66666666000000701818187E1800;
INST tc1/charRam0/ram1 INIT_06=003C0C0C0C0C0C3C007E0C18307E00001E307C666666000000663C183C660000;
INST tc1/charRam0/ram1 INIT_07=00080CFEFE0C0800181818187E3C1800003C30303030303C003F460C3E0C4830;
INST tc1/charRam0/ram1 INIT_08=006666FF66FF6666000000000066666600180000181818180000000000000000;
INST tc1/charRam0/ram1 INIT_09=000000000018306000FC66E61C3C663C0062660C1830664600183E603C067C18;
INST tc1/charRam0/ram1 INIT_0A=000018187E1818000000663CFF3C6600000C18303030180C0030180C0C0C1830;
INST tc1/charRam0/ram1 INIT_0B=00060C183060C0000018180000000000000000007E0000000C18180000000000;
INST tc1/charRam0/ram1 INIT_0C=003C66603860663C007E060C3060663C007E1818181C1818003C66666E76663C;
INST tc1/charRam0/ram1 INIT_0D=001818181830667E003C66663E06663C003C6660603E067E006060FE66787060;
INST tc1/charRam0/ram1 INIT_0E=0C181800001800000000180000180000003C66607C66663C003C66663C66663C;
INST tc1/charRam0/ram1 INIT_0F=001800183060663C000E18306030180E0000007E007E00000070180C060C1870;
INST tc1/charRam0/ram1 INIT_10=003C66060606663C003E66663E66663E006666667E663C18000000FFFF000000;
INST tc1/charRam0/ram1 INIT_11=003C66667606663C000606061E06067E007E06061E06067E001E36666666361E;
INST tc1/charRam0/ram1 INIT_12=0066361E0E1E3666001C363030303078003C18181818183C006666667E666666;
INST tc1/charRam0/ram1 INIT_13=003C66666666663C006666767E7E6E6600C6C6C6D6FEEEC6007E060606060606;
INST tc1/charRam0/ram1 INIT_14=003C66603C06663C0066361E3E66663E00703C666666663C000606063E66663E;
INST tc1/charRam0/ram1 INIT_15=00C6EEFED6C6C6C600183C6666666666003C666666666666001818181818187E;
INST tc1/charRam0/ram1 INIT_16=181818FFFF181818007E060C1830607E001818183C6666660066663C183C6666;
INST tc1/charRam0/ram1 INIT_17=663399CC663399CC3333CCCC3333CCCC18181818181818180C0C03030C0C0303;
INST tc1/charRam0/ram1 INIT_18=00000000000000FFFFFFFFFF000000000F0F0F0F0F0F0F0F0000000000000000;
INST tc1/charRam0/ram1 INIT_19=C0C0C0C0C0C0C0C0CCCC3333CCCC33330303030303030303FF00000000000000;
INST tc1/charRam0/ram1 INIT_1A=181818F8F8181818C0C0C0C0C0C0C0C066CC993366CC9933CCCC333300000000;
INST tc1/charRam0/ram1 INIT_1B=FFFF0000000000001818181F1F000000000000F8F8181818F0F0F0F000000000;
INST tc1/charRam0/ram1 INIT_1C=1818181F1F181818181818FFFF000000000000FFFF181818181818F8F8000000;
INST tc1/charRam0/ram1 INIT_1D=000000000000FFFFE0E0E0E0E0E0E0E007070707070707070303030303030303;
INST tc1/charRam0/ram1 INIT_1E=0F0F0F0F0000000000060E1E3660C080FFFFFF00000000000000000000FFFFFF;
INST tc1/charRam0/ram1 INIT_1F=F0F0F0F00F0F0F0F000000000F0F0F0F0000001F1F18181800000000F0F0F0F0;
INST tc1/charRam0/ram1 INIT_20=FFC3F9F9F9C3FFFFFFC19999C1F9F9FFFF8399839FC3FFFFFFC399F9898999C3;
INST tc1/charRam0/ram1 INIT_21=C19F83999983FFFFFFE7E7E783E78FFFFFC3F98199C3FFFFFF839999839F9FFF;
INST tc1/charRam0/ram1 INIT_22=FF99C9E1C9F9F9FFC39F9F9F9FFF9FFFFFC3E7E7E3FFE7FFFF999999C1F9F9FF;
INST tc1/charRam0/ram1 INIT_23=FFC3999999C3FFFFFF99999999C1FFFFFF3929010199FFFFFFC3E7E7E7E7E3FF;
INST tc1/charRam0/ram1 INIT_24=FFC19FC3F983FFFFFFF9F9F999C1FFFF9F9F83999983FFFFF9F9C19999C1FFFF;
INST tc1/charRam0/ram1 INIT_25=FF9383012939FFFFFFE7C3999999FFFFFF8399999999FFFFFF8FE7E7E781E7FF;
INST tc1/charRam0/ram1 INIT_26=FFC3F3F3F3F3F3C3FF81F3E7CF81FFFFE1CF83999999FFFFFF99C3E7C399FFFF;
INST tc1/charRam0/ram1 INIT_27=FFF7F30101F3F7FFE7E7E7E781C3E7FFFFC3CFCFCFCFCFC3FFC0B9F3C1F3B7CF;
INST tc1/charRam0/ram1 INIT_28=FF99990099009999FFFFFFFFFF999999FFE7FFFFE7E7E7E7FFFFFFFFFFFFFFFF;
INST tc1/charRam0/ram1 INIT_29=FFFFFFFFFFE7CF9FFF039919E3C399C3FF9D99F3E7CF99B9FFE7C19FC3F983E7;
INST tc1/charRam0/ram1 INIT_2A=FFFFE7E781E7E7FFFFFF99C300C399FFFFF3E7CFCFCFE7F3FFCFE7F3F3F3E7CF;
INST tc1/charRam0/ram1 INIT_2B=FFF9F3E7CF9F3FFFFFE7E7FFFFFFFFFFFFFFFFFF81FFFFFFF3E7E7FFFFFFFFFF;
INST tc1/charRam0/ram1 INIT_2C=FFC3999FC79F99C3FF81F9F3CF9F99C3FF81E7E7E7E3E7E7FFC39999918999C3;
INST tc1/charRam0/ram1 INIT_2D=FFE7E7E7E7CF9981FFC39999C1F999C3FFC3999F9FC1F981FF9F9F0199878F9F;
INST tc1/charRam0/ram1 INIT_2E=F3E7E7FFFFE7FFFFFFFFE7FFFFE7FFFFFFC3999F839999C3FFC39999C39999C3;
INST tc1/charRam0/ram1 INIT_2F=FFE7FFE7CF9F99C3FFF1E7CF9FCFE7F1FFFFFF81FF81FFFFFF8FE7F3F9F3E78F;
INST tc1/charRam0/ram1 INIT_30=FFC399F9F9F999C3FFC19999C19999C1FF9999998199C3E7FFFFFF0000FFFFFF;
INST tc1/charRam0/ram1 INIT_31=FFC3999989F999C3FFF9F9F9E1F9F981FF81F9F9E1F9F981FFE1C9999999C9E1;
INST tc1/charRam0/ram1 INIT_32=FF99C9E1F1E1C999FFE3C9CFCFCFCF87FFC3E7E7E7E7E7C3FF99999981999999;
INST tc1/charRam0/ram1 INIT_33=FFC39999999999C3FF99998981819199FF39393929011139FF81F9F9F9F9F9F9;
INST tc1/charRam0/ram1 INIT_34=FFC3999FC3F999C3FF99C9E1C19999C1FF8FC399999999C3FFF9F9F9C19999C1;
INST tc1/charRam0/ram1 INIT_35=FF39110129393939FFE7C39999999999FFC3999999999999FFE7E7E7E7E7E781;
INST tc1/charRam0/ram1 INIT_36=E7E7E70000E7E7E7FF81F9F3E7CF9F81FFE7E7E7C3999999FF9999C3E7C39999;
INST tc1/charRam0/ram1 INIT_37=99CC663399CC6633CCCC3333CCCC3333E7E7E7E7E7E7E7E7F3F3FCFCF3F3FCFC;
INST tc1/charRam0/ram1 INIT_38=FFFFFFFFFFFFFF0000000000FFFFFFFFF0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFF;
INST tc1/charRam0/ram1 INIT_39=3F3F3F3F3F3F3F3F3333CCCC3333CCCCFCFCFCFCFCFCFCFC00FFFFFFFFFFFFFF;
INST tc1/charRam0/ram1 INIT_3A=E7E7E70707E7E7E73F3F3F3F3F3F3F3F993366CC993366CC3333CCCCFFFFFFFF;
INST tc1/charRam0/ram1 INIT_3B=0000FFFFFFFFFFFFE7E7E7E0E0FFFFFFFFFFFF0707E7E7E70F0F0F0FFFFFFFFF;
INST tc1/charRam0/ram1 INIT_3C=E7E7E7E0E0E7E7E7E7E7E70000FFFFFFFFFFFF0000E7E7E7E7E7E70707FFFFFF;
INST tc1/charRam0/ram1 INIT_3D=FFFFFFFFFFFF00001F1F1F1F1F1F1F1FF8F8F8F8F8F8F8F8FCFCFCFCFCFCFCFC;
INST tc1/charRam0/ram1 INIT_3E=F0F0F0F0FFFFFFFFFFF9F1E1C99F3F7F000000FFFFFFFFFFFFFFFFFFFF000000;
INST tc1/charRam0/ram1 INIT_3F=0F0F0F0FF0F0F0F0FFFFFFFFF0F0F0F0FFFFFFE0E0E7E7E7FFFFFFFF0F0F0F0F;
 
 
# Character Glyphs
# 512 Ascii characters
# VIC20
#
#INST tc1/charRam0/ram0 INIT_00=0038440202024438003E44443C44443E004242427E422418007804326A524438;
#INST tc1/charRam0/ram0 INIT_01=0038444272024438000202021E02027E007E02021E02027E001E24444444241E;
#INST tc1/charRam0/ram0 INIT_02=004222120E122242001C2220202020700038101010101038004242427E424242;
#INST tc1/charRam0/ram0 INIT_03=001824424242241800424262524A4642004242425A5A6642007E020202020202;
#INST tc1/charRam0/ram0 INIT_04=003C42403C02423C004222123E42423E0058245242422418000202023E42423E;
#INST tc1/charRam0/ram0 INIT_05=0042665A5A4242420018182424424242003C424242424242001010101010107C;
#INST tc1/charRam0/ram0 INIT_06=003C04040404043C007E02041820407E00101010384444440042422418244242;
#INST tc1/charRam0/ram0 INIT_07=000804FE040800001010101054381000003C20202020203C00760E083C080830;
#INST tc1/charRam0/ram0 INIT_08=0024247E247E2424000000000024242400100000101010100000000000000000;
#INST tc1/charRam0/ram0 INIT_09=0000000000081020005C22520C12120C006264081026460000103C5038147810;
#INST tc1/charRam0/ram0 INIT_0A=000010107C101000001054387C38541000040810101008040020100808081020;
#INST tc1/charRam0/ram0 INIT_0B=00020408102040000018180000000000000000007E0000000810100000000000;
#INST tc1/charRam0/ram0 INIT_0C=003C42403840423C007E020C3040423C007C101010141810003C42465A62423C;
#INST tc1/charRam0/ram0 INIT_0D=000808081020427E003C42423E020438001C2240201E027E0020207E24283020;
#INST tc1/charRam0/ram0 INIT_0E=08101000001000000000100000100000001C20407C42423C003C42423C42423C;
#INST tc1/charRam0/ram0 INIT_0F=000800083040423C000E18306030180E0000007E007E00000070180C060C1870;
#INST tc1/charRam0/ram0 INIT_10=00000000FF0000000808080808080808007C38FEFE7C3810000000FF00000000;
#INST tc1/charRam0/ram0 INIT_11=04040404040404040000FF0000000000000000000000FF000000000000FF0000;
#INST tc1/charRam0/ram0 INIT_12=0000000708101010000000C02010101010100807000000002020202020202020;
#INST tc1/charRam0/ram0 INIT_13=01010101010101FF01020408102040808040201008040201FF01010101010101;
#INST tc1/charRam0/ram0 INIT_14=0010387CFEFEFE6C00FF000000000000003C7E7E7E7E3C0080808080808080FF;
#INST tc1/charRam0/ram0 INIT_15=003C424242423C008142241818244281101020C0000000000202020202020202;
#INST tc1/charRam0/ram0 INIT_16=101010FF101010100010387CFE7C3810404040404040404000101054EE543810;
#INST tc1/charRam0/ram0 INIT_17=80C0E0F0F8FCFEFF0028282A7C80000010101010101010100A050A050A050A05;
#INST tc1/charRam0/ram0 INIT_18=00000000000000FFFFFFFFFF000000000F0F0F0F0F0F0F0F0000000000000000;
#INST tc1/charRam0/ram0 INIT_19=8080808080808080AA55AA55AA55AA550101010101010101FF00000000000000;
#INST tc1/charRam0/ram0 INIT_1A=101010F010101010C0C0C0C0C0C0C0C00103070F1F3F7FFFAA55AA5500000000;
#INST tc1/charRam0/ram0 INIT_1B=FFFF0000000000001010101F00000000000000F010101010F0F0F0F000000000;
#INST tc1/charRam0/ram0 INIT_1C=1010101F10101010101010FF00000000000000FF10101010101010F000000000;
#INST tc1/charRam0/ram0 INIT_1D=000000000000FFFFE0E0E0E0E0E0E0E007070707070707070303030303030303;
#INST tc1/charRam0/ram0 INIT_1E=0F0F0F0F00000000FF80808080808080FFFFFF00000000000000000000FFFFFF;
#INST tc1/charRam0/ram0 INIT_1F=F0F0F0F00F0F0F0F000000000F0F0F0F0000001F1010101000000000F0F0F0F0;
#INST tc1/charRam0/ram0 INIT_20=FFC7BBFDFDFDBBC7FFC1BBBBC3BBBBC1FFBDBDBD81BDDBE7FF87FBCD95ADBBC7;
#INST tc1/charRam0/ram0 INIT_21=FFC7BBBD8DFDBBC7FFFDFDFDE1FDFD81FF81FDFDE1FDFD81FFE1DBBBBBBBDBE1;
#INST tc1/charRam0/ram0 INIT_22=FFBDDDEDF1EDDDBDFFE3DDDFDFDFDF8FFFC7EFEFEFEFEFC7FFBDBDBD81BDBDBD;
#INST tc1/charRam0/ram0 INIT_23=FFE7DBBDBDBDDBE7FFBDBD9DADB5B9BDFFBDBDBDA5A599BDFF81FDFDFDFDFDFD;
#INST tc1/charRam0/ram0 INIT_24=FFC3BDBFC3FDBDC3FFBDDDEDC1BDBDC1FFA7DBADBDBDDBE7FFFDFDFDC1BDBDC1;
#INST tc1/charRam0/ram0 INIT_25=FFBD99A5A5BDBDBDFFE7E7DBDBBDBDBDFFC3BDBDBDBDBDBDFFEFEFEFEFEFEF83;
#INST tc1/charRam0/ram0 INIT_26=FFC3FBFBFBFBFBC3FF81FDFBE7DFBF81FFEFEFEFC7BBBBBBFFBDBDDBE7DBBDBD;
#INST tc1/charRam0/ram0 INIT_27=FFF7FB01FBF7FFFFEFEFEFEFABC7EFFFFFC3DFDFDFDFDFC3FF89F1F7C3F7F7CF;
#INST tc1/charRam0/ram0 INIT_28=FFDBDB81DB81DBDBFFFFFFFFFFDBDBDBFFEFFFFFEFEFEFEFFFFFFFFFFFFFFFFF;
#INST tc1/charRam0/ram0 INIT_29=FFFFFFFFFFF7EFDFFFA3DDADF3EDEDF3FF9D9BF7EFD9B9FFFFEFC3AFC7EB87EF;
#INST tc1/charRam0/ram0 INIT_2A=FFFFEFEF83EFEFFFFFEFABC783C7ABEFFFFBF7EFEFEFF7FBFFDFEFF7F7F7EFDF;
#INST tc1/charRam0/ram0 INIT_2B=FFFDFBF7EFDFBFFFFFE7E7FFFFFFFFFFFFFFFFFF81FFFFFFF7EFEFFFFFFFFFFF;
#INST tc1/charRam0/ram0 INIT_2C=FFC3BDBFC7BFBDC3FF81FDF3CFBFBDC3FF83EFEFEFEBE7EFFFC3BDB9A59DBDC3;
#INST tc1/charRam0/ram0 INIT_2D=FFF7F7F7EFDFBD81FFC3BDBDC1FDFBC7FFE3DDBFDFE1FD81FFDFDF81DBD7CFDF;
#INST tc1/charRam0/ram0 INIT_2E=F7EFEFFFFFEFFFFFFFFFEFFFFFEFFFFFFFE3DFBF83BDBDC3FFC3BDBDC3BDBDC3;
#INST tc1/charRam0/ram0 INIT_2F=FFF7FFF7CFBFBDC3FFF1E7CF9FCFE7F1FFFFFF81FF81FFFFFF8FE7F3F9F3E78F;
#INST tc1/charRam0/ram0 INIT_30=FFFFFFFF00FFFFFFF7F7F7F7F7F7F7F7FF83C7010183C7EFFFFFFF00FFFFFFFF;
#INST tc1/charRam0/ram0 INIT_31=FBFBFBFBFBFBFBFBFFFF00FFFFFFFFFFFFFFFFFFFFFF00FFFFFFFFFFFF00FFFF;
#INST tc1/charRam0/ram0 INIT_32=FFFFFFF8F7EFEFEFFFFFFF3FDFEFEFEFEFEFF7F8FFFFFFFFDFDFDFDFDFDFDFDF;
#INST tc1/charRam0/ram0 INIT_33=FEFEFEFEFEFEFE00FEFDFBF7EFDFBF7F7FBFDFEFF7FBFDFE00FEFEFEFEFEFEFE;
#INST tc1/charRam0/ram0 INIT_34=FFEFC78301010193FF00FFFFFFFFFFFFFFC381818181C3FF7F7F7F7F7F7F7F00;
#INST tc1/charRam0/ram0 INIT_35=FFC3BDBDBDBDC3FF7EBDDBE7E7DBBD7EEFEFDF3FFFFFFFFFFDFDFDFDFDFDFDFD;
#INST tc1/charRam0/ram0 INIT_36=EFEFEF00EFEFEFEFFFEFC7830183C7EFBFBFBFBFBFBFBFBFFFEFEFAB11ABC7EF;
#INST tc1/charRam0/ram0 INIT_37=7F3F1F0F07030100FFD7D7D5837FFFFFEFEFEFEFEFEFEFEFF5FAF5FAF5FAF5FA;
#INST tc1/charRam0/ram0 INIT_38=FFFFFFFFFFFFFF0000000000FFFFFFFFF0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFF;
#INST tc1/charRam0/ram0 INIT_39=7F7F7F7F7F7F7F7F55AA55AA55AA55AAFEFEFEFEFEFEFEFE00FFFFFFFFFFFFFF;
#INST tc1/charRam0/ram0 INIT_3A=EFEFEF0FEFEFEFEF3F3F3F3F3F3F3F3FFEFCF8F0E0C0800055AA55AAFFFFFFFF;
#INST tc1/charRam0/ram0 INIT_3B=0000FFFFFFFFFFFFEFEFEFE0FFFFFFFFFFFFFF0FEFEFEFEF0F0F0F0FFFFFFFFF;
#INST tc1/charRam0/ram0 INIT_3C=EFEFEFE0EFEFEFEFEFEFEF00FFFFFFFFFFFFFF00EFEFEFEFEFEFEF0FFFFFFFFF;
#INST tc1/charRam0/ram0 INIT_3D=FFFFFFFFFFFF00001F1F1F1F1F1F1F1FF8F8F8F8F8F8F8F8FCFCFCFCFCFCFCFC;
#INST tc1/charRam0/ram0 INIT_3E=F0F0F0F0FFFFFFFF007F7F7F7F7F7F7F000000FFFFFFFFFFFFFFFFFFFF000000;
#INST tc1/charRam0/ram0 INIT_3F=0F0F0F0FF0F0F0F0FFFFFFFFF0F0F0F0FFFFFFE0EFEFEFEFFFFFFFFF0F0F0F0F;
 
#INST tc1/charRam0/ram1 INIT_00=003C4202423C0000003A4642463A0202005C223C201C0000007804326A524438;
#INST tc1/charRam0/ram1 INIT_01=3C405C62625C0000000808083E084830003C027E423C0000005C6242625C4040;
#INST tc1/charRam0/ram1 INIT_02=0022160A122202021C22202020300020003810101018001000424242463A0202;
#INST tc1/charRam0/ram1 INIT_03=003C4242423C000000424242463A000000929292926E00000038101010101018;
#INST tc1/charRam0/ram1 INIT_04=003E403C027C000000020202463A000040405C62625C000002023A46463A0000;
#INST tc1/charRam0/ram1 INIT_05=006C9292928200000018244242420000005C62424242000000304808083E0808;
#INST tc1/charRam0/ram1 INIT_06=003C04040404043C007E0418207E00003C405C62424200000042241824420000;
#INST tc1/charRam0/ram1 INIT_07=000804FE040800001010101054381000003C20202020203C00760E083C080830;
#INST tc1/charRam0/ram1 INIT_08=0024247E247E2424000000000024242400100000101010100000000000000000;
#INST tc1/charRam0/ram1 INIT_09=0000000000081020005C22520C12120C006264081026460000103C5038147810;
#INST tc1/charRam0/ram1 INIT_0A=000010107C101000001054387C38541000040810101008040020100808081020;
#INST tc1/charRam0/ram1 INIT_0B=00020408102040000018180000000000000000007E0000000810100000000000;
#INST tc1/charRam0/ram1 INIT_0C=003C42403840423C007E020C3040423C007C101010141810003C42465A62423C;
#INST tc1/charRam0/ram1 INIT_0D=000808081020427E003C42423E020438001C2240201E027E0020207E24283020;
#INST tc1/charRam0/ram1 INIT_0E=08101000001000000000100000100000001C20407C42423C003C42423C42423C;
#INST tc1/charRam0/ram1 INIT_0F=000800083040423C000E18306030180E0000007E007E00000070180C060C1870;
#INST tc1/charRam0/ram1 INIT_10=0038440202024438003E44443C44443E004242427E422418000000FF00000000;
#INST tc1/charRam0/ram1 INIT_11=0038444272024438000202021E02027E007E02021E02027E001E24444444241E;
#INST tc1/charRam0/ram1 INIT_12=004222120E122242001C2220202020700038101010101038004242427E424242;
#INST tc1/charRam0/ram1 INIT_13=001824424242241800424262524A4642004242425A5A6642007E020202020202;
#INST tc1/charRam0/ram1 INIT_14=003C42403C02423C004222123E42423E0058245242422418000202023E42423E;
#INST tc1/charRam0/ram1 INIT_15=0042665A5A4242420018182424424242003C424242424242001010101010107C;
#INST tc1/charRam0/ram1 INIT_16=101010FF10101010007E02041820407E00101010384444440042422418244242;
#INST tc1/charRam0/ram1 INIT_17=99CC663399CC6633CCCC3333CCCC333310101010101010100A050A050A050A05;
#INST tc1/charRam0/ram1 INIT_18=00000000000000FFFFFFFFFF000000000F0F0F0F0F0F0F0F0000000000000000;
#INST tc1/charRam0/ram1 INIT_19=8080808080808080AA55AA55AA55AA550101010101010101FF00000000000000;
#INST tc1/charRam0/ram1 INIT_1A=101010F010101010C0C0C0C0C0C0C0C03366CC993366CC99AA55AA5500000000;
#INST tc1/charRam0/ram1 INIT_1B=FFFF0000000000001010101F00000000000000F010101010F0F0F0F000000000;
#INST tc1/charRam0/ram1 INIT_1C=1010101F10101010101010FF00000000000000FF10101010101010F000000000;
#INST tc1/charRam0/ram1 INIT_1D=000000000000FFFFE0E0E0E0E0E0E0E007070707070707070303030303030303;
#INST tc1/charRam0/ram1 INIT_1E=0F0F0F0F000000000002060A12224080FFFFFF00000000000000000000FFFFFF;
#INST tc1/charRam0/ram1 INIT_1F=F0F0F0F00F0F0F0F000000000F0F0F0F0000001F1010101000000000F0F0F0F0;
#INST tc1/charRam0/ram1 INIT_20=FFC3BDFDBDC3FFFFFFC5B9BDB9C5FDFDFFA3DDC3DFE3FFFFFF87FBCD95ADBBC7;
#INST tc1/charRam0/ram1 INIT_21=C3BFA39D9DA3FFFFFFF7F7F7C1F7B7CFFFC3FD81BDC3FFFFFFA39DBD9DA3BFBF;
#INST tc1/charRam0/ram1 INIT_22=FFDDE9F5EDDDFDFDE3DDDFDFDFCFFFDFFFC7EFEFEFE7FFEFFFBDBDBDB9C5FDFD;
#INST tc1/charRam0/ram1 INIT_23=FFC3BDBDBDC3FFFFFFBDBDBDB9C5FFFFFF6D6D6D6D91FFFFFFC7EFEFEFEFEFE7;
#INST tc1/charRam0/ram1 INIT_24=FFC1BFC3FD83FFFFFFFDFDFDB9C5FFFFBFBFA39D9DA3FFFFFDFDC5B9B9C5FFFF;
#INST tc1/charRam0/ram1 INIT_25=FF936D6D6D7DFFFFFFE7DBBDBDBDFFFFFFA39DBDBDBDFFFFFFCFB7F7F7C1F7F7;
#INST tc1/charRam0/ram1 INIT_26=FFC3FBFBFBFBFBC3FF81FBE7DF81FFFFC3BFA39DBDBDFFFFFFBDDBE7DBBDFFFF;
#INST tc1/charRam0/ram1 INIT_27=FFF7FB01FBF7FFFFEFEFEFEFABC7EFFFFFC3DFDFDFDFDFC3FF89F1F7C3F7F7CF;
#INST tc1/charRam0/ram1 INIT_28=FFDBDB81DB81DBDBFFFFFFFFFFDBDBDBFFEFFFFFEFEFEFEFFFFFFFFFFFFFFFFF;
#INST tc1/charRam0/ram1 INIT_29=FFFFFFFFFFF7EFDFFFA3DDADF3EDEDF3FF9D9BF7EFD9B9FFFFEFC3AFC7EB87EF;
#INST tc1/charRam0/ram1 INIT_2A=FFFFEFEF83EFEFFFFFEFABC783C7ABEFFFFBF7EFEFEFF7FBFFDFEFF7F7F7EFDF;
#INST tc1/charRam0/ram1 INIT_2B=FFFDFBF7EFDFBFFFFFE7E7FFFFFFFFFFFFFFFFFF81FFFFFFF7EFEFFFFFFFFFFF;
#INST tc1/charRam0/ram1 INIT_2C=FFC3BDBFC7BFBDC3FF81FDF3CFBFBDC3FF83EFEFEFEBE7EFFFC3BDB9A59DBDC3;
#INST tc1/charRam0/ram1 INIT_2D=FFF7F7F7EFDFBD81FFC3BDBDC1FDFBC7FFE3DDBFDFE1FD81FFDFDF81DBD7CFDF;
#INST tc1/charRam0/ram1 INIT_2E=F7EFEFFFFFEFFFFFFFFFEFFFFFEFFFFFFFE3DFBF83BDBDC3FFC3BDBDC3BDBDC3;
#INST tc1/charRam0/ram1 INIT_2F=FFF7FFF7CFBFBDC3FFF1E7CF9FCFE7F1FFFFFF81FF81FFFFFF8FE7F3F9F3E78F;
#INST tc1/charRam0/ram1 INIT_30=FFC7BBFDFDFDBBC7FFC1BBBBC3BBBBC1FFBDBDBD81BDDBE7FFFFFF00FFFFFFFF;
#INST tc1/charRam0/ram1 INIT_31=FFC7BBBD8DFDBBC7FFFDFDFDE1FDFD81FF81FDFDE1FDFD81FFE1DBBBBBBBDBE1;
#INST tc1/charRam0/ram1 INIT_32=FFBDDDEDF1EDDDBDFFE3DDDFDFDFDF8FFFC7EFEFEFEFEFC7FFBDBDBD81BDBDBD;
#INST tc1/charRam0/ram1 INIT_33=FFE7DBBDBDBDDBE7FFBDBD9DADB5B9BDFFBDBDBDA5A599BDFF81FDFDFDFDFDFD;
#INST tc1/charRam0/ram1 INIT_34=FFC3BDBFC3FDBDC3FFBDDDEDC1BDBDC1FFA7DBADBDBDDBE7FFFDFDFDC1BDBDC1;
#INST tc1/charRam0/ram1 INIT_35=FFBD99A5A5BDBDBDFFE7E7DBDBBDBDBDFFC3BDBDBDBDBDBDFFEFEFEFEFEFEF83;
#INST tc1/charRam0/ram1 INIT_36=EFEFEF00EFEFEFEFFF81FDFBE7DFBF81FFEFEFEFC7BBBBBBFFBDBDDBE7DBBDBD;
#INST tc1/charRam0/ram1 INIT_37=663399CC663399CC3333CCCC3333CCCCEFEFEFEFEFEFEFEFF5FAF5FAF5FAF5FA;
#INST tc1/charRam0/ram1 INIT_38=FFFFFFFFFFFFFF0000000000FFFFFFFFF0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFF;
#INST tc1/charRam0/ram1 INIT_39=7F7F7F7F7F7F7F7F55AA55AA55AA55AAFEFEFEFEFEFEFEFE00FFFFFFFFFFFFFF;
#INST tc1/charRam0/ram1 INIT_3A=EFEFEF0FEFEFEFEF3F3F3F3F3F3F3F3FCC993366CC99336655AA55AAFFFFFFFF;
#INST tc1/charRam0/ram1 INIT_3B=0000FFFFFFFFFFFFEFEFEFE0FFFFFFFFFFFFFF0FEFEFEFEF0F0F0F0FFFFFFFFF;
#INST tc1/charRam0/ram1 INIT_3C=EFEFEFE0EFEFEFEFEFEFEF00FFFFFFFFFFFFFF00EFEFEFEFEFEFEF0FFFFFFFFF;
#INST tc1/charRam0/ram1 INIT_3D=FFFFFFFFFFFF00001F1F1F1F1F1F1F1FF8F8F8F8F8F8F8F8FCFCFCFCFCFCFCFC;
#INST tc1/charRam0/ram1 INIT_3E=F0F0F0F0FFFFFFFFFFFDF9F5EDDDBF7F000000FFFFFFFFFFFFFFFFFFFF000000;
#INST tc1/charRam0/ram1 INIT_3F=0F0F0F0FF0F0F0F0FFFFFFFFF0F0F0F0FFFFFFE0EFEFEFEFFFFFFFFF0F0F0F0F;
 
#INST tc1/charRam0/ram0 INIT_00=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
#INST tc1/charRam0/ram0 INIT_01=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
#INST tc1/charRam0/ram0 INIT_02=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
#INST tc1/charRam0/ram0 INIT_03=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
#INST tc1/charRam0/ram0 INIT_04=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
#INST tc1/charRam0/ram0 INIT_05=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
#INST tc1/charRam0/ram0 INIT_06=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
#INST tc1/charRam0/ram0 INIT_07=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
#INST tc1/charRam0/ram0 INIT_08=000000143E143E14000000000000141400000008000808080000000000000000;
#INST tc1/charRam0/ram0 INIT_09=00000000000004080000002C120C140C00000032340816260000001C281C0A1C;
#INST tc1/charRam0/ram0 INIT_0A=00000008083E08080000002A1C081C2A00000008101010080000000804040408;
#INST tc1/charRam0/ram0 INIT_0B=0000000204081020000000181800000000000000003E00000000081018000000;
#INST tc1/charRam0/ram0 INIT_0C=0000001C201C201C0000003E021C201C0000001C08080C080000001C222A221C;
#INST tc1/charRam0/ram0 INIT_0D=000000080808103E0000001C221E021C0000001E201E021E00000010103E1212;
#INST tc1/charRam0/ram0 INIT_0E=00000C180018180000001818001818000000001C203C221C0000001C221C221C;
#INST tc1/charRam0/ram0 INIT_0F=000000080018201C0000000408100804000000003E003E000000001008040810;
#INST tc1/charRam0/ram0 INIT_10=0000001C0202021C0000001E221E221E00000022223E221C0000001C023A3A1C;
#INST tc1/charRam0/ram0 INIT_11=0000001C2232021C00000002021E023E0000003E020E023E0000001E2222221E;
#INST tc1/charRam0/ram0 INIT_12=00000022120E12220000001C222020200000001C0808081C00000022223E2222;
#INST tc1/charRam0/ram0 INIT_13=0000001C2222221C00000022322A262200000022222A36220000003E02020202;
#INST tc1/charRam0/ram0 INIT_14=0000001C201C021C00000022121E221E0000003C3222221C00000002021E221E;
#INST tc1/charRam0/ram0 INIT_15=000000142A2A222200000008141422220000001C22222222000000080808083E;
#INST tc1/charRam0/ram0 INIT_16=0000001C0404041C0000003E0408103E00000008080814220000002214081422;
#INST tc1/charRam0/ram0 INIT_17=000000000000000000000000000014080000001C1010101C0000002010080402;
#INST tc1/charRam0/ram0 INIT_18=0000001C02021C000000000E12120E020000001C1E100C000000000000080404;
#INST tc1/charRam0/ram0 INIT_19=000C101C12120C0000000004040E04080000000C021E0C000000001C12121C10;
#INST tc1/charRam0/ram0 INIT_1A=000000120E0E1202000C1210101000000000001C08080C000000001212120E02;
#INST tc1/charRam0/ram0 INIT_1B=0000000C12120C000000001212120E0000000022222A16000000001C0808080C;
#INST tc1/charRam0/ram0 INIT_1C=0000000E18061C000000000202120E000010301C12121C000002020E12120E00;
#INST tc1/charRam0/ram0 INIT_1D=000000142A222200000000040A1212000000001C121212000000000808081C08;
#INST tc1/charRam0/ram0 INIT_1E=00000008103810080000001E04081E00000C101C12120000000000120C0C1200;
#INST tc1/charRam0/ram0 INIT_1F=7F7F7F7F7F7F7F7F0000000000102A040000000000102A0400000008040E0408;
 
# Text screen
 
# Blue background, light-blue foreground
INST tc1/textRam0/ram0 INIT_00=0000000000000000000000000000000000000000000000000000000000434241;
INST tc1/textRam0/ram0 INIT_01=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_02=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_03=0000000000004545524600534554584200363132373737363100000000000000;
INST tc1/textRam0/ram0 INIT_04=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_05=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_06=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_07=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_08=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_09=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_0A=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_0B=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_0C=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_0D=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_0E=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_0F=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_10=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_11=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_12=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_13=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_14=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_15=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_16=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_17=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_18=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_19=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_1A=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_1B=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_1C=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_1D=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_1E=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_1F=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_20=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_21=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_22=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_23=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_24=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_25=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_26=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_27=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_28=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_29=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_2A=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_2B=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_2C=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_2D=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_2E=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_2F=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_30=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_31=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_32=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_33=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_34=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_35=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_36=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_37=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_38=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_39=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_3A=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_3B=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_3C=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_3D=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_3E=0000000000000000000000000000000000000000000000000000000000000000;
INST tc1/textRam0/ram0 INIT_3F=0000000000000000000000000000000000000000000000000000000000000000;
 
#INST tc1/textRam0/ram1 INIT_00=2222222222222222222222222222222222222222222222222222222222222444;
#INST tc1/textRam0/ram1 INIT_01=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_02=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_03=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_04=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_05=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_06=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_07=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_08=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_09=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_0A=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_0B=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_0C=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_0D=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_0E=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_0F=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_10=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_11=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_12=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_13=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_14=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_15=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_16=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_17=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_18=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_19=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_1A=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_1B=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_1C=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_1D=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_1E=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_1F=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_20=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_21=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_22=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_23=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_24=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_25=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_26=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_27=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_28=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_29=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_2A=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_2B=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_2C=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_2D=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_2E=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_2F=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_30=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_31=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_32=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_33=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_34=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_35=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_36=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_37=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_38=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_39=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_3A=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_3B=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_3C=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_3D=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_3E=2222222222222222222222222222222222222222222222222222222222222222;
#INST tc1/textRam0/ram1 INIT_3F=2222222222222222222222222222222222222222222222222222222222222222;
 
# Forground color
INST tc1/colorRam0/ram0 INIT_00=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_01=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
INST tc1/colorRam0/ram0 INIT_02=7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F;
INST tc1/colorRam0/ram0 INIT_03=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_04=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_05=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_06=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_07=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_08=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_09=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_0A=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_0B=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_0C=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_0D=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_0E=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_0F=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_10=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_11=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_12=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_13=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_14=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_15=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_16=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_17=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_18=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_19=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_1A=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_1B=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_1C=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_1D=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_1E=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_1F=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_20=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_21=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_22=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_23=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_24=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_25=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_26=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_27=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_28=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_29=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_2A=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_2B=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_2C=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_2D=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_2E=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_2F=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_30=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_31=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_32=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_33=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_34=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_35=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_36=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_37=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_38=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_39=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_3A=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_3B=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_3C=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_3D=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_3E=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
INST tc1/colorRam0/ram0 INIT_3F=6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E;
 
# Background color
#INST tc1/colorRam0/ram1 INIT_00=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_01=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_02=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_03=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_04=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_05=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_06=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_07=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_08=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_09=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_0A=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_0B=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_0C=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_0D=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_0E=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_0F=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_10=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_11=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_12=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_13=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_14=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_15=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_16=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_17=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_18=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_19=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_1A=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_1B=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_1C=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_1D=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_1E=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_1F=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_20=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_21=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_22=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_23=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_24=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_25=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_26=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_27=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_28=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_29=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_2A=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_2B=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_2C=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_2D=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_2E=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_2F=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_30=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_31=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_32=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_33=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_34=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_35=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_36=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_37=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_38=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_39=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_3A=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_3B=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_3C=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_3D=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_3E=6666666666666666666666666666666666666666666666666666666666666666;
#INST tc1/colorRam0/ram1 INIT_3F=6666666666666666666666666666666666666666666666666666666666666666;
 
/trunk/rtl/verilog/PSGShaper.v
0,0 → 1,47
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
rob@birdcomputer.ca
 
bcPSGShaper.v
Shape the channels by applying the envelope to the tone generator
output.
 
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
============================================================================ */
 
module PSGShaper(clk_i, ce, tgi, env, o);
input clk_i; // clock
input ce; // clock enable
input [11:0] tgi; // tone generator input
input [7:0] env; // envelop generator input
output [19:0] o; // shaped output
reg [19:0] o; // shaped output
 
// shape output according to envelope
always @(posedge clk_i)
if (ce)
o <= tgi * env;
 
endmodule
/trunk/rtl/verilog/PSGEnvGen.v
0,0 → 1,356
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
 
PSGEnvGen.v
Version 1.1
 
ADSR envelope generator.
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
Note that this envelope generator directly uses the values for attack,
decay, sustain, and release. The original SID had to use four bit codes
and lookup tables due to register limitations. This generator is
built assuming there aren't any such register limitations.
A wrapper could be built to provide that functionality.
This component isn't really meant to be used in isolation. It is
intended to be integrated into a larger audio component (eg SID
emulator). The host component should take care of wrapping the control
signals into a register array.
 
The 'cnt' signal acts a prescaler used to determine the base frequency
used to generate envelopes. The core expects to be driven at
approximately a 1.0MHz rate for proper envelope generation. This is
accomplished using the 'cnt' signal, which should the output of a
counter used to divide the master clock frequency down to approximately
a 1MHz rate. Therefore, the master clock frequency must be at least 4MHz
for a 4 channel generator, 8MHZ for an 8 channel generator. The test
system uses a 66.667MHz master clock and 'cnt' is the output of a seven
bit counter that divides by 66.
 
Note the resource space optimization. Rather than simply build a single
channel ADSR envelope generator and instantiate it four or eight times,
This unit uses a single envelope generator and time-multiplexes the
controls from four (or eight) different channels. The ADSR is just
complex enough that it's less expensive resource wise to multiplex the
control signals. The luxury of time division multiplexing can be used
here since audio signals are low frequency. The time division multiplex
means that we need a clock that's four (or eight) times faster than
would be needed if independent ADSR's were used. This probably isn't a
problem for most cases.
 
Spartan3
Webpack 9.1i xc3s1000-4ft256
522 LUTs / 271 slices / 81.155 MHz (speed)
============================================================================ */
 
/*
sample attack values / rates
----------------------------
8 2ms
32 8ms
64 16ms
96 24ms
152 38ms
224 56ms
272 68ms
320 80ms
400 100ms
955 239ms
1998 500ms
3196 800ms
3995 1s
12784 3.2s
21174 5.3s
31960 8s
 
rate = 990.00ns x 256 x value
*/
 
 
// envelope generator states
`define ENV_IDLE 0
`define ENV_ATTACK 1
`define ENV_DECAY 2
`define ENV_SUSTAIN 3
`define ENV_RELEASE 4
 
// Envelope generator
module PSGEnvGen(rst, clk, cnt,
gate,
attack0, attack1, attack2, attack3,
decay0, decay1, decay2, decay3,
sustain0, sustain1, sustain2, sustain3,
relese0, relese1, relese2, relese3,
o);
parameter pChannels = 4;
parameter pPrescalerBits = 8;
input rst; // reset
input clk; // core clock
input [pPrescalerBits-1:0] cnt; // clock rate prescaler
input [15:0] attack0;
input [15:0] attack1;
input [15:0] attack2;
input [15:0] attack3;
input [11:0] decay0;
input [11:0] decay1;
input [11:0] decay2;
input [11:0] decay3;
input [7:0] sustain0;
input [7:0] sustain1;
input [7:0] sustain2;
input [7:0] sustain3;
input [11:0] relese0;
input [11:0] relese1;
input [11:0] relese2;
input [11:0] relese3;
input [3:0] gate;
output [7:0] o;
 
reg [7:0] sustain;
reg [15:0] attack;
reg [17:0] decay;
reg [17:0] relese;
// Per channel count storage
reg [7:0] envCtr [3:0];
reg [7:0] envCtr2 [3:0];
reg [7:0] iv [3:0]; // interval value for decay/release
reg [2:0] icnt [3:0]; // interval count
reg [19:0] envDvn [3:0];
reg [2:0] envState [3:0];
 
reg [2:0] envStateNxt;
reg [15:0] envStepPeriod; // determines the length of one step of the envelope generator
reg [7:0] envCtrx;
reg [19:0] envDvnx;
 
// Time multiplexed values
wire [15:0] attack_x;
wire [11:0] decay_x;
wire [7:0] sustain_x;
wire [11:0] relese_x;
 
integer n;
 
wire [1:0] sel = cnt[1:0];
 
mux4to1 #(16) u1 (
.e(1'b1),
.s(sel),
.i0(attack0),
.i1(attack1),
.i2(attack2),
.i3(attack3),
.z(attack_x)
);
 
mux4to1 #(12) u2 (
.e(1'b1),
.s(sel),
.i0(decay0),
.i1(decay1),
.i2(decay2),
.i3(decay3),
.z(decay_x)
);
 
mux4to1 #(8) u3 (
.e(1'b1),
.s(sel),
.i0(sustain0),
.i1(sustain1),
.i2(sustain2),
.i3(sustain3),
.z(sustain_x)
);
 
mux4to1 #(12) u4 (
.e(1'b1),
.s(sel),
.i0(relese0),
.i1(relese1),
.i2(relese2),
.i3(relese3),
.z(relese_x)
);
 
always @(attack_x)
attack <= attack_x;
 
always @(decay_x)
decay <= decay_x;
 
always @(sustain_x)
sustain <= sustain_x;
 
always @(relese_x)
relese <= relese_x;
 
 
always @(sel)
envCtrx <= envCtr[sel];
 
always @(sel)
envDvnx <= envDvn[sel];
 
 
// Envelope generate state machine
// Determine the next envelope state
always @(sel or gate or sustain)
begin
case (envState[sel])
`ENV_IDLE:
if (gate[sel])
envStateNxt <= `ENV_ATTACK;
else
envStateNxt <= `ENV_IDLE;
`ENV_ATTACK:
if (envCtrx==8'hFE) begin
if (sustain==8'hFF)
envStateNxt <= `ENV_SUSTAIN;
else
envStateNxt <= `ENV_DECAY;
end
else
envStateNxt <= `ENV_ATTACK;
`ENV_DECAY:
if (envCtrx==sustain)
envStateNxt <= `ENV_SUSTAIN;
else
envStateNxt <= `ENV_DECAY;
`ENV_SUSTAIN:
if (~gate[sel])
envStateNxt <= `ENV_RELEASE;
else
envStateNxt <= `ENV_SUSTAIN;
`ENV_RELEASE: begin
if (envCtrx==8'h00)
envStateNxt <= `ENV_IDLE;
else if (gate[sel])
envStateNxt <= `ENV_SUSTAIN;
else
envStateNxt <= `ENV_RELEASE;
end
// In case of hardware problem
default:
envStateNxt <= `ENV_IDLE;
endcase
end
 
always @(posedge clk)
if (rst) begin
for (n = 0; n < pChannels; n = n + 1)
envState[n] <= `ENV_IDLE;
end
else if (cnt < pChannels)
envState[sel] <= envStateNxt;
 
 
// Handle envelope counter
always @(posedge clk)
if (rst) begin
for (n = 0; n < pChannels; n = n + 1) begin
envCtr[n] <= 0;
envCtr2[n] <= 0;
icnt[n] <= 0;
iv[n] <= 0;
end
end
else if (cnt < pChannels) begin
case (envState[sel])
`ENV_IDLE:
begin
envCtr[sel] <= 0;
envCtr2[sel] <= 0;
icnt[sel] <= 0;
iv[sel] <= 0;
end
`ENV_SUSTAIN:
begin
envCtr2[sel] <= 0;
icnt[sel] <= 0;
iv[sel] <= sustain >> 3;
end
`ENV_ATTACK:
begin
icnt[sel] <= 0;
iv[sel] <= (8'hff - sustain) >> 3;
if (envDvnx==20'h0) begin
envCtr2[sel] <= 0;
envCtr[sel] <= envCtrx + 1;
end
end
`ENV_DECAY,
`ENV_RELEASE:
if (envDvnx==20'h0) begin
envCtr[sel] <= envCtrx - 1;
if (envCtr2[sel]==iv[sel]) begin
envCtr2[sel] <= 0;
if (icnt[sel] < 3'd7)
icnt[sel] <= icnt[sel] + 1;
end
else
envCtr2[sel] <= envCtr2[sel] + 1;
end
endcase
end
 
// Determine envelope divider adjustment source
always @(sel or attack or decay or relese)
begin
case(envState[sel])
`ENV_ATTACK: envStepPeriod <= attack;
`ENV_DECAY: envStepPeriod <= decay;
`ENV_RELEASE: envStepPeriod <= relese;
default: envStepPeriod <= 16'h0;
endcase
end
 
 
// double the delay at appropriate points
// for exponential modelling
wire [19:0] envStepPeriod1 = {4'b0,envStepPeriod} << icnt[sel];
 
 
// handle the clock divider
// loadable down counter
// This sets the period of each step of the envelope
always @(posedge clk)
if (rst) begin
for (n = 0; n < pChannels; n = n + 1)
envDvn[n] <= 0;
end
else if (cnt < pChannels) begin
if (envDvnx==20'h0)
envDvn[sel] <= envStepPeriod1;
else
envDvn[sel] <= envDvnx - 1;
end
 
assign o = envCtrx;
 
endmodule
 
 
/trunk/rtl/verilog/rtfRandom.v
0,0 → 1,151
// ============================================================================
// 2011 Robert Finch
// robfinch@<remove>opencores.ca
//
// rtfRandom.v
// Random number generator.
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Reg no.
// 0 random output bits [31:16]
// 1 random output bits [15: 0]
// 2 not used
// 3 not used
// 4 m_z seed setting bits [31:16]
// 5 m_z seed setting bits [15 :0]
// 6 m_w seed setting bits [31:16]
// 7 m_w seed setting bits [15 :0]
//
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |WISHBONE Datasheet
// |WISHBONE SoC Architecture Specification, Revision B.3
// |
// |Description: Specifications:
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |General Description: random number generator
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Supported Cycles: SLAVE,READ/WRITE
// | SLAVE,BLOCK READ/WRITE
// | SLAVE,RMW
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Data port, size: 16 bit
// |Data port, granularity: 16 bit
// |Data port, maximum operand size: 16 bit
// |Data transfer ordering: Undefined
// |Data transfer sequencing: Undefined
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Clock frequency constraints: none
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Supported signal list and Signal Name WISHBONE equiv.
// |cross reference to equivalent ack_o ACK_O
// |WISHBONE signals adr_i[43:0] ADR_I()
// | clk_i CLK_I
// | rst_i RST_I()
// | dat_i(15:0) DAT_I()
// | dat_o(15:0) DAT_O()
// | cyc_i CYC_I
// | stb_i STB_I
// | we_i WE_I
// |
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |Special requirements:
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
// ============================================================================
//
// Uses George Marsaglia's multiply method
//
// m_w = <choose-initializer>; /* must not be zero */
// m_z = <choose-initializer>; /* must not be zero */
//
// uint get_random()
// {
// m_z = 36969 * (m_z & 65535) + (m_z >> 16);
// m_w = 18000 * (m_w & 65535) + (m_w >> 16);
// return (m_z << 16) + m_w; /* 32-bit result */
// }
//
module rtfRandom(rst_i, clk_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o, vol_o);
input rst_i;
input clk_i;
input cyc_i;
input stb_i;
output ack_o;
input we_i;
input [43:0] adr_i;
input [15:0] dat_i;
output [15:0] dat_o;
reg [15:0] dat_o;
output vol_o; // outputting a vclatile register
 
wire cs = cyc_i && stb_i && (adr_i[43:4]==40'hFFF_FFDC_0C0);
assign ack_o = cs;
assign vol_o = cs && !we_i && (adr_i[3:1]==3'd0 || adr_i[3:1]==3'd1);
 
reg [31:0] m_z;
reg [31:0] m_w;
reg [31:0] next_m_z;
reg [31:0] next_m_w;
reg [31:0] out;
 
always @(m_z or m_w)
begin
next_m_z <= (18'h36969 * m_z[15:0]) + m_z[31:16];
next_m_w <= (18'h18000 * m_w[15:0]) + m_w[31:16];
end
 
// Register read path
//
always @(cs or adr_i or out or m_z or m_w)
if (cs)
case(adr_i[3:1])
3'd0: dat_o <= out[31:16];
3'd1: dat_o <= out[15: 0];
// Uncomment these for register read-back
// 3'd4: dat_o <= m_z[31:16];
// 3'd5: dat_o <= m_z[15: 0];
// 3'd6: dat_o <= m_w[31:16];
// 3'd7: dat_o <= m_w[15: 0];
endcase
else
dat_o <= 16'h0000;
 
// Register write path
//
always @(posedge clk_i)
if (rst_i) begin
m_z <= 32'h01234567; // These must be non-zero
m_w <= 32'h88888888;
end
else begin
if (cs) begin
if (we_i)
case(adr_i[3:1])
3'd4: m_z[31:16] <= dat_i;
3'd5: m_z[15: 0] <= dat_i;
3'd6: m_w[31:16] <= dat_i;
3'd7: m_w[15: 0] <= dat_i;
endcase
// cycle the generator on a read
else begin
m_z <= next_m_z;
m_w <= next_m_w;
out <= {m_z[15:0],16'd0} + m_w;
end
end
end
 
endmodule
/trunk/rtl/verilog/PSGMasterVolumeControl.v
0,0 → 1,53
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
rob@birdcomputer.ca
 
bcPSGMasterVolumeControl.v
Controls the PSG's output volume.
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
============================================================================ */
 
module PSGMasterVolumeControl(rst_i, clk_i, i, volume, o);
input rst_i;
input clk_i;
input [15:0] i;
input [3:0] volume;
output [15:0] o;
reg [15:0] o;
 
// Multiply 16x4 bits
wire [19:0] v1 = volume[0] ? i : 20'd0;
wire [19:0] v2 = volume[1] ? {i,1'b0} + v1: v1;
wire [19:0] v3 = volume[2] ? {i,2'b0} + v2: v2;
wire [19:0] vo = volume[3] ? {i,3'b0} + v3: v3;
 
always @(posedge clk_i)
if (rst_i)
o <= 16'b0; // Force the output volume to zero on reset
else
o <= vo[15:0];
 
endmodule
 
/trunk/rtl/verilog/PSGFilter.v
0,0 → 1,105
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
 
PSGFilter.v
Version 1.1
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
16-tap digital filter
 
Currently this filter is only partially tested. The author believes that
the approach used is valid however.
The author opted to include the filter because it is part of the design,
and even this untested component can provide an idea of the resource
requirements, and device capabilities.
This is a "how one might approach the problem" example, at least
until the author is sure the filter is working correctly.
Time division multiplexing is used to implement this filter in order to
reduce the resource requirement. This should be okay because it is being
used to filter audio signals. The effective operating frequency of the
filter depends on the 'cnt' supplied (eg 1MHz)
 
Spartan3
Webpack 9.1i xc3s1000-4ft256
158 LUTs / 88 slices / 73.865MHz
1 MULT
============================================================================ */
 
module PSGFilter(rst, clk, cnt, wr, adr, din, i, o);
parameter pTaps = 16;
input rst;
input clk;
input [7:0] cnt;
input wr;
input [3:0] adr;
input [12:0] din;
input [14:0] i;
output [14:0] o;
reg [14:0] o;
 
reg [30:0] acc; // accumulator
reg [14:0] tap [0:pTaps-1]; // tap registers
integer n;
 
// coefficient memory
reg [11:0] coeff [0:pTaps-1]; // magnitude of coefficient
reg [pTaps-1:0] sgn; // sign of coefficient
 
 
// update coefficient memory
always @(posedge clk)
if (wr) begin
coeff[adr] <= din[11:0];
sgn[adr] <= din[12];
end
 
// shift taps
// Note: infer a dsr by NOT resetting the registers
always @(posedge clk)
if (cnt==8'd0) begin
tap[0] <= i;
for (n = 1; n < pTaps; n = n + 1)
tap[n] <= tap[n-1];
end
 
wire [26:0] mult = coeff[cnt[3:0]] * tap[cnt[3:0]];
 
always @(posedge clk)
if (rst)
acc <= 0;
else if (cnt==8'd0)
acc <= sgn[cnt[3:0]] ? 0 - mult : 0 + mult;
else if (cnt < pTaps)
acc <= sgn[cnt[3:0]] ? acc - mult : acc + mult;
 
always @(posedge clk)
if (rst)
o <= 0;
else if (cnt==8'd0)
o <= acc[30:16];
 
endmodule
 
/trunk/rtl/verilog/PSG16.v
0,0 → 1,478
//=============================================================================
// 2007,2010 Robert Finch
// robfinch@FPGAfield.ca
//
// PSG16.v
// 4 Channel ADSR sound generator
//
// This source code is available only for veiwing, testing and evaluation
// purposes. Any commercial use requires a license. This copyright
// statement and disclaimer must remain present in the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// Registers
// 0 ffffffff ffffffff freq [15:0]
// 1 ----pppp pppppppp pulse width [11:0]
// 2 trsg--fo -vvvvv-- test, ringmod, sync, gate, filter, output, voice type
// vvvvv
// wnpst
// 3 -------- -------- reserved
// 4 aaaaaaaa aaaaaaaa attack
// 5 ----dddd dddddddd decay
// 6 -------- ssssssss sustain
// 7 ----rrrr rrrrrrrr release
// ...
// 64 -------- ----vvvv volume (0-15)
// 65 nnnnnnnn nnnnnnnn osc3 oscillator 3
// 66 -------- nnnnnnnn env3 envelope 3
// 67
// 68 aa------ -------- wave table address a15-14
// 69 aaaaaaaa aaaaaaaa wave table address a31-16
//
// 80-87 s---kkkk kkkkkkkk filter coefficients
// 88-96 -------- -------- reserved for more filter coefficients
//
//
// Spartan3
// Webpack 12.3 xc3s1200e-4fg320
// 1290 LUTs / 893 slices / 69.339 MHz
// 1 Multipliers
//=============================================================================
 
module PSG16(rst_i, clk_i, cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
vol_o, bg,
m_cyc_o, m_stb_o, m_ack_i, m_we_o, m_sel_o, m_adr_o, m_dat_i, o
);
parameter pClkDivide = 66;
 
// WISHBONE SYSCON
input rst_i;
input clk_i; // system clock
// WISHBONE SLAVE
input cyc_i; // cycle valid
input stb_i; // circuit select
output ack_o;
input we_i; // write
input [1:0] sel_i; // byte selects
input [43:0] adr_i; // address input
input [15:0] dat_i; // data input
output [15:0] dat_o; // data output
// WISHBONE MASTER
output m_cyc_o; // bus request
output m_stb_o; // strobe output
input m_ack_i;
output m_we_o; // write enable (always inactive)
output [ 1:0] m_sel_o; // byte lane selects
output [43:0] m_adr_o; // wave table address
input [11:0] m_dat_i; // wave table data input
 
output vol_o;
 
input bg; // bus grant
 
output [11:0] o;
 
// I/O registers
reg [15:0] dat_o;
reg vol_o;
reg [43:0] m_adr_o;
 
reg [3:0] test; // test (enable note generator)
reg [4:0] vt [3:0]; // voice type
reg [15:0] freq0, freq1, freq2, freq3; // frequency control
reg [11:0] pw0, pw1, pw2, pw3; // pulse width control
reg [3:0] gate;
reg [15:0] attack0, attack1, attack2, attack3;
reg [11:0] decay0, decay1, decay2, decay3;
reg [7:0] sustain0, sustain1, sustain2, sustain3;
reg [11:0] relese0, relese1, relese2, relese3;
reg [3:0] sync;
reg [3:0] ringmod;
reg [3:0] outctrl;
reg [3:0] filt; // 1 = output goes to filter
wire [23:0] acc0, acc1, acc2, acc3;
reg [3:0] volume; // master volume
wire [11:0] ngo; // not generator output
wire [7:0] env; // envelope generator output
wire [7:0] env3;
wire [7:0] ibr;
wire [7:0] ibg;
wire [21:0] out1;
wire [21:0] out3;
wire [19:0] out4;
wire [21:0] filtin1; // FIR filter input
wire [14:0] filt_o; // FIR filter output
 
wire cs = cyc_i && stb_i && (adr_i[43:8]==36'hFFF_FFD4_00);
assign m_cyc_o = |ibr & ~bg;
assign m_stb_o = m_cyc_o;
assign m_we_o = 1'b0;
assign m_sel_o = {m_cyc_o,m_cyc_o};
assign ack_o = cs;
wire my_ack = m_ack_i;
 
// write to registers
always @(posedge clk_i)
begin
if (rst_i) begin
freq0 <= 0;
freq1 <= 0;
freq2 <= 0;
freq3 <= 0;
pw0 <= 0;
pw1 <= 0;
pw2 <= 0;
pw3 <= 0;
test <= 0;
vt[0] <= 0;
vt[1] <= 0;
vt[2] <= 0;
vt[3] <= 0;
gate <= 0;
outctrl <= 0;
filt <= 0;
attack0 <= 0;
attack1 <= 0;
attack2 <= 0;
attack3 <= 0;
decay0 <= 0;
sustain0 <= 0;
relese0 <= 0;
decay1 <= 0;
sustain1 <= 0;
relese1 <= 0;
decay2 <= 0;
sustain2 <= 0;
relese2 <= 0;
decay3 <= 0;
sustain3 <= 0;
relese3 <= 0;
sync <= 0;
ringmod <= 0;
volume <= 0;
m_adr_o[31:14] <= 18'b0000_0000_0000_0011_10; // 00038000
end
else begin
if (ack_o & we_i) begin
case(adr_i[7:1])
7'd0:
begin
if (sel_i[0]) freq0[ 7:0] <= dat_i[ 7:0];
if (sel_i[1]) freq0[15:8] <= dat_i[15:8];
end
7'd1:
begin
if (sel_i[0]) pw0[ 7:0] <= dat_i[ 7:0];
if (sel_i[1]) pw0[11:8] <= dat_i[11:8];
end
7'd2: begin
if (sel_i[0]) vt[0] <= dat_i[6:2];
if (sel_i[1]) begin
outctrl[0] <= dat_i[8];
filt[0] <= dat_i[9];
gate[0] <= dat_i[12];
sync[0] <= dat_i[13];
ringmod[0] <= dat_i[14];
test[0] <= dat_i[15];
end
end
7'd3: ;
7'd4: attack0 <= dat_i;
7'd5: decay0 <= dat_i;
7'd6: if (sel_i[0]) sustain0 <= dat_i;
7'd7: relese0 <= dat_i;
 
7'd8:
begin
if (sel_i[0]) freq1[ 7:0] <= dat_i[ 7:0];
if (sel_i[1]) freq1[15:8] <= dat_i[15:8];
end
7'd9:
begin
if (sel_i[0]) pw1[ 7:0] <= dat_i[ 7:0];
if (sel_i[1]) pw1[11:8] <= dat_i[11:8];
end
7'd10: begin
if (sel_i[0]) vt[1] <= dat_i[6:2];
if (sel_i[1]) begin
outctrl[1] <= dat_i[8];
filt[1] <= dat_i[9];
gate[1] <= dat_i[12];
sync[1] <= dat_i[13];
ringmod[1] <= dat_i[14];
test[1] <= dat_i[15];
end
end
7'd11: ;
7'd12: attack1 <= dat_i;
7'd13: decay1 <= dat_i;
7'd14: if (sel_i[0]) sustain1 <= dat_i;
7'd15: relese1 <= dat_i;
 
7'd16:
begin
if (sel_i[0]) freq2[ 7:0] <= dat_i[ 7:0];
if (sel_i[1]) freq2[15:8] <= dat_i[15:8];
end
7'd17:
begin
if (sel_i[0]) pw2[ 7:0] <= dat_i[ 7:0];
if (sel_i[1]) pw2[11:8] <= dat_i[11:8];
end
7'd18: begin
if (sel_i[0]) vt[2] <= dat_i[6:2];
if (sel_i[1]) begin
outctrl[2] <= dat_i[8];
filt[2] <= dat_i[9];
gate[2] <= dat_i[12];
sync[2] <= dat_i[5];
outctrl[0] <= dat_i[13];
ringmod[2] <= dat_i[14];
test[2] <= dat_i[15];
end
end
7'd19: ;
7'd20: attack2 <= dat_i;
7'd21: decay2 <= dat_i;
7'd22: if (sel_i[0]) sustain2 <= dat_i;
7'd23: relese2 <= dat_i;
 
7'd24:
begin
if (sel_i[0]) freq3[ 7:0] <= dat_i[ 7:0];
if (sel_i[1]) freq3[15:8] <= dat_i[15:8];
end
7'd25:
begin
if (sel_i[0]) pw3[ 7:0] <= dat_i[ 7:0];
if (sel_i[1]) pw3[11:8] <= dat_i[11:8];
end
7'd26: begin
if (sel_i[0]) vt[3] <= dat_i[6:2];
if (sel_i[1]) begin
outctrl[3] <= dat_i[8];
filt[3] <= dat_i[9];
gate[3] <= dat_i[12];
sync[3] <= dat_i[13];
ringmod[3] <= dat_i[14];
test[3] <= dat_i[15];
end
end
7'd27: ;
7'd28: attack3 <= dat_i;
7'd29: decay3 <= dat_i;
7'd30: if (sel_i[0]) sustain3 <= dat_i;
7'd31: relese3 <= dat_i;
 
7'd64: if (sel_i[0]) volume <= dat_i[3:0];
 
7'd68: begin
if (sel_i[1]) m_adr_o[15:14] <= dat_i[15:14];
end
7'd69:
begin
if (sel_i[0]) m_adr_o[23:16] <= dat_i[ 7:0];
if (sel_i[1]) m_adr_o[31:24] <= dat_i[15:8];
end
7'd70: begin
if (sel_i[0]) m_adr_o[39:32] <= dat_i[ 7:0];
if (sel_i[1]) m_adr_o[43:40] <= dat_i[11:8];
end
default: ;
endcase
end
end
end
 
 
always @(adr_i or acc3 or env3 or cs)
begin
if (cs) begin
case(adr_i[6:0])
7'd65: begin
vol_o <= 1'b1;
dat_o <= acc3[23:8];
end
7'd66: begin
vol_o <= 1'b1;
dat_o <= env3;
end
default: begin
dat_o <= env3;
vol_o <= 1'b0;
end
endcase
end
else begin
dat_o <= 16'b0;
vol_o <= 1'b0;
end
end
 
wire [3:0] ibg1 = ibg & {4{bg}};
wire [11:0] alow;
 
// set wave table output address
always @(ibg1 or acc1 or acc0 or acc2 or acc3 or alow)
begin
m_adr_o[13:12] <= {ibg1[2]|ibg1[3],ibg1[1]|ibg1[3]};
m_adr_o[11:0] <= alow;
end
 
mux4to1 #(12) u11
(
.e(1'b1),
.s(m_adr_o[13:12]),
.i0({acc0[23:13],1'b0}),
.i1({acc1[23:13],1'b0}),
.i2({acc2[23:13],1'b0}),
.i3({acc3[23:13],1'b0}),
.z(alow)
);
 
// This counter controls channel multiplexing and the base
// operating frequency.
wire [7:0] cnt;
counter #(8) u1
(
.rst(rst_i),
.clk(clk_i),
.ce(1'b1),
.ld(cnt!=pClkDivide),
.d(8'd1),
.q(cnt)
);
 
// channel select signal
wire [1:0] sel = cnt[1:0];
 
 
// bus arbitrator for wave table access
wire [2:0] bgn;
PSGBusArb u2
(
.rst(rst_i),
.clk(clk_i),
.ce(1'b1),
.ack(1'b1), .seln(bgn),
.req0(ibr[0]), .req1(ibr[1]), .req2(ibr[2]), .req3(ibr[3]),
.sel0(ibg[0]), .sel1(ibg[1]), .sel2(ibg[2]), .sel3(ibg[3]),
.req4(1'b0), .req5(1'b0), .req6(1'b0), .req7(1'b0),
.sel4(), .sel5(), .sel6(), .sel7()
);
 
// note generator - multi-channel
PSGNoteGen u3
(
.rst(rst_i), .clk(clk_i),
.cnt(cnt), .br(ibr), .bg(ibg1), .ack(my_ack), .bgn(bgn),
.test(test),
.vt0(vt[0]), .vt1(vt[1]), .vt2(vt[2]), .vt3(vt[3]),
.freq0(freq0), .freq1(freq1), .freq2(freq2), .freq3(freq3),
.pw0(pw0), .pw1(pw1), .pw2(pw2), .pw3(pw3),
.acc0(acc0), .acc1(acc1), .acc2(acc2), .acc3(acc3),
.wave(m_dat_i),
.sync(sync),
.ringmod(ringmod),
.o(ngo)
);
 
// envelope generator - multi-channel
PSGEnvGen u4
(
.rst(rst_i),
.clk(clk_i),
.cnt(cnt),
.gate(gate),
.attack0(attack0), .attack1(attack1), .attack2(attack2), .attack3(attack3),
.decay0(decay0), .decay1(decay1), .decay2(decay2), .decay3(decay3),
.sustain0(sustain0), .sustain1(sustain1), .sustain2(sustain2), .sustain3(sustain3),
.relese0(relese0), .relese1(relese1), .relese2(relese2), .relese3(relese3),
.o(env)
);
 
// shape output according to envelope
PSGShaper u5
(
.clk_i(clk_i),
.ce(1'b1),
.tgi(ngo),
.env(env),
.o(out2)
);
 
// Sum the channels not going to the filter
PSGChannelSummer u6
(
.clk_i(clk_i),
.cnt(cnt),
.outctrl(outctrl),
.tmc_i(out2),
.o(out1)
);
 
// Sum the channels going to the filter
PSGChannelSummer u7
(
.clk_i(clk_i),
.cnt(cnt),
.outctrl(filt),
.tmc_i(out2),
.o(filtin1)
);
 
// The FIR filter
PSGFilter u8
(
.rst(rst_i),
.clk(clk_i),
.cnt(cnt),
.wr(we_i && stb_i && adr_i[6:4]==3'b101),
.adr(adr_i[3:0]),
.din({dat_i[15],dat_i[11:0]}),
.i(filtin1[21:7]),
.o(filt_o)
);
 
// Sum the filtered and unfiltered output
PSGOutputSummer u9
(
.clk_i(clk_i),
.cnt(cnt),
.ufi(out1),
.fi({filt_o,7'b0}),
.o(out3)
);
 
// Last stage:
// Adjust output according to master volume
PSGMasterVolumeControl u10
(
.rst_i(rst_i),
.clk_i(clk_i),
.i(out3[21:6]),
.volume(volume),
.o(out4)
);
 
assign o = out4[19:8];
 
endmodule
 
/trunk/rtl/verilog/PSGNoteOutMux.v
0,0 → 1,57
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
 
bcPSGNoteOutMux.v
Version 1.0
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
Selects from one of five waveforms for output. Selected waveform
outputs are anded together. This is approximately how the
original SID worked.
 
Spartan3
Webpack 9.1i xc3s1000-4ft256
36 LUTs / 21 slices / 11ns
============================================================================ */
 
module PSGNoteOutMux(s, a, b, c, d, e, o);
parameter WID = 12;
input [4:0] s;
input [WID-1:0] a,b,c,d,e;
output [WID-1:0] o;
 
wire [WID-1:0] o1,o2,o3,o4,o5;
 
assign o1 = s[4] ? e : {WID{1'b1}};
assign o2 = s[3] ? d : {WID{1'b1}};
assign o3 = s[2] ? c : {WID{1'b1}};
assign o4 = s[1] ? b : {WID{1'b1}};
assign o5 = s[0] ? a : {WID{1'b1}};
 
assign o = o1 & o2 & o3 & o4 & o5;
 
endmodule
 
 
/trunk/rtl/verilog/rtfTextController.v
0,0 → 1,526
// ============================================================================
// (C) 2006-2011 Robert Finch
// robfinch@<remove>opencores.org
//
// rtfTextController.v
// text controller
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// Text Controller
//
// FEATURES
//
// This core requires an external timing generator to provide horizontal
// and vertical sync signals, but otherwise can be used as a display
// controller on it's own. However, this core may also be embedded within
// another core such as a VGA controller.
//
// Window positions are referenced to the rising edge of the vertical and
// horizontal sync pulses.
//
// The core includes an embedded dual port RAM to hold the screen
// characters.
//
//
//--------------------------------------------------------------------
// Registers
//
// 00 - nnnnnnnn number of columns (horizontal displayed number of characters)
// 01 - nnnnnnnn number of rows (vertical displayed number of characters)
// 02 - n nnnnnnnn window left (horizontal sync position - reference for left edge of displayed)
// 03 - n nnnnnnnn window top (vertical sync position - reference for the top edge of displayed)
// 04 - ---nnnnn maximum scan line (char ROM max value is 7)
// 05 - hhhhwwww pixel size, hhhh=height,wwww=width
// 07 - ---nnnnn color code for transparent background
// 08 - -BPnnnnn cursor start / blink control
// BP: 00=no blink
// BP: 01=no display
// BP: 10=1/16 field rate blink
// BP: 11=1/32 field rate blink
// 09 - ----nnnnn cursor end
// 10 - aaaaaaaa aaaaaaaaa start address (index into display memory)
// 11 - aaaaaaaa aaaaaaaaa cursor position
// 12 - aaaaaaaa aaaaaaaaa light pen position
//--------------------------------------------------------------------
//
// ============================================================================
 
module rtfTextController(
rst_i, clk_i,
cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
lp, curpos,
vclk, eol, eof, blank, border, rgbIn, rgbOut
);
parameter COLS = 12'd52;
parameter ROWS = 12'd31;
 
// Syscon
input rst_i; // reset
input clk_i; // clock
 
// Slave signals
input cyc_i; // cycle valid
input stb_i; // data strobe
output ack_o; // transfer acknowledge
input we_i; // write
input [ 1:0] sel_i; // byte select
input [31:0] adr_i; // address
input [15:0] dat_i; // data input
output [15:0] dat_o; // data output
reg [15:0] dat_o;
 
//
input lp; // light pen
input [15:0] curpos; // cursor position
 
// Video signals
input vclk; // video dot clock
input eol; // end of scan line
input eof; // end of frame
input blank; // blanking signal
input border; // border area
input [24:0] rgbIn; // input pixel stream
output reg [24:0] rgbOut; // output pixel stream
 
 
wire [23:0] bkColor24; // background color
wire [23:0] fgColor24; // foreground color
wire [23:0] tcColor24; // transparent color
 
wire pix; // pixel value from character generator 1=on,0=off
 
reg [15:0] rego;
reg [11:0] windowTop;
reg [11:0] windowLeft;
reg [11:0] numCols;
reg [11:0] numRows;
reg [ 1:0] mode;
reg [ 4:0] maxScanline;
reg [ 4:0] maxScanpix;
reg [ 4:0] cursorStart, cursorEnd;
reg [15:0] cursorPos;
reg [15:0] startAddress;
reg [ 2:0] rBlink;
reg [ 3:0] bdrColorReg;
reg [ 3:0] pixelWidth; // horizontal pixel width in clock cycles
reg [ 3:0] pixelHeight; // vertical pixel height in scan lines
 
wire [11:0] hctr; // horizontal reference counter (counts clocks since hSync)
wire [11:0] scanline; // scan line
wire [11:0] row; // vertical reference counter (counts rows since vSync)
wire [11:0] col; // horizontal column
reg [ 4:0] rowscan; // scan line within row
wire nxt_row; // when to increment the row counter
wire nxt_col; // when to increment the column counter
wire [ 5:0] bcnt; // blink timing counter
wire blink;
reg iblank;
 
wire nhp; // next horizontal pixel
wire ld_shft = nxt_col & nhp;
 
 
// display and timing signals
reg [15:0] txtAddr; // index into memory
reg [15:0] penAddr;
wire [8:0] txtOut; // character code
wire [7:0] charOut; // character ROM output
wire [3:0] txtBkCode; // background color code
wire [4:0] txtFgCode; // foreground color code
reg [4:0] txtTcCode; // transparent color code
reg bgt;
 
wire [8:0] tdat_o;
wire [8:0] cdat_o;
wire [7:0] chdat_o;
 
wire [2:0] scanindex = scanline[2:0];
 
 
//--------------------------------------------------------------------
// Address Decoding
// I/O range FFDx
//--------------------------------------------------------------------
wire cs_text = cyc_i && stb_i && (adr_i[31:16]==16'hFFD0);
wire cs_color= cyc_i && stb_i && (adr_i[31:16]==16'hFFD1);
wire cs_rom = cyc_i && stb_i && (adr_i[31:16]==16'hFFD2);
wire cs_reg = cyc_i && stb_i && (adr_i[31: 8]==24'hFFDA_00);
 
 
always @(cs_text or cs_color or cs_rom or cs_reg or tdat_o or cdat_o or chdat_o or rego)
if (cs_text) dat_o <= tdat_o;
else if (cs_color) dat_o <= cdat_o;
else if (cs_rom) dat_o <= chdat_o;
else if (cs_reg) dat_o <= rego;
else dat_o <= 16'h0000;
 
 
//--------------------------------------------------------------------
// Video Memory
//--------------------------------------------------------------------
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Address Calculation:
// - Simple: the row times the number of cols plus the col plue the
// base screen address
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
wire [17:0] rowcol = row * numCols;
always @(posedge vclk)
txtAddr <= startAddress + rowcol + col;
 
// text screen RAM
syncRam4kx9_1rw1r textRam0
(
.wclk(clk_i),
.wadr(adr_i[13:1]),
.i(dat_i),
.wo(tdat_o),
.wce(cs_text),
.we(we_i),
.wrst(1'b0),
 
.rclk(vclk),
.radr(txtAddr[12:0]),
.o(txtOut),
.rce(ld_shft),
.rrst(1'b0)
);
 
// screen attribute RAM
syncRam4kx9_1rw1r colorRam0
(
.wclk(clk_i),
.wadr(adr_i[13:1]),
.i(dat_i),
.wo(cdat_o),
.wce(cs_color),
.we(we_i),
.wrst(1'b0),
 
.rclk(vclk),
.radr(txtAddr[12:0]),
.o({txtBkCode,txtFgCode}),
.rce(ld_shft),
.rrst(1'b0)
);
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Character bitmap ROM
// - room for 512 characters
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
syncRam4kx9_1rw1r charRam0
(
.wclk(clk_i),
.wadr(adr_i[11:0]),
.i(dat_i),
.wo(chdat_o),
.wce(cs_rom),
.we(we_i),
.wrst(1'b0),
 
.rclk(vclk),
.radr({txtOut,rowscan[2:0]}),
.o(charOut),
.rce(ld_shft),
.rrst(1'b0)
);
 
 
// pipeline delay - sync color with character bitmap output
reg [3:0] txtBkCode1;
reg [4:0] txtFgCode1;
always @(posedge vclk)
if (nhp & ld_shft) txtBkCode1 <= txtBkCode;
always @(posedge vclk)
if (nhp & ld_shft) txtFgCode1 <= txtFgCode;
 
//--------------------------------------------------------------------
// bus interfacing
// - there is a one cycle latency for reads, an ack is generated
// after the synchronous RAM read
// - writes can be acknowledged right away.
//--------------------------------------------------------------------
reg ramRdy;
always @(posedge clk_i)
ramRdy = cs_text|cs_rom|cs_color|cs_reg;
 
assign ack_o = (cyc_i & stb_i) ? (we_i ? (cs_text|cs_color|cs_rom|cs_reg) : ramRdy) : 1'b0;
 
 
//--------------------------------------------------------------------
// Registers
//
// 00 - nnnnnnnn number of columns (horizontal displayed number of characters)
// 01 - nnnnnnnn number of rows (vertical displayed number of characters)
// 02 - n nnnnnnnn window left (horizontal sync position - reference for left edge of displayed)
// 03 - n nnnnnnnn window top (vertical sync position - reference for the top edge of displayed)
// 04 - ---nnnnn maximum scan line (char ROM max value is 7)
// 05 - hhhhwwww pixel size, hhhh=height,wwww=width
// 08 - -BPnnnnn cursor start / blink control
// BP: 00=no blink
// BP: 01=no display
// BP: 10=1/16 field rate blink
// BP: 11=1/32 field rate blink
// 09 - ----nnnnn cursor end
// 10 - aaaaaaaa aaaaaaaaa start address (index into display memory)
// 11 - aaaaaaaa aaaaaaaaa cursor position
// 12 - aaaaaaaa aaaaaaaaa light pen position
//--------------------------------------------------------------------
 
//--------------------------------------------------------------------
// Light Pen
//--------------------------------------------------------------------
wire lpe;
edge_det u1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(lp), .pe(lpe), .ne(), .ee() );
 
always @(posedge clk_i)
if (rst_i)
penAddr <= 32'h0000_0000;
else begin
if (lpe)
penAddr <= txtAddr;
end
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Register read port
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
always @(cs_reg or cursorPos or penAddr or adr_i)
if (cs_reg) begin
case(adr_i[4:1])
4'd0: rego <= numCols;
4'd1: rego <= numRows;
4'd11: rego <= cursorPos;
4'd12: rego <= penAddr;
default: rego <= 16'h0000;
endcase
end
else
rego <= 16'h0000;
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Register write port
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
reg interlace;
always @(posedge clk_i)
if (rst_i) begin
// 104x63
/*
windowTop <= 12'd26;
windowLeft <= 12'd260;
pixelWidth <= 4'd0;
pixelHeight <= 4'd1; // 525 pixels (408 with border)
*/
// 52x31
windowTop <= 12'd14;
windowLeft <= 12'd117;
pixelWidth <= 4'd1;
pixelHeight <= 4'd3; // 262 pixels (248 with border)
 
numCols <= COLS;
numRows <= ROWS;
maxScanline <= 5'd7;
maxScanpix <= 5'd7;
rBlink <= 3'b111; // 01 = non display
startAddress <= 16'h0000;
cursorStart <= 5'd00;
cursorEnd <= 5'd31;
cursorPos <= 16'h0003;
txtTcCode <= 5'd31;
end
else begin
if (cs_reg & we_i) begin // register write ?
 
case(adr_i[4:1])
4'd00: numCols <= dat_i; // horizontal displayed
4'd01: numRows <= dat_i;
4'd02: windowLeft <= dat_i[11:0];
4'd03: windowTop <= dat_i[11:0]; // vertical sync position
4'd04: maxScanline <= dat_i[4:0];
4'd05: begin
pixelHeight <= dat_i[7:4];
pixelWidth <= dat_i[3:0]; // horizontal pixel width
end
4'd07: txtTcCode <= dat_i[4:0];
4'd08: begin
cursorStart <= dat_i[4:0]; // scan line sursor starts on
rBlink <= dat_i[7:5];
end
4'd09: cursorEnd <= dat_i[4:0]; // scan line cursor ends on
4'd10: startAddress <= dat_i;
4'd11: cursorPos <= dat_i;
endcase
end
end
 
 
//--------------------------------------------------------------------
//--------------------------------------------------------------------
 
// "Box" cursor bitmap
reg [7:0] curout;
always @(scanindex)
case(scanindex)
3'd0: curout = 8'b11111111;
3'd1: curout = 8'b10000001;
3'd2: curout = 8'b10000001;
3'd3: curout = 8'b10000001;
3'd4: curout = 8'b10000001;
3'd5: curout = 8'b10000001;
3'd6: curout = 8'b10011001;
3'd7: curout = 8'b11111111;
endcase
 
 
//-------------------------------------------------------------
// Video Stuff
//-------------------------------------------------------------
 
// Horizontal counter:
//
 
HVCounter uhv1
(
.rst(rst_i),
.vclk(vclk),
.pixcce(1'b1),
.sync(eol),
.cnt_offs(windowLeft),
.pixsz(pixelWidth),
.maxpix(maxScanpix),
.nxt_pix(nhp),
.pos(col),
.nxt_pos(nxt_col),
.ctr(hctr)
);
 
 
// Vertical counter:
//
HVCounter uhv2
(
.rst(rst_i),
.vclk(vclk),
.pixcce(eol),
.sync(eof),
.cnt_offs(windowTop),
.pixsz(pixelHeight),
.maxpix(maxScanline),
.nxt_pix(nvp),
.pos(row),
.nxt_pos(nxt_row),
.ctr(scanline)
);
 
always @(posedge vclk)
rowscan <= scanline - row * (maxScanline+1);
 
 
// Blink counter
//
VT163 #(6) ub1
(
.clk(vclk),
.clr_n(!rst_i),
.ent(eol & eof),
.enp(1'b1),
.ld_n(1'b1),
.d(6'd0),
.q(bcnt)
);
 
wire blink_en = (cursorPos+2==txtAddr) && (scanline[4:0] >= cursorStart) && (scanline[4:0] <= cursorEnd);
 
VT151 ub2
(
.e_n(!blink_en),
.s(rBlink),
.i0(1'b1), .i1(1'b0), .i2(bcnt[4]), .i3(bcnt[5]),
.i4(1'b1), .i5(1'b0), .i6(bcnt[4]), .i7(bcnt[5]),
.z(blink),
.z_n()
);
 
// These tables map a five bit color code to an eight bit color value.
rtfColorROM ucm1 (.clk(vclk), .ce(nhp & ld_shft), .code(txtBkCode1), .color(bkColor24) );
rtfColorROM ucm2 (.clk(vclk), .ce(nhp & ld_shft), .code(txtFgCode1), .color(fgColor24) );
always @(posedge vclk)
if (nhp & ld_shft)
bgt <= {1'b0,txtBkCode1}==txtTcCode;
 
 
// Convert character bitmap to pixels
// For convenience, the character bitmap data in the ROM is in the
// opposite bit order to what's needed for the display. The following
// just alters the order without adding any hardware.
//
wire [7:0] charRev = {
charOut[0],
charOut[1],
charOut[2],
charOut[3],
charOut[4],
charOut[5],
charOut[6],
charOut[7]
};
 
wire [7:0] charout1 = blink ? (charRev ^ curout) : charRev;
 
// Convert parallel to serial
ParallelToSerial ups1
(
.rst(rst_i),
.clk(vclk),
.ce(nhp),
.ld(ld_shft),
.qin(1'b0),
.d(charout1),
.qh(pix)
);
 
 
// Pipelining Effect:
// - character output is delayed by 3 character times relative to the video counters.
// - this means we must adapt the blanking signal by shifting the blanking window
// three character times.
wire bpix = hctr[1] ^ scanline[4];// ^ blink;
always @(posedge vclk)
if (nhp)
iblank <= (row >= numRows) || (col >= numCols + 3) || (col < 3);
 
// Choose between input RGB and controller generated RGB
// Select between foreground and background colours.
always @(posedge vclk)
if (nhp) begin
casex({blank,iblank,border,bpix,pix})
5'b1xxxx: rgbOut <= 25'h0000000;
5'b01xxx: rgbOut <= rgbIn;
5'b0010x: rgbOut <= 24'hBF2020;
5'b0011x: rgbOut <= 24'hDFDFDF;
5'b000x0: rgbOut <= bgt ? rgbIn : bkColor24;
5'b000x1: rgbOut <= fgColor24;
default: rgbOut <= rgbIn;
endcase
end
 
endmodule
 
/trunk/rtl/verilog/down_counter.v
0,0 → 1,58
// ============================================================================
// down_counter.v
// - counts down
//
//
// 2010 Robert Finch
// pfingh>remove<@birdcomputer.ca
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// Verilog 1995
// ============================================================================
 
module down_counter(rst, clk, ce, ld, d, q, z);
parameter WID=8;
input rst;
input clk;
input ce;
input ld;
input [WID:1] d;
output [WID:1] q;
reg [WID:1] q;
output z;
 
always @(posedge clk)
if (rst)
q <= 0;
else if (ce) begin
if (ld)
q <= d;
else
q <= q + {WID{1'b1}};
end
 
assign z = q == 0;
 
endmodule
/trunk/rtl/verilog/WXGASyncGen1680x1050_60Hz_tb.v
0,0 → 1,48
// ============================================================================
// 2011 Robert Finch
//
// WXGASyncGen1680x1050_60Hz_tb.v
// WXGA sync generator test bench
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
 
module WXGASyncGen1680x1050_60Hz_tb();
 
reg clk;
reg rst;
 
initial begin
clk = 1;
rst = 0;
#100 rst = 1;
#100 rst = 0;
end
 
always #6.8000 clk = ~clk; // 73.529 MHz
 
WXGASyncGen1680x1050_60Hz u1
(
.rst(rst),
.clk(clk),
.hSync(),
.vSync(),
.blank(),
.border(),
.eol(),
.eof()
);
 
endmodule
/trunk/rtl/verilog/rtf68kSysClkgen.v
0,0 → 1,174
//=============================================================================
// 2005-2010 Robert T Fingh
// robfinch@FPGAfield.ca
//
// rtf68kSysClkgen.v
//
//
// This source code is available only for viewing, testing and evaluation
// purposes. Any commercial use requires a license. This copyright
// statement and disclaimer must remain present in the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// System clock generator. Generates clock enables for various parts of the
// system.
//
//=============================================================================
 
module rtf68kSysClkgen(xreset, xclk, rst, clk50, clk25, vclk, vclk5, pulse1000Hz);
input xreset; // external reset
input xclk; // external clock source (50 MHz)
output rst;
output clk50; // cpu (system clock - eg. 50.000 MHz)
output clk25;
output vclk; // video clock
output vclk5; // 5x vidoe clock
output pulse1000Hz; // 1000 Hz pulse
 
wire gnd;
wire clk39u;
wire clk39ub;
wire clk100u;
wire clkfb;
wire clk2x;
wire clk50u; // unbuffered 60MHz
wire clk73u; // unbuffered 73MHz
wire clkvu;
wire locked0;
wire clk25u;
wire clk147u;
wire clk367u;
 
assign gnd = 1'b0;
 
BUFG bg0 (.I(clk50u), .O(clk50) );
BUFG bg1 (.I(clk73u), .O(vclk) );
BUFG bg2 (.I(clk25u), .O(clk25) );
BUFG bg3 (.I(clk367u), .O(vclk5) );
 
// Reset:
//
// Hold the reset line active for a few thousand clock cycles
// to allow the clock generator and other devices to stabilize.
 
reg [14:0] rst_ctr;
assign rst = xreset | !locked0;// | !rst_ctr[14];
 
always @(posedge xclk)
if (xreset)
rst_ctr <= 0;
else if (!rst_ctr[14])
rst_ctr <= rst_ctr + 1;
 
 
// 1000Hz pulse generator
reg [15:0] cnt;
assign pulse1000Hz = cnt==16'd25000;
 
always @(posedge clk25)
if (rst)
cnt <= 16'd1;
else begin
if (pulse1000Hz)
cnt <= 16'd1;
else
cnt <= cnt + 16'd1;
end
 
 
// connect rst to global network
//STARTUP_SPARTAN3 su0(.GSR(rst));
 
// Generate 73.529 MHz source from 100 MHz
DCM dcm0(
.RST(xreset),
.PSCLK(gnd),
.PSEN(gnd),
.PSINCDEC(gnd),
.DSSEN(gnd),
.CLKIN(xclk),
.CLKFB(clk100u), // 100.000 MHz
.CLKDV(clk25u),
.CLKFX(clk73u), // 73.728 MHz unbuffered
.CLKFX180(),
.CLK0(clk50u),
.CLK2X(clk100u), // 100.000 MHz
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(locked0),
.PSDONE(),
.STATUS()
);
defparam dcm0.CLK_FEEDBACK = "2x";
defparam dcm0.CLKDV_DIVIDE = 3.0;
defparam dcm0.CLKFX_DIVIDE = 17; // (25/17)*50 = 73.529 MHz
defparam dcm0.CLKFX_MULTIPLY = 25;
defparam dcm0.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam dcm0.CLKIN_PERIOD = 20.000;
defparam dcm0.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm0.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam dcm0.DFS_FREQUENCY_MODE = "LOW";
defparam dcm0.DLL_FREQUENCY_MODE = "LOW";
defparam dcm0.DUTY_CYCLE_CORRECTION = "FALSE";
// defparam dcm0.FACTORY_JF = 16'h8080;
defparam dcm0.PHASE_SHIFT = 0;
defparam dcm0.STARTUP_WAIT = "FALSE";
 
wire clkfb1;
 
DCM dcm1(
.RST(xreset),
.PSCLK(gnd),
.PSEN(gnd),
.PSINCDEC(gnd),
.DSSEN(gnd),
.CLKIN(vclk),
.CLKFB(clkfb1), // 73.529 MHz
.CLKDV(),
.CLKFX(clk367u), // 367.645 MHz unbuffered
.CLKFX180(),
.CLK0(),
.CLK2X(clkfb1), // 100.000 MHz
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS()
);
defparam dcm1.CLK_FEEDBACK = "2x";
defparam dcm1.CLKDV_DIVIDE = 2.0;
defparam dcm1.CLKFX_DIVIDE = 2; // (10/2)*73.529 = 367.645 MHz
defparam dcm1.CLKFX_MULTIPLY = 10;
defparam dcm1.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam dcm1.CLKIN_PERIOD = 13.600;
defparam dcm1.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam dcm1.DFS_FREQUENCY_MODE = "LOW";
defparam dcm1.DLL_FREQUENCY_MODE = "LOW";
defparam dcm1.DUTY_CYCLE_CORRECTION = "FALSE";
// defparam dcm0.FACTORY_JF = 16'h8080;
defparam dcm1.PHASE_SHIFT = 0;
defparam dcm1.STARTUP_WAIT = "FALSE";
 
endmodule
/trunk/rtl/verilog/rtf68kSysRAMCtrl.v
0,0 → 1,751
// ============================================================================
// RAMCtrl.v
// - Interface to PSRAM
//
//
// 2010 Robert Finch
// robfinch<remove>@FPGAfield.ca
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// Verilog 1995
// Webpack 9.2i xc3s1200-4fg320
// 177 slices / 339 LUTs / 107.262 MHz
// 120 ff's /
//
// ============================================================================
 
// 36/256 6/16
// 16x with only 6x
// 276 slices / 770 LUTs / 246 FF's / 119.446 MHz
 
module rtf68kSysRAMCtrl
(
rst_i, clk_i, gblen,
as, dtack, rw, uds, lds, adr, dat_i, dat_o,
eppWr, eppRd, eppAdr, eppDati, eppDato, eppHSreq, eppStart, eppDone,
vcti_i, vcyc_i, vack_o, vadr_i, vdat_o,
gr_cyc_i, gr_stb_i, gr_ack_o, gr_we_i, gr_sel_i, gr_adr_i, gr_dat_i, gr_dat_o,
sp_cyc_i, sp_stb_i, sp_ack_o, sp_we_i, sp_sel_i, sp_adr_i, sp_dat_i, sp_dat_o,
ar_cyc_i, ar_stb_i, ar_ack_o, ar_we_i, ar_sel_i, ar_adr_i, ar_dat_i, ar_dat_o,
ap_cyc_i, ap_stb_i, ap_ack_o, ap_we_i, ap_sel_i, ap_adr_i, ap_dat_i, ap_dat_o,
ram_clk, ram_adv, ram_cre, ram_ce, ram_we, ram_oe, ram_lb, ram_ub, ram_a, ram_d, ram_weh,
flash_ce, flash_st, flash_rp
);
parameter pClkFreq = 60000000;
parameter ABIT=24;
// timing parameters must be at least 1
parameter tRC = pClkFreq / 14285714 + 1; // 70 ns
parameter tWC = pClkFreq / 14285714 + 1; // 70 ns
parameter tAPA = pClkFreq / 50000000 + 1; // 20 ns page mode access time
parameter tPWR = pClkFreq / 6667 + 1; // 150 micro seconds
parameter pRCRValue = 23'h000090; // enables page mode (default setting 0010
parameter pBCRValue = 23'h089D1F;
parameter tRCFlash = pClkFreq / 9090909 + 1; // 110 ns
 
// states
parameter POWER_UP = 6'd0;
parameter WRITE_RCR = 6'd1;
parameter WRITE_RCR_WAIT = 6'd2;
parameter WRITE_BCR = 6'd3;
parameter WRITE_BCR_WAIT = 6'd4;
parameter IDLE = 6'd5;
parameter CPU_ACCESS = 6'd6;
parameter CPU_ACCESS1 = 6'd7;
parameter CPU_NACK = 6'd8;
parameter WAIT_NACK = 6'd9;
parameter STORE_WAIT = 6'd12;
parameter FETCH_VIDEO = 6'd13;
parameter FV1 = 6'd14;
parameter FV2 = 6'd15;
parameter FV_NACK = 6'd16;
parameter RANDOMIZE = 6'd17;
parameter RANDOMIZE2 = 6'd18;
 
parameter EPP_STORE = 6'd21;
parameter EPP_FETCH = 6'd22;
parameter EPP_NACK = 6'd23;
 
parameter CPU_STORE = 6'd24;
parameter CPU_STORE2 = 6'd25;
parameter CST_NACK = 6'd26;
 
parameter AP_FETCH = 6'd27;
parameter AP_NACK = 6'd28;
parameter GR_ACCESS = 6'd29;
parameter GR_NACK = 6'd30;
parameter SP_ACCESS = 6'd31;
parameter SP_NACK = 6'd32;
 
parameter WB_CAB=3'b001; // constant address burst
parameter WB_BURST=3'b010; // incrementing burst cycle
parameter WB_EOB=3'b111; // end-of-burst
 
// SYSCON
input rst_i; // system reset
input clk_i; // system clock
input gblen;
// Slave
input as; // cycle valid
output dtack; // transfer acknowledge
input rw; // write enable
input uds;
input lds;
input [43:0] adr; // address
input [15:0] dat_i; // data input
output [15:0] dat_o; // data output
// Epp interface
input eppWr;
input eppRd;
input [7:0] eppAdr;
input [7:0] eppDati;
output [7:0] eppDato;
reg [7:0] eppDato;
output eppHSreq;
output eppDone;
input eppStart;
// WISHBONE Slave
input [2:0] vcti_i;
input vcyc_i;
output vack_o;
input [23:0] vadr_i;
output [15:0] vdat_o;
// WISHBONE Slave
input gr_cyc_i; // cycle valid
input gr_stb_i; // strobe
output gr_ack_o; // transfer acknowledge
input gr_we_i; // write enable
input [ 1:0] gr_sel_i; // byte select
input [31:0] gr_adr_i; // address
input [15:0] gr_dat_i; // data input
output [15:0] gr_dat_o; // data output
reg [15:0] gr_dat_o;
// WISHBONE Slave
input sp_cyc_i; // cycle valid
input sp_stb_i; // strobe
output sp_ack_o; // transfer acknowledge
input sp_we_i; // write enable
input [ 1:0] sp_sel_i; // byte select
input [31:0] sp_adr_i; // address
input [15:0] sp_dat_i; // data input
output [15:0] sp_dat_o; // data output
reg [15:0] sp_dat_o;
// WISHBONE Slave
input ar_cyc_i; // cycle valid
input ar_stb_i; // strobe
output ar_ack_o; // transfer acknowledge
input ar_we_i; // write enable
input [ 1:0] ar_sel_i; // byte select
input [43:0] ar_adr_i; // address
input [15:0] ar_dat_i; // data input
output [15:0] ar_dat_o; // data output
// WISHBONE Slave
input ap_cyc_i; // cycle valid
input ap_stb_i; // strobe
output ap_ack_o; // transfer acknowledge
input ap_we_i; // write enable
input [ 1:0] ap_sel_i; // byte select
input [43:0] ap_adr_i; // address
input [15:0] ap_dat_i; // data input
output [15:0] ap_dat_o; // data output
// RAM ports
output ram_clk;
tri ram_clk;
output ram_adv;
tri ram_adv;
output ram_cre;
tri ram_cre;
output ram_ce;
tri ram_ce;
output ram_we;
tri ram_we;
output ram_weh;
tri ram_weh;
output ram_oe;
tri ram_oe;
output ram_lb;
tri ram_lb;
output ram_ub;
tri ram_ub;
output [23:1] ram_a;
tri [23:1] ram_a;
inout [15:0] ram_d;
tri [15:0] ram_d;
output flash_ce;
tri flash_ce;
output flash_rp;
tri flash_rp;
input flash_st;
 
reg iram_cre;
reg iram_ce;
reg iram_we;
reg iram_oe;
reg iram_lb;
reg iram_ub;
reg iram_weh;
reg [23:1] iram_a;
reg [15:0] rdat;
 
reg iflash_ce;
 
assign ram_clk = gblen ? 1'b0 : 1'bz; // always low
assign ram_adv = gblen ? 1'b0 : 1'bz; // always low - asynch mode
 
reg [22:0] BCRReg;
reg [22:0] RCRReg;
 
wire pud;
reg gack;
 
reg [15:0] vdat_o;
reg [15:0] dat_o;
reg [15:0] ap_dat_o;
reg vack1_o;
reg ap_ack_o;
reg ar_ack_o;
assign vack_o = vack1_o & vcyc_i;
 
assign ram_d = (gblen && (iram_weh==1'b0)) ? rdat : {16{1'bz}};
 
wire isCPUAccess = !as & (!uds | !lds);
wire isVideoRead = vcyc_i;
wire isARWrite = ar_cyc_i && ar_stb_i && ar_we_i && (ar_adr_i[43:24]==20'h00);
wire isAPRead = ap_cyc_i && ap_stb_i && (ap_adr_i[43:24]==20'h00);
 
// Forces ack_o low immediately when cyc_i or stb_i is lost.
reg dtack1;
assign dtack = (uds & lds) | dtack1;
 
reg gack1;
assign gr_ack_o = gack1 & gr_cyc_i & gr_stb_i;
reg spack;
assign sp_ack_o = spack & sp_cyc_i & sp_stb_i;
 
reg [31:0] sadr;
reg [15:0] sdat;
reg [1:0] ssel;
reg [2:0] src;
reg [7:0] vhold;
 
reg [7:0] cnt;
wire cnt_done = cnt==8'd0;
wire flash = adr[31:24]==8'hFE;
assign iflash_rp = rst_i;
 
reg [ 5:0] state;
reg [7:0] ectl;
reg [23:0] eadr;
assign eppDone = state==EPP_NACK;
assign eppHSreq = eppAdr==8'h0E || eppAdr==8'h0F;
wire eppCycle = (eppAdr==8'h0E || eppAdr==8'h0F) && eppStart;
reg [15:0] edat,edato;
wire eword = ectl[5];
wire eppDudCycle = (!(ectl[0] ^ eadr[0])) && eword; // read odd, write even
 
assign ram_cre = gblen ? iram_cre : 1'bz;
assign ram_ce = gblen ? iram_ce : 1'bz;
assign ram_we = gblen ? iram_we : 1'bz;
assign ram_oe = gblen ? iram_oe : 1'bz;
assign ram_weh = gblen ? iram_weh : 1'bz;
assign ram_ub = gblen ? iram_ub : 1'bz;
assign ram_lb = gblen ? iram_lb : 1'bz;
assign ram_a = gblen ? iram_a : {23{1'bz}};
assign flash_ce = gblen ? iflash_ce : 1'bz;
assign flash_rp = gblen ? iflash_rp : 1'bz;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Epp register reads
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
always @(eppAdr)
case(eppAdr)
8'h08: eppDato <= ectl;
8'h09: eppDato <= eadr[ 7: 0];
8'h0A: eppDato <= eadr[15: 8];
8'h0B: eppDato <= eadr[23:16];
8'h0C: eppDato <= edato[7:0];
8'h0D: eppDato <= eadr[0] ? ram_d[15:8] : ram_d[7:0];
8'h0E: eppDato <= edato[7:0];
default: eppDato <= 8'h00; // prepare for wor
endcase
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Probably not necessary, but who knows ?
// FPGA's typically have an internal power up delay, which is likely
// greater than the RAM's.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PSRAMCtrl_PudTimer u7 (rst_i, clk_i, pud);
 
always @(posedge clk_i)
if (rst_i) begin
BCRReg <= pBCRValue;
RCRReg <= pRCRValue;
end
 
reg [15:0] radr;
 
always @(posedge clk_i)
if (rst_i) begin
iram_cre <= 1'b0;
iram_ce <= 1'b1;
iram_we <= 1'b1;
iram_weh <= 1'b1;
iram_oe <= 1'b1;
iram_lb <= 1'b1;
iram_ub <= 1'b1;
iram_a <= 23'h7FFFFF;
iflash_ce <= 1'b1;
vack1_o <= 1'b0;
ar_ack_o <= 1'b0;
ap_ack_o <= 1'b0;
dtack1 <= 1'b1;
gack1 <= 1'b0;
dat_o <= 16'hFFFF;
state <= POWER_UP;
radr <= 16'h0000;
rdat <= 32'h0000_0000;
edato <= 16'h8765;
end
else begin
 
// Downcount the RAM access timing counter
if (!cnt_done)
cnt <= cnt - 8'd1;
 
// Clear bus transfer acknowledge
if (!ar_cyc_i || !ar_stb_i)
ar_ack_o <= 1'b0;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Epp control register access
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
if (eppWr) begin
case(eppAdr)
8'h08: begin
ectl <= eppDati;
end
8'h09: eadr[7:0] <= eppDati;
8'h0A: eadr[15:8] <= eppDati;
8'h0B: eadr[23:16] <= eppDati;
8'h0C: if (eadr[0])
edat[15:8] <= eppDati;
else
edat[7:0] <= eppDati;
8'h0E,8'h0F:
begin
if (eadr[0])
edat[15:8] <= eppDati;
else
edat[7:0] <= eppDati;
end
endcase
end
 
case(state)
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Power-up
//
// Don't do anything for 150 micro-seconds.
// Then set the RAM's control registers as desired.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
POWER_UP:
if (!pud)
state <= WRITE_RCR;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Wait for a read or write access request.
// Dispatch
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDLE:
begin
cnt <= tRC; // read access time (70ns)
// Drive the RAM control signals inactive then
// override them later.
iram_ce <= 1'b1;
iram_oe <= 1'b1;
iram_we <= 1'b1;
iram_weh <= 1'b1;
iram_ub <= 1'b1;
iram_lb <= 1'b1;
iflash_ce <= 1'b1;
 
// We can only get out of the IDLE state if the global
// enable signal is active.
//
if (!gblen)
;
// Wait for flash to be ready.
else if (!flash_st)
;
 
// Page align video address
else if (isVideoRead) begin
state <= FETCH_VIDEO;
iram_ce <= 1'b0;
iram_oe <= 1'b0;
iram_ub <= 1'b0;
iram_lb <= 1'b0;
iram_a <= vadr_i[23:1];
end
/*
else if (isARWrite) begin
state <= STORE_WAIT;
ram_ce <= 1'b0;
ram_we <= 1'b0;
ram_oe <= 1'b1;
ram_ub <= 1'b0;
ram_lb <= 1'b0;
ram_a <= ar_adr_i[23:1];
rdat <= ar_dat_i;
src <= 3'd0;
end
*/
// Teh data strobes may not be active yet. They become
// active a cycle after the address strobe.
else if (!as) begin
state <= CPU_ACCESS;
if (flash)
cnt <= tRCFlash;
iram_a <= adr[23:1];
iram_ce <= !(adr[31:24]==8'h00);
iflash_ce <= !(adr[31:24]==8'hFE);
iram_oe <= !rw;
iram_we <= rw || (adr[31:24]==8'hFE);
iram_weh <= rw;
iram_ub <= uds;
iram_lb <= lds;
rdat <= dat_i;
end
else if (gr_cyc_i) begin
state <= GR_ACCESS;
iram_a <= gr_adr_i[23:1];
iram_ce <= 1'b0;
iram_oe <= gr_we_i;
iram_we <= !gr_we_i;
iram_weh <= !gr_we_i;
iram_ub <= gr_sel_i[1];
iram_lb <= gr_sel_i[0];
rdat <= gr_dat_i;
end
else if (sp_cyc_i) begin
state <= SP_ACCESS;
iram_a <= sp_adr_i[23:1];
iram_ce <= 1'b0;
iram_oe <= sp_we_i;
iram_we <= !sp_we_i;
iram_weh <= !sp_we_i;
iram_ub <= sp_sel_i[1];
iram_lb <= sp_sel_i[0];
rdat <= sp_dat_i;
end
else if (isAPRead) begin
state <= AP_FETCH;
iram_ce <= 1'b0;
iram_oe <= 1'b0;
iram_ub <= 1'b0;
iram_lb <= 1'b0;
iram_a <= ap_adr_i;
src <= 3'd2;
end
else if (eppCycle) begin
if (eppDudCycle) begin
edato[7:0] <= edato[15:8];
state <= EPP_NACK;
end
else begin
cnt <= tRC; // read (or write) access time (70ns)
iram_oe <= !ectl[0];
iram_we <= ectl[0];
iram_weh <= ectl[0];
iram_ce <= 1'b0;
iram_a <= eadr[23:1];
if (eword) begin
iram_lb <= 1'b0;
iram_ub <= 1'b0;
end
else begin
iram_lb <= eadr[0];
iram_ub <= !eadr[0];
end
rdat <= edat;
state <= ectl[0] ? EPP_FETCH : EPP_STORE;
end
end
end
 
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Memory Fetch/Store completion
// - If the address is still on the same page, use page mode timing
// - Terminate the write cycle to the RAM as soon as access time
// is met by driving ram_we high (inactive).
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CPU_ACCESS:
// Wait for a data strobe to go active (low)
if (~lds | ~uds) begin
cnt <= rw ? tRC : tWC;
state <= CPU_ACCESS1;
iram_a <= adr[23:1];
iram_ce <= 1'b0;
iram_oe <= ~rw;
iram_we <= rw || (adr[31:24]==8'hFE);
iram_weh <= rw;
iram_ub <= uds;
iram_lb <= lds;
rdat <= dat_i;
end
 
CPU_ACCESS1:
if (cnt_done) begin
iram_we <= 1'b1; // cause a rising edge on we
dat_o <= ram_d;
dtack1 <= 1'b0;
state <= CPU_NACK;
end
 
CPU_NACK:
// Wait for both data strobes to go inactive (high)
// The address strobe should also go high at this point,
// unless it's an RMW cycle.
if (uds & lds) begin
dtack1 <= 1'b1;
iram_ce <= 1'b1;
iram_oe <= 1'b1;
iram_we <= 1'b1;
iram_weh <= 1'b1;
iram_lb <= 1'b1;
iram_ub <= 1'b1;
if (as)
state <= IDLE;
// Must be a RMW (read-modify-write) cycle
// Or a longword access
// go back for another access
else
state <= CPU_ACCESS;
end
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
GR_ACCESS:
if (cnt_done) begin
iram_we <= 1'b1;
gr_dat_o <= ram_d;
gack1 <= 1'b1;
state <= GR_NACK;
end
GR_NACK:
if (!gr_cyc_i || !gr_stb_i) begin
gack1 <= 1'b0;
iram_ce <= 1'b1;
iram_oe <= 1'b1;
iram_we <= 1'b1;
iram_weh <= 1'b1;
iram_lb <= 1'b1;
iram_ub <= 1'b1;
state <= IDLE;
end
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SP_ACCESS:
if (cnt_done) begin
iram_we <= 1'b1;
sp_dat_o <= ram_d;
spack <= 1'b1;
state <= SP_NACK;
end
SP_NACK:
if (!sp_cyc_i || !sp_stb_i) begin
spack <= 1'b0;
iram_ce <= 1'b1;
iram_oe <= 1'b1;
iram_we <= 1'b1;
iram_weh <= 1'b1;
iram_lb <= 1'b1;
iram_ub <= 1'b1;
state <= IDLE;
end
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AP_FETCH:
if (cnt_done) begin
ap_dat_o <= ram_d;
ap_ack_o <= 1'b1;
state <= AP_NACK;
end
AP_NACK:
if (!ap_cyc_i || !ap_stb_i) begin
ap_ack_o <= 1'b0;
iram_ce <= 1'b1;
iram_oe <= 1'b1;
iram_we <= 1'b1;
iram_weh <= 1'b1;
iram_lb <= 1'b1;
iram_ub <= 1'b1;
state <= IDLE;
end
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Fetch video data using page mode access.
// A whole memory page of 32 bytes is fetched.
// Typically 5+30 = 35 clock cycles are required assuming a
// 60 MHz clock.
// 2+15+1 = 18 clock cycles @ 25 MHz
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FETCH_VIDEO:
if (cnt_done) begin
vack1_o <= 1'b1;
vdat_o <= ram_d;
iram_a <= iram_a + 23'd1;
if (iram_a[4:1]==4'hF)
state <= FV_NACK;
end
else
vack1_o <= 1'b0;
 
FV_NACK:
if (!vcyc_i) begin
vack1_o <= 1'b0;
iram_ce <= 1'b1;
iram_oe <= 1'b1;
iram_we <= 1'b1;
iram_weh <= 1'b1;
iram_lb <= 1'b1;
iram_ub <= 1'b1;
state <= IDLE;
end
 
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Epp access states.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
EPP_STORE:
if (cnt_done) begin
iram_we <= 1'b1;
state <= EPP_NACK;
end
EPP_FETCH:
if (cnt_done) begin
edato <= ram_d;
state <= EPP_NACK;
end
EPP_NACK:
begin
if (eppCycle==1'b0) begin
iram_ce <= 1'b1;
iram_oe <= 1'b1;
iram_we <= 1'b1;
iram_weh <= 1'b1;
iram_lb <= 1'b1;
iram_ub <= 1'b1;
state <= IDLE;
eadr <= eadr + 23'd1;
end
end
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Memory randomizer.
// - On power up memory is usually filled with zeros, as a result the
// display appears blank and one can't tell whether or not the video
// (or perhaps anything else) is actually working.
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
RANDOMIZE:
begin
state <= RANDOMIZE2;
iram_ce <= 1'b0;
iram_oe <= 1'b1;
iram_we <= 1'b0;
iram_lb <= 1'b0;
iram_ub <= 1'b0;
iram_a <= iram_a + 23'd1;
rdat <= rdat * 17'h10DCD + 32'h1;
// rdat <= 16'hE003;
// rdat <= {2{ram_a[8:6],ram_a[8:6],ram_a[8:7]}};
cnt <= tWC;
end
RANDOMIZE2:
if (cnt_done) begin
if (iram_a==23'h7F_FFFF)
state <= IDLE;
else
state <= RANDOMIZE;
iram_ce <= 1'b1;
iram_we <= 1'b1;
end
 
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Write to the RAM's control registers
// RCR: enables page mode (default setting 0010
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
WRITE_RCR:
begin
state <= WRITE_RCR_WAIT;
iram_cre <= 1'b1;
iram_ce <= 1'b0;
iram_we <= 1'b0;
iram_a <= RCRReg;
cnt <= tWC;
end
WRITE_RCR_WAIT:
if (cnt_done) begin
state <= WRITE_BCR;
iram_cre <= 1'b0;
iram_ce <= 1'b1;
iram_we <= 1'b1;
end
WRITE_BCR:
begin
state <= WRITE_BCR_WAIT;
iram_cre <= 1'b1;
iram_ce <= 1'b0;
iram_we <= 1'b0;
iram_a <= BCRReg;
cnt <= tWC;
end
WRITE_BCR_WAIT:
if (cnt_done) begin
state <= IDLE; //RANDOMIZE;
iram_cre <= 1'b0;
iram_ce <= 1'b1;
iram_we <= 1'b1;
iram_a <= 23'd0;
end
default:
state <= IDLE;
endcase
end
 
endmodule
 
/trunk/rtl/verilog/PSGEnvGenDec.v
0,0 → 1,507
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
 
PSGEnvGen.v
Version 1.1
 
ADSR envelope generator.
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
Note that this envelope generator directly uses the values for attack,
decay, sustain, and release. The original SID had to use four bit codes
and lookup tables due to register limitations. This generator is
built assuming there aren't any such register limitations.
A wrapper could be built to provide that functionality.
This component isn't really meant to be used in isolation. It is
intended to be integrated into a larger audio component (eg SID
emulator). The host component should take care of wrapping the control
signals into a register array.
 
The 'cnt' signal acts a prescaler used to determine the base frequency
used to generate envelopes. The core expects to be driven at
approximately a 1.0MHz rate for proper envelope generation. This is
accomplished using the 'cnt' signal, which should the output of a
counter used to divide the master clock frequency down to approximately
a 1MHz rate. Therefore, the master clock frequency must be at least 4MHz
for a 4 channel generator, 8MHZ for an 8 channel generator. The test
system uses a 66.667MHz master clock and 'cnt' is the output of a seven
bit counter that divides by 66.
 
Note the resource space optimization. Rather than simply build a single
channel ADSR envelope generator and instantiate it four or eight times,
This unit uses a single envelope generator and time-multiplexes the
controls from four (or eight) different channels. The ADSR is just
complex enough that it's less expensive resource wise to multiplex the
control signals. The luxury of time division multiplexing can be used
here since audio signals are low frequency. The time division multiplex
means that we need a clock that's four (or eight) times faster than
would be needed if independent ADSR's were used. This probably isn't a
problem for most cases.
 
Spartan3
Webpack 9.1i xc3s1000-4ft256
522 LUTs / 271 slices / 81.155 MHz (speed)
============================================================================ */
 
/*
sample attack values / rates
----------------------------
8 2ms
32 8ms
64 16ms
96 24ms
152 38ms
224 56ms
272 68ms
320 80ms
400 100ms
955 239ms
1998 500ms
3196 800ms
3995 1s
12784 3.2s
21174 5.3s
31960 8s
 
rate = 990.00ns x 256 x value
*/
 
 
// envelope generator states
`define ENV_IDLE 0
`define ENV_ATTACK 1
`define ENV_DECAY 2
`define ENV_SUSTAIN 3
`define ENV_RELEASE 4
 
//`define CHANNELS8
 
// Envelope generator
module PSGEnvGen(rst, clk, cnt,
gate,
attack0, attack1, attack2, attack3,
decay0, decay1, decay2, decay3,
sustain0, sustain1, sustain2, sustain3,
relese0, relese1, relese2, relese3,
`ifdef CHANNELS8
attack4, attack5, attack6, attack7,
decay4, decay5, decay6, decay7,
sustain4, sustain5, sustain6, sustain7,
relese4, relese5, relese6, relese7,
`endif
o);
parameter pChannels = 4;
parameter pPrescalerBits = 5;
input rst; // reset
input clk; // core clock
input [pPrescalerBits-1:0] cnt; // clock rate prescaler
input [3:0] attack0;
input [3:0] attack1;
input [3:0] attack2;
input [3:0] attack3;
input [3:0] decay0;
input [3:0] decay1;
input [3:0] decay2;
input [3:0] decay3;
input [3:0] sustain0;
input [3:0] sustain1;
input [3:0] sustain2;
input [3:0] sustain3;
input [3:0] relese0;
input [3:0] relese1;
input [3:0] relese2;
input [3:0] relese3;
`ifdef CHANNELS8
input [7:0] gate;
input [3:0] attack4;
input [3:0] attack5;
input [3:0] attack6;
input [3:0] attack7;
input [3:0] decay4;
input [3:0] decay5;
input [3:0] decay6;
input [3:0] decay7;
input [3:0] sustain4;
input [3:0] sustain5;
input [3:0] sustain6;
input [3:0] sustain7;
input [3:0] relese4;
input [3:0] relese5;
input [3:0] relese6;
input [3:0] relese7;
`else
input [3:0] gate;
`endif
output [7:0] o;
 
reg [7:0] sustain;
reg [15:0] attack;
reg [17:0] decay;
reg [17:0] relese;
`ifdef CHANNELS8
reg [7:0] envCtr [7:0];
reg [7:0] envCtr2 [7:0]; // for counting intervals
reg [7:0] iv[7:0]; // interval value for decay/release
reg [2:0] icnt[7:0]; // interval count
reg [19:0] envDvn [7:0];
reg [2:0] envState [7:0];
`else
reg [7:0] envCtr [3:0];
reg [7:0] envCtr2 [3:0];
reg [7:0] iv[3:0]; // interval value for decay/release
reg [2:0] icnt[3:0]; // interval count
reg [19:0] envDvn [3:0];
reg [2:0] envState [3:0];
`endif
reg [2:0] envStateNxt;
reg [15:0] envStepPeriod; // determines the length of one step of the envelope generator
reg [7:0] envCtrx;
reg [19:0] envDvnx;
 
wire [3:0] attack_x;
wire [3:0] decay_x;
wire [3:0] sustain_x;
wire [3:0] relese_x;
 
integer n;
 
// Decodes a 4-bit code into an attack value
function [15:0] AttackDecode;
input [3:0] atk;
begin
case(atk)
4'd0: AttackDecode = 16'd8;
4'd1: AttackDecode = 16'd32;
4'd2: AttackDecode = 16'd63;
4'd3: AttackDecode = 16'd95;
4'd4: AttackDecode = 16'd150;
4'd5: AttackDecode = 16'd221;
4'd6: AttackDecode = 16'd268;
4'd7: AttackDecode = 16'd316;
4'd8: AttackDecode = 16'd395;
4'd9: AttackDecode = 16'd986;
4'd10: AttackDecode = 16'd1973;
4'd11: AttackDecode = 16'd3157;
4'd12: AttackDecode = 16'd3946;
4'd13: AttackDecode = 16'd11837;
4'd14: AttackDecode = 16'd19729;
4'd15: AttackDecode = 16'd31566;
endcase
end
 
endfunction
 
// Decodes a 4-bit code into a decay/release value
function [15:0] DecayDecode;
input [3:0] dec;
begin
case(dec)
4'd0: DecayDecode = 17'd24;
4'd1: DecayDecode = 17'd95;
4'd2: DecayDecode = 17'd190;
4'd3: DecayDecode = 17'd285;
4'd4: DecayDecode = 17'd452;
4'd5: DecayDecode = 17'd665;
4'd6: DecayDecode = 17'd808;
4'd7: DecayDecode = 17'd951;
4'd8: DecayDecode = 17'd1188;
4'd9: DecayDecode = 17'd2971;
4'd10: DecayDecode = 17'd5942;
4'd11: DecayDecode = 17'd9507;
4'd12: DecayDecode = 17'd11884;
4'd13: DecayDecode = 17'd35651;
4'd14: DecayDecode = 17'd59418;
4'd15: DecayDecode = 17'd95068;
endcase
end
 
endfunction
 
`ifdef CHANNELS8
wire [2:0] sel = cnt[2:0];
 
always @(sel or
attack0 or attack1 or attack2 or attack3 or
attack4 or attack5 or attack6 or attack7)
case (sel)
0: attack_x <= attack0;
1: attack_x <= attack1;
2: attack_x <= attack2;
3: attack_x <= attack3;
4: attack_x <= attack4;
5: attack_x <= attack5;
6: attack_x <= attack6;
7: attack_x <= attack7;
endcase
 
always @(sel or
decay0 or decay1 or decay2 or decay3 or
decay4 or decay5 or decay6 or decay7)
case (sel)
0: decay_x <= decay0;
1: decay_x <= decay1;
2: decay_x <= decay2;
3: decay_x <= decay3;
4: decay_x <= decay4;
5: decay_x <= decay5;
6: decay_x <= decay6;
7: decay_x <= decay7;
endcase
 
always @(sel or
sustain0 or sustain1 or sustain2 or sustain3 or
sustain4 or sustain5 or sustain6 or sustain7)
case (sel)
0: sustain <= sustain0;
1: sustain <= sustain1;
2: sustain <= sustain2;
3: sustain <= sustain3;
4: sustain <= sustain4;
5: sustain <= sustain5;
6: sustain <= sustain6;
7: sustain <= sustain7;
endcase
 
always @(sel or
relese0 or relese1 or relese2 or relese3 or
relese4 or relese5 or relese6 or relese7)
case (sel)
0: relese <= relese0;
1: relese <= relese1;
2: relese <= relese2;
3: relese <= relese3;
4: relese <= relese4;
5: relese <= relese5;
6: relese <= relese6;
7: relese <= relese7;
endcase
 
`else
 
wire [1:0] sel = cnt[1:0];
 
mux4to1 #(4) u1 (
.e(1'b1),
.s(sel),
.i0(attack0),
.i1(attack1),
.i2(attack2),
.i3(attack3),
.z(attack_x)
);
 
mux4to1 #(12) u2 (
.e(1'b1),
.s(sel),
.i0(decay0),
.i1(decay1),
.i2(decay2),
.i3(decay3),
.z(decay_x)
);
 
mux4to1 #(8) u3 (
.e(1'b1),
.s(sel),
.i0(sustain0),
.i1(sustain1),
.i2(sustain2),
.i3(sustain3),
.z(sustain_x)
);
 
mux4to1 #(12) u4 (
.e(1'b1),
.s(sel),
.i0(relese0),
.i1(relese1),
.i2(relese2),
.i3(relese3),
.z(relese_x)
);
 
`endif
 
always @(attack_x)
attack <= AttackDecode(attack_x);
 
always @(decay_x)
decay <= DecayDecode(decay_x);
 
always @(sustain_x)
sustain <= {sustain_x,sustain_x};
 
always @(relese_x)
relese <= DecayDecode(relese_x);
 
 
always @(sel)
envCtrx <= envCtr[sel];
 
always @(sel)
envDvnx <= envDvn[sel];
 
 
// Envelope generate state machine
// Determine the next envelope state
always @(sel or gate or sustain)
begin
case (envState[sel])
`ENV_IDLE:
if (gate[sel])
envStateNxt <= `ENV_ATTACK;
else
envStateNxt <= `ENV_IDLE;
`ENV_ATTACK:
if (envCtrx==8'hFE) begin
if (sustain==8'hFF)
envStateNxt <= `ENV_SUSTAIN;
else
envStateNxt <= `ENV_DECAY;
end
else
envStateNxt <= `ENV_ATTACK;
`ENV_DECAY:
if (envCtrx==sustain)
envStateNxt <= `ENV_SUSTAIN;
else
envStateNxt <= `ENV_DECAY;
`ENV_SUSTAIN:
if (~gate[sel])
envStateNxt <= `ENV_RELEASE;
else
envStateNxt <= `ENV_SUSTAIN;
`ENV_RELEASE: begin
if (envCtrx==8'h00)
envStateNxt <= `ENV_IDLE;
else if (gate[sel])
envStateNxt <= `ENV_SUSTAIN;
else
envStateNxt <= `ENV_RELEASE;
end
// In case of hardware problem
default:
envStateNxt <= `ENV_IDLE;
endcase
end
 
always @(posedge clk)
if (rst) begin
for (n = 0; n < pChannels; n = n + 1)
envState[n] <= `ENV_IDLE;
end
else if (cnt < pChannels)
envState[sel] <= envStateNxt;
 
 
// Handle envelope counter
always @(posedge clk)
if (rst) begin
for (n = 0; n < pChannels; n = n + 1) begin
envCtr[n] <= 0;
envCtr2[n] <= 0;
icnt[n] <= 0;
iv[n] <= 0;
end
end
else if (cnt < pChannels) begin
case (envState[sel])
`ENV_IDLE:
begin
envCtr[sel] <= 0;
envCtr2[sel] <= 0;
icnt[sel] <= 0;
iv[sel] <= 0;
end
`ENV_SUSTAIN:
begin
envCtr2[sel] <= 0;
icnt[sel] <= 0;
iv[sel] <= sustain >> 3;
end
`ENV_ATTACK:
begin
icnt[sel] <= 0;
iv[sel] <= (8'hff - sustain) >> 3;
if (envDvnx==20'h0) begin
envCtr2[sel] <= 0;
envCtr[sel] <= envCtrx + 1;
end
end
`ENV_DECAY,
`ENV_RELEASE:
if (envDvnx==20'h0) begin
envCtr[sel] <= envCtrx - 1;
if (envCtr2[sel]==iv[sel]) begin
envCtr2[sel] <= 0;
if (icnt[sel] < 3'd7)
icnt[sel] <= icnt[sel] + 1;
end
else
envCtr2[sel] <= envCtr2[sel] + 1;
end
endcase
end
 
// Determine envelope divider adjustment source
always @(sel or attack or decay or relese)
begin
case(envState[sel])
`ENV_ATTACK: envStepPeriod <= attack;
`ENV_DECAY: envStepPeriod <= decay;
`ENV_RELEASE: envStepPeriod <= relese;
default: envStepPeriod <= 16'h0;
endcase
end
 
 
// double the delay at appropriate points
// for exponential modelling
wire [19:0] envStepPeriod1 = {4'b0,envStepPeriod} << icnt[sel];
 
 
// handle the clock divider
// loadable down counter
// This sets the period of each step of the envelope
always @(posedge clk)
if (rst) begin
for (n = 0; n < pChannels; n = n + 1)
envDvn[n] <= 0;
end
else if (cnt < pChannels) begin
if (envDvnx==20'h0)
envDvn[sel] <= envStepPeriod1;
else
envDvn[sel] <= envDvnx - 1;
end
 
assign o = envCtrx;
 
endmodule
 
 
/trunk/rtl/verilog/EppStartAddress.v
0,0 → 1,58
module EppStartAddress(rst, clk, wr, ad, dbi, dbo, myad, trigger, startAddress);
input rst;
input clk;
input wr;
input [7:0] ad;
input [7:0] dbi;
output [7:0] dbo;
reg [7:0] dbo;
output myad;
output trigger;
output [47:0] startAddress;
reg [47:0] startAddress;
 
reg loadedBit;
assign trigger = loadedBit;
 
always @(posedge clk)
if (rst) begin
loadedBit <= 1'b0;
startAddress <= 48'd0;
end
else begin
if (wr) begin
case (ad)
8'h80: loadedBit <= |dbi;
8'h81: startAddress[ 7: 0] <= dbi;
8'h82: startAddress[15: 8] <= dbi;
8'h83: startAddress[23:16] <= dbi;
8'h84: startAddress[31:24] <= dbi;
8'h85: startAddress[39:32] <= dbi;
8'h86: startAddress[47:40] <= dbi;
endcase
end
end
 
wire myad =
ad==8'h80 ||
ad==8'h81 ||
ad==8'h82 ||
ad==8'h83 ||
ad==8'h84 ||
ad==8'h85 ||
ad==8'h86
;
always @(ad or loadedBit or startAddress)
case (ad)
8'h80: dbo <= {8{loadedBit}};
8'h81: dbo <= startAddress[7:0];
8'h82: dbo <= startAddress[15:8];
8'h83: dbo <= startAddress[23:16];
8'h84: dbo <= startAddress[31:24];
8'h85: dbo <= startAddress[39:32];
8'h86: dbo <= startAddress[47:40];
default: dbo <= 8'h00;
endcase
 
endmodule
 
/trunk/rtl/verilog/PSGNoteGen.v
0,0 → 1,197
/* ============================================================================
(C) 2007 Robert Finch
All rights reserved.
 
PSGNoteGen.v
Version 1.1
 
This source code is available for evaluation and validation purposes
only. This copyright statement and disclaimer must remain present in
the file.
 
 
NO WARRANTY.
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
Work.
 
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
Note generator. 4/8 channels
 
Spartan3
Webpack 9.1i xc3s1000-4ft256
337 LUTs / 224 slices / 98.445 MHz
============================================================================ */
 
module PSGNoteGen(rst, clk, cnt, br, bg, bgn, ack, test,
vt0, vt1, vt2, vt3,
freq0, freq1, freq2, freq3,
pw0, pw1, pw2, pw3,
acc0, acc1, acc2, acc3,
wave, sync, ringmod, o
);
input rst;
input clk;
input [7:0] cnt;
input ack;
input [11:0] wave;
input [2:0] bgn; // bus grant number
output [3:0] br;
input [3:0] bg;
input [3:0] test;
input [4:0] vt0, vt1, vt2, vt3;
input [15:0] freq0, freq1, freq2, freq3;
input [11:0] pw0, pw1, pw2, pw3;
input [3:0] sync;
input [3:0] ringmod;
// input pxacc25;
output [23:0] acc0, acc1, acc2, acc3; // 1.023MHz / 2^ 24 = 0.06Hz resolution
output [11:0] o;
 
wire [15:0] freqx;
wire [11:0] pwx;
reg [23:0] pxacc;
reg [23:0] acc;
reg [11:0] outputT;
reg [7:0] pxacc23x;
reg [7:0] ibr;
 
integer n;
 
reg [23:0] accx [3:0];
reg [11:0] pacc [3:0];
wire [1:0] sel = cnt[1:0];
reg [11:0] outputW [3:0];
reg [22:0] lfsr [3:0];
 
assign br[0] = ibr[0] & ~bg[0];
assign br[1] = ibr[1] & ~bg[1];
assign br[2] = ibr[2] & ~bg[2];
assign br[3] = ibr[3] & ~bg[3];
 
wire [4:0] vtx;
 
always @(sel)
acc <= accx[sel];
 
 
mux4to1 #(16) u1 (.e(1'b1), .s(sel), .i0(freq0), .i1(freq1), .i2(freq2), .i3(freq3), .z(freqx) );
mux4to1 #(12) u2 (.e(1'b1), .s(sel), .i0(pw0), .i1(pw1), .i2(pw2), .i3(pw3), .z(pwx) );
mux4to1 #( 5) u3 (.e(1'b1), .s(sel), .i0(vt0), .i1(vt1), .i2(vt2), .i3(vt3), .z(vtx) );
 
 
wire [22:0] lfsrx = lfsr[sel];
wire [7:0] paccx = pacc[sel];
 
always @(sel)
pxacc <= accx[sel-1];
wire pxacc23 = pxacc[23];
 
 
// for sync'ing
always @(posedge clk)
if (cnt < 8'd4)
pxacc23x[sel] <= pxacc23;
 
wire synca = ~pxacc23x[sel]&pxacc23&sync[sel];
 
 
// detect a transition on the wavetable address
// previous address not equal to current address
wire accTran = pacc[sel]!=acc[23:12];
 
// for wave table DMA
// capture the previous address
always @(posedge clk)
if (rst) begin
for (n = 0; n < 4; n = n + 1)
pacc[n] <= 0;
end
else if (cnt < 8'd4)
pacc[sel] <= acc[23:12];
 
 
// capture wave input
// must be to who was granted the bus
always @(posedge clk)
if (rst) begin
for (n = 0; n < 8'd4; n = n + 1)
outputW[n] <= 0;
end
else if (ack)
outputW[bgn] <= wave;
 
 
// bus request control
always @(posedge clk)
if (rst) begin
ibr <= 0;
end
else if (cnt < 8'd4) begin
// check for an address transition and wave enabled
// if so, request bus
if (accTran & vtx[4])
ibr[sel] <= 1;
// otherwise
// turn off bus request for whoever it was granted
else
ibr[bgn] <= 0;
end
 
 
// Noise generator
always @(posedge clk)
if (cnt < 8'd4 && paccx[2] != acc[18])
lfsr[sel] <= {lfsrx[21:0],~(lfsrx[22]^lfsrx[17])};
 
 
// Harmonic synthesizer
always @(posedge clk)
if (rst) begin
for (n = 0; n < 4; n = n + 1)
accx[n] <= 0;
end
else if (cnt < 8'd4) begin
if (~test[sel]) begin
if (synca)
accx[sel] <= 0;
else
accx[sel] <= acc + freqx;
end
else
accx[sel] <= 0;
end
 
 
// Triangle wave, ring modulation
wire msb = ringmod[sel] ? acc[23]^pxacc23 : acc[23];
always @(acc or msb)
outputT <= msb ? ~acc[22:11] : acc[22:11];
 
// Other waveforms, ho-hum
wire [11:0] outputP = {12{acc[23:12] < pwx}};
wire [11:0] outputS = acc[23:12];
wire [11:0] outputN = lfsrx[11:0];
 
wire [11:0] out;
PSGNoteOutMux #(12) u4 (.s(vtx), .a(outputT), .b(outputS), .c(outputP), .d(outputN), .e(outputW[sel]), .o(out) );
assign o = out;
 
assign acc0 = accx[0];
assign acc1 = accx[1];
assign acc2 = accx[2];
assign acc3 = accx[3];
 
endmodule
 

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