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Rev 23 → Rev 24

/verilog/gfx_CalcAddress6.v
1,6 → 1,6
// ============================================================================
// __
// \\__/ o\ (C) 2015-2018 Robert Finch, Waterloo
// \\__/ o\ (C) 2015-2019 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
27,6 → 27,8
//
module gfx_CalcAddress6(clk, base_address_i, color_depth_i, hdisplayed_i, x_coord_i, y_coord_i,
address_o, mb_o, me_o, ce_o);
parameter SW = 128; // strip width in bits
parameter BN = SW==128 ? 6 : SW==64 ? 5 : 4;
input clk;
input [31:0] base_address_i;
input [2:0] color_depth_i;
34,9 → 36,9
input [11:0] x_coord_i;
input [11:0] y_coord_i;
output [31:0] address_o;
output [5:0] mb_o; // mask begin
output [5:0] me_o; // mask end
output [5:0] ce_o; // color bits end
output [BN:0] mb_o; // mask begin
output [BN:0] me_o; // mask end
output [BN:0] ce_o; // color bits end
 
parameter BPP4 = 3'd0;
parameter BPP8 = 3'd1;
50,14 → 52,47
// speed divide operation.
reg [15:0] coeff;
always @(color_depth_i)
case(color_depth_i)
BPP4: coeff = 4096; // 1/16 * 65536
BPP8: coeff = 8192; // 1/8 * 65536
BPP12: coeff = 13107; // 1/5 * 65536
BPP16: coeff = 16384; // 1/4 * 65536
BPP20: coeff = 21845; // 1/3 * 65536
BPP32: coeff = 32768; // 1/2 * 65536
default: coeff = 16384;
case(SW)
128:
case(color_depth_i)
BPP4: coeff = 2048; // 1/32 * 65536
BPP8: coeff = 4096; // 1/16 * 65536
BPP12: coeff = 6554; // 1/10 * 65536
BPP16: coeff = 8192; // 1/8 * 65536
BPP20: coeff = 10923; // 1/6 * 65536
BPP32: coeff = 16384; // 1/4 * 65536
default: coeff = 8192;
endcase
64:
case(color_depth_i)
BPP4: coeff = 4096; // 1/16 * 65536
BPP8: coeff = 8192; // 1/8 * 65536
BPP12: coeff = 13107; // 1/5 * 65536
BPP16: coeff = 16384; // 1/4 * 65536
BPP20: coeff = 21845; // 1/3 * 65536
BPP32: coeff = 32767; // 1/2 * 65536
default: coeff = 16384;
endcase
32:
case(color_depth_i)
BPP4: coeff = 8192; // 1/8 * 65536
BPP8: coeff = 16384; // 1/4 * 65536
BPP12: coeff = 32767; // 1/2 * 65536
BPP16: coeff = 32767; // 1/2 * 65536
BPP20: coeff = 65535; // 1/1 * 65536
BPP32: coeff = 65535; // 1/1 * 65536
default: coeff = 32767;
endcase
default: // 128
case(color_depth_i)
BPP4: coeff = 2048; // 1/32 * 65536
BPP8: coeff = 4096; // 1/16 * 65536
BPP12: coeff = 6554; // 1/10 * 65536
BPP16: coeff = 8192; // 1/8 * 65536
BPP20: coeff = 10923; // 1/6 * 65536
BPP32: coeff = 16384; // 1/4 * 65536
default: coeff = 8192;
endcase
endcase
 
// Bits per pixel minus one.
88,16 → 123,16
 
// This coefficient is the number of bits used by all pixels in the strip.
// Used to determine pixel placement in the strip.
reg [6:0] coeff2;
reg [7:0] coeff2;
always @(color_depth_i)
case(color_depth_i)
BPP4: coeff2 = 64;
BPP8: coeff2 = 64;
BPP12: coeff2 = 60;
BPP16: coeff2 = 64;
BPP20: coeff2 = 60;
BPP32: coeff2 = 64;
default: coeff2 = 64;
BPP4: coeff2 = SW;
BPP8: coeff2 = SW;
BPP12: coeff2 = SW==128 ? 120 : SW==64 ? 60 : 24;
BPP16: coeff2 = SW;
BPP20: coeff2 = SW==128 ? 120 : SW==64 ? 60 : 20;
BPP32: coeff2 = SW;
default: coeff2 = SW;
endcase
 
// Compute the fixed point horizonal strip number value. This has 16 binary
110,8 → 145,8
// horizontal strip number.
wire [15:0] strip_fract = strip_num65k[15:0]+16'h7F; // +7F to round
// Pixel beginning bit is ratio of pixel # into all bits used by pixels
wire [14:0] ndx = strip_fract[15:7] * coeff2;
assign mb_o = ndx[12:7]; // Get whole pixel position (discard fraction)
wire [15:0] ndx = strip_fract[15:7] * coeff2;
assign mb_o = ndx[15:9]; // Get whole pixel position (discard fraction)
assign me_o = mb_o + bpp; // Set high order position for mask
assign ce_o = mb_o + cbpp;
// num_strips is essentially a constant value unless the screen resolution changes.
122,7 → 157,7
num_strips65k <= hdisplayed_i * coeff;
wire [11:0] num_strips = num_strips65k[27:16];
 
wire [31:0] offset = {(({4'b0,num_strips} * y_coord_i) + strip_num),3'h0};
wire [31:0] offset = {(({4'b0,num_strips} * y_coord_i) + strip_num),SW==128 ? 4'h0 : SW==64 ? 3'h0 : 2'd0};
assign address_o = base_address_i + offset;
 
endmodule
/verilog/rtfBitmapController5.v
5,7 → 5,7
//
//
// __
// \\__/ o\ (C) 2008-2018 Robert Finch, Waterloo
// \\__/ o\ (C) 2008-2019 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
26,7 → 26,7
//
//
// The default base screen address is:
// $0200000 - the second 4MiB of RAM
// $0200000 - the third meg of RAM
//
//
// Verilog 1995
39,18 → 39,21
`define ABITS 31:0
`define HIGH 1'b1
`define LOW 1'b0
`define TRUE 1'b1
`define FALSE 1'b0
 
module rtfBitmapController5(
rst_i,
s_clk_i, s_cs_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_sel_i, s_adr_i, s_dat_i, s_dat_o, irq_o,
rst_i, irq_o,
s_clk_i, s_cs_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_sel_i, s_adr_i, s_dat_i, s_dat_o,
m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_we_o, m_sel_o, m_adr_o, m_dat_i, m_dat_o,
dot_clk_i, zrgb_o, xonoff_i
`ifdef INTERNAL_SYNC_GEN
, hsync_o, vsync_o, blank_o, border_o
, hsync_o, vsync_o, blank_o, border_o, hctr_o, vctr_o, fctr_o
`else
, hsync_i, vsync_i, blank_i
`endif
);
parameter MDW = 128; // Bus master data width
parameter BM_BASE_ADDR1 = 32'h0020_0000;
parameter BM_BASE_ADDR2 = 32'h0028_0000;
parameter REG_CTRL = 9'd0;
63,6 → 66,7
parameter REG_SYNC_ONOFF = 9'd9;
parameter REG_BLANK_ONOFF = 9'd10;
parameter REG_BORDER_ONOFF = 9'd11;
parameter REG_RASTCMP = 9'd12;
 
parameter BPP4 = 3'd0;
parameter BPP8 = 3'd1;
107,6 → 111,7
 
// SYSCON
input rst_i; // system reset
output irq_o;
 
// Peripheral IO slave port
input s_clk_i;
120,7 → 125,6
input [63:0] s_dat_i;
output [63:0] s_dat_o;
reg [63:0] s_dat_o;
output irq_o;
 
// Video Memory Master Port
// Used to read memory via burst access
128,11 → 132,11
output m_cyc_o; // video burst request
output m_stb_o;
output reg m_we_o;
output [7:0] m_sel_o;
output [MDW/8-1:0] m_sel_o;
input m_ack_i; // vid_acknowledge from memory
output [`ABITS] m_adr_o; // address for memory access
input [63:0] m_dat_i; // memory data input
output reg [63:0] m_dat_o;
input [MDW-1:0] m_dat_i; // memory data input
output reg [MDW-1:0] m_dat_o;
 
// Video
input dot_clk_i; // Video clock 80 MHz
141,6 → 145,9
output vsync_o;
output blank_o;
output border_o;
output [11:0] hctr_o;
output [11:0] vctr_o;
output [5:0] fctr_o;
`else
input hsync_i; // start/end of scan line
input vsync_i; // start/end of frame
154,25 → 161,48
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// IO registers
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg irq_o;
reg m_cyc_o;
reg [31:0] m_adr_o;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
wire cs = s_cyc_i & s_stb_i & s_cs_i;
reg ack,ack1;
wire vclk;
reg cs;
reg we;
reg [7:0] sel;
reg [11:0] adri;
reg [63:0] dat;
 
always @(posedge s_clk_i)
begin
ack1 <= cs;
ack <= ack1 & cs;
end
assign s_ack_o = cs ? (s_we_i ? 1'b1 : ack) : 1'b0;
cs <= s_cyc_i & s_stb_i & s_cs_i;
always @(posedge s_clk_i)
we <= s_we_i;
always @(posedge s_clk_i)
sel <= s_sel_i;
always @(posedge s_clk_i)
adri <= s_adr_i;
always @(posedge s_clk_i)
dat <= s_dat_i;
 
ack_gen #(
.READ_STAGES(2),
.WRITE_STAGES(0),
.REGISTER_OUTPUT(1)
) uag1
(
.clk_i(s_clk_i),
.ce_i(1'b1),
.i(cs),
.we_i(s_cyc_i & s_stb_i & s_cs_i & s_we_i),
.o(s_ack_o)
);
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
integer n;
wire vclk;
reg [11:0] hDisplayed,vDisplayed;
reg [11:0] rastcmp;
reg [`ABITS] bm_base_addr1,bm_base_addr2;
reg [2:0] color_depth;
wire [7:0] fifo_cnt;
186,7 → 216,7
reg [11:0] map; // memory access period
reg [11:0] mapctr;
reg [`ABITS] baseAddr; // base address register
wire [127:0] rgbo1;
wire [63:0] rgbo1;
reg [11:0] pixelRow;
reg [11:0] pixelCol;
wire [31:0] pal_wo;
208,6 → 238,8
reg [11:0] hBorderOn = phBorderOn, hBorderOff = phBorderOff;
reg [11:0] vBorderOn = pvBorderOn, vBorderOff = pvBorderOff;
reg sgLock;
wire pe_hsync, pe_hsync2;
wire pe_vsync;
 
`ifdef INTERNAL_SYNC_GEN
wire hsync_i, vsync_i, blank_i;
220,8 → 252,8
.eof(),
.hSync(hsync_o),
.vSync(vsync_o),
.hCtr(),
.vCtr(),
.hCtr(hctr_o),
.vCtr(vctr_o),
.blank(blank_o),
.vblank(vblank),
.vbl_int(),
257,7 → 289,31
.ee()
);
 
// Frame counter
//
VT163 #(6) ub1
(
.clk(vclk),
.clr_n(!rst_i),
.ent(pe_vsync),
.enp(1'b1),
.ld_n(1'b1),
.d(6'd0),
.q(fctr_o),
.rco()
);
 
reg rst_irq;
always @(posedge vclk)
if (rst_i)
irq_o <= `LOW;
else begin
if (hctr_o==12'd02 && rastcmp==vctr_o)
irq_o <= `HIGH;
else if (rst_irq)
irq_o <= `LOW;
end
 
always @(page or bm_base_addr1 or bm_base_addr2)
baseAddr = page ? bm_base_addr2 : bm_base_addr1;
 
266,10 → 322,10
(
.wrst(1'b0),
.wclk(s_clk_i),
.wce(cs & s_adr_i[11]),
.we(s_we_i),
.wadr({2'b0,s_adr_i[9:3]}),
.i(s_dat_i[31:0]),
.wce(cs & adri[11]),
.we(we),
.wadr({2'b0,adri[9:3]}),
.i(dat[31:0]),
.wo(pal_wo),
.rrst(1'b0),
.rclk(vclk),
293,91 → 349,100
greyscale <= 1'b0;
bm_base_addr1 <= BM_BASE_ADDR1;
bm_base_addr2 <= BM_BASE_ADDR2;
hrefdelay <= 12'd154;//12'd218;
vrefdelay <= 12'd10;//12'd27;
hrefdelay <= 12'd103;//12'd218;
vrefdelay <= 12'd13;//12'd27;
map <= 12'd0;
pcmd <= 2'b00;
rstcmd1 <= 1'b0;
rst_irq <= 1'b0;
rastcmp <= 12'hFFF;
end
else begin
rstcmd1 <= rstcmd;
rst_irq <= 1'b0;
if (rstcmd & ~rstcmd1)
pcmd <= 2'b00;
if (cs_edge) begin
if (s_we_i) begin
case(s_adr_i[11:3])
if (we) begin
casez(adri[11:3])
REG_CTRL:
begin
if (s_sel_i[0]) onoff <= s_dat_i[0];
if (s_sel_i[1]) begin
color_depth <= s_dat_i[10:8];
greyscale <= s_dat_i[11];
if (sel[0]) onoff <= dat[0];
if (sel[1]) begin
color_depth <= dat[10:8];
greyscale <= dat[11];
end
if (s_sel_i[2]) begin
hres <= s_dat_i[18:16];
vres <= s_dat_i[21:19];
if (sel[2]) begin
hres <= dat[18:16];
vres <= dat[21:19];
end
if (s_sel_i[3]) begin
page <= s_dat_i[24];
pals <= s_dat_i[25];
if (sel[3]) begin
page <= dat[24];
pals <= dat[25];
end
if (|s_sel_i[7:6]) map <= s_dat_i[59:48];
if (|sel[7:6]) map <= dat[59:48];
end
REG_DISPLAYED:
begin
if (|s_sel_i[1:0]) hDisplayed <= s_dat_i[11:0];
if (|s_sel_i[3:2]) vDisplayed <= s_dat_i[27:16];
if (|s_sel_i[5:4]) hrefdelay <= s_dat_i[43:32];
if (|s_sel_i[7:6]) vrefdelay <= s_dat_i[59:48];
if (|sel[1:0]) hDisplayed <= dat[11:0];
if (|sel[3:2]) vDisplayed <= dat[27:16];
if (|sel[5:4]) hrefdelay <= dat[43:32];
if (|sel[7:6]) vrefdelay <= dat[59:48];
end
REG_PAGE1ADDR: bm_base_addr1 <= s_dat_i;
REG_PAGE2ADDR: bm_base_addr2 <= s_dat_i;
REG_PAGE1ADDR: bm_base_addr1 <= dat;
REG_PAGE2ADDR: bm_base_addr2 <= dat;
REG_PXYZ:
begin
if (|s_sel_i[1:0]) px <= s_dat_i[11:0];
if (|s_sel_i[3:2]) py <= s_dat_i[27:16];
if (|s_sel_i[ 4]) pz <= s_dat_i[39:32];
if (|sel[1:0]) px <= dat[11:0];
if (|sel[3:2]) py <= dat[27:16];
if (|sel[ 4]) pz <= dat[39:32];
end
REG_PCOLCMD:
begin
if (s_sel_i[0]) pcmd <= s_dat_i[1:0];
if (s_sel_i[2]) raster_op <= s_dat_i[19:16];
if (|s_sel_i[7:4]) color <= s_dat_i[63:32];
if (sel[0]) pcmd <= dat[1:0];
if (sel[2]) raster_op <= dat[19:16];
if (|sel[7:4]) color <= dat[63:32];
end
REG_RASTCMP:
begin
if (sel[0]) rastcmp[7:0] <= dat[7:0];
if (sel[1]) rastcmp[11:8] <= dat[11:8];
if (sel[7]) rst_irq <= dat[63];
end
`ifdef INTERNAL_SYNC_GEN
REG_TOTAL:
begin
if (!sgLock) begin
if (|s_sel_i[1:0]) hTotal <= s_dat_i[11:0];
if (|s_sel_i[3:2]) vTotal <= s_dat_i[27:16];
if (|sel[1:0]) hTotal <= dat[11:0];
if (|sel[3:2]) vTotal <= dat[27:16];
end
if (|s_sel_i[7:4]) begin
if (s_dat_i[63:32]==32'hA1234567)
if (|sel[7:4]) begin
if (dat[63:32]==32'hA1234567)
sgLock <= 1'b0;
else if (s_dat_i[63:32]==32'h7654321A)
else if (dat[63:32]==32'h7654321A)
sgLock <= 1'b1;
end
end
REG_SYNC_ONOFF:
if (!sgLock) begin
if (|s_sel_i[1:0]) hSyncOff <= s_dat_i[11:0];
if (|s_sel_i[3:2]) hSyncOn <= s_dat_i[27:16];
if (|s_sel_i[5:4]) vSyncOff <= s_dat_i[43:32];
if (|s_sel_i[7:6]) vSyncOn <= s_dat_i[59:48];
if (|sel[1:0]) hSyncOff <= dat[11:0];
if (|sel[3:2]) hSyncOn <= dat[27:16];
if (|sel[5:4]) vSyncOff <= dat[43:32];
if (|sel[7:6]) vSyncOn <= dat[59:48];
end
REG_BLANK_ONOFF:
if (!sgLock) begin
if (|s_sel_i[1:0]) hBlankOff <= s_dat_i[11:0];
if (|s_sel_i[3:2]) hBlankOn <= s_dat_i[27:16];
if (|s_sel_i[5:4]) vBlankOff <= s_dat_i[43:32];
if (|s_sel_i[7:6]) vBlankOn <= s_dat_i[59:48];
if (|sel[1:0]) hBlankOff <= dat[11:0];
if (|sel[3:2]) hBlankOn <= dat[27:16];
if (|sel[5:4]) vBlankOff <= dat[43:32];
if (|sel[7:6]) vBlankOn <= dat[59:48];
end
REG_BORDER_ONOFF:
begin
if (|s_sel_i[1:0]) hBorderOff <= s_dat_i[11:0];
if (|s_sel_i[3:2]) hBorderOn <= s_dat_i[27:16];
if (|s_sel_i[5:4]) vBorderOff <= s_dat_i[43:32];
if (|s_sel_i[7:6]) vBorderOn <= s_dat_i[59:48];
if (|sel[1:0]) hBorderOff <= dat[11:0];
if (|sel[3:2]) hBorderOn <= dat[27:16];
if (|sel[5:4]) vBorderOff <= dat[43:32];
if (|sel[7:6]) vBorderOn <= dat[59:48];
end
`endif
default: ;
384,7 → 449,7
endcase
end
end
casez(s_adr_i[11:3])
casez(adri[11:3])
REG_CTRL:
begin
s_dat_o[0] <= onoff;
406,8 → 471,6
endcase
end
 
assign irq_o = 1'b0;
 
`ifdef USE_CLOCK_GATE
BUFHCE ucb1
(
424,8 → 487,6
// Horizontal and Vertical timing reference counters
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
wire pe_hsync, pe_hsync2;
wire pe_vsync;
edge_det edh1
(
.rst(rst_i),
504,18 → 565,47
BPP16: bpp = 15;
BPP20: bpp = 19;
BPP32: bpp = 31;
default: bpp = 15;
endcase
 
reg [5:0] shifts;
always @(color_depth)
case(color_depth)
BPP4: shifts = 6'd16;
BPP8: shifts = 6'd8;
BPP12: shifts = 6'd5;
BPP16: shifts = 6'd4;
BPP20: shifts = 6'd3;
BPP32: shifts = 6'd2;
default: shifts = 6'd4;
case(MDW)
128:
case(color_depth)
BPP4: shifts = 6'd32;
BPP8: shifts = 6'd16;
BPP12: shifts = 6'd10;
BPP16: shifts = 6'd8;
BPP20: shifts = 6'd6;
BPP32: shifts = 6'd4;
default: shifts = 6'd8;
endcase
64:
case(color_depth)
BPP4: shifts = 6'd16;
BPP8: shifts = 6'd8;
BPP12: shifts = 6'd5;
BPP16: shifts = 6'd4;
BPP20: shifts = 6'd3;
BPP32: shifts = 6'd2;
default: shifts = 6'd4;
endcase
32:
case(color_depth)
BPP4: shifts = 6'd8;
BPP8: shifts = 6'd4;
BPP12: shifts = 6'd2;
BPP16: shifts = 6'd2;
BPP20: shifts = 6'd1;
BPP32: shifts = 6'd1;
default: shifts = 6'd2;
endcase
default:
begin
$display("rtfBitmapController5: Bad master bus width");
$finish;
end
endcase
 
wire vFetch = pixelRow < vDisplayed;
524,12 → 614,13
 
wire[31:0] grAddr,xyAddr;
reg [11:0] fetchCol;
wire [5:0] mb,me,ce;
reg [63:0] mem_strip;
wire [63:0] mem_strip_o;
localparam CMS = MDW==128 ? 6 : MDW==64 ? 5 : 4;
wire [CMS:0] mb,me,ce;
reg [MDW-1:0] mem_strip;
wire [MDW-1:0] mem_strip_o;
wire [31:0] mem_color;
 
gfx_CalcAddress6 u1
gfx_CalcAddress6 #(MDW) u1
(
.clk(m_clk_i),
.base_address_i(baseAddr),
543,7 → 634,7
.ce_o()
);
 
gfx_CalcAddress6 u2
gfx_CalcAddress6 #(MDW) u2
(
.clk(m_clk_i),
.base_address_i(baseAddr),
604,7 → 695,7
do_loads <= 1'b0;
 
assign m_stb_o = m_cyc_o;
assign m_sel_o = 8'hFF;
assign m_sel_o = MDW==128 ? 16'hFFFF : MDW==64 ? 8'hFF : 4'hF;
 
reg [31:0] adr;
reg [3:0] state;
639,6 → 730,7
OPXNOR: rastop = ~(a ^ b);
OPORN: rastop = a | ~b;
OPWHITE: rastop = 1'b1;
default: rastop = 1'b0;
endcase
endfunction
 
674,7 → 766,7
else
rstcmd <= 1'b1;
IDLE:
if (load_fifo) begin
if (load_fifo & ~m_ack_i) begin
m_cyc_o <= `HIGH;
m_we_o <= `LOW;
m_adr_o <= adr;
696,7 → 788,7
if (m_ack_i) begin
wb_nack();
mem_strip <= m_dat_i;
icolor1 <= {32'b0,color} << mb;
icolor1 <= {96'b0,color} << mb;
rstcmd <= 1'b1;
if (pcmd==2'b01)
state <= ICOLOR3;
723,7 → 815,7
// Registered inline color2mem
ICOLOR2:
begin
for (n = 0; n < 64; n = n + 1)
for (n = 0; n < MDW; n = n + 1)
m_dat_o[n] <= (n >= mb && n <= me)
? ((n <= ce) ? rastop(raster_op, mem_strip[n], icolor1[n]) : icolor1[n])
: mem_strip[n];
738,7 → 830,7
ACKSTRIP:
if (m_ack_i) begin
wb_nack();
state <= pcmd == 2'b0 ? WAIT_NACK : WAITRST;
state <= pcmd == 2'b0 ? IDLE : WAITRST;
if (pcmd==2'b00)
rstcmd <= 1'b0;
end
745,7 → 837,8
WAITLOAD:
if (m_ack_i) begin
wb_nack();
state <= WAIT_NACK;
state <= IDLE;
// state <= WAIT_NACK;
end
WAIT_NACK:
if (~m_ack_i)
763,7 → 856,7
 
reg [11:0] pixelColD1;
reg [31:0] rgbo2,rgbo4;
reg [63:0] rgbo3;
reg [MDW-1:0] rgbo3;
always @(posedge vclk)
case(color_depth)
BPP4: rgbo4 <= {rgbo3[3],7'h00,21'd0,rgbo3[2:0]}; // feeds into palette
799,7 → 892,7
// than hDisplayed as the value is unsigned. That means that fifo reading is
// active only during the display area 0 to hDisplayed.
wire shift1 = hc==hres;
reg [4:0] shift_cnt;
reg [5:0] shift_cnt;
always @(posedge vclk)
if (pe_hsync)
shift_cnt <= 5'd1;
831,12 → 924,13
rgbo3 <= rgbo1;
else if (shift) begin
case(color_depth)
BPP4: rgbo3 <= {4'h0,rgbo3[63:4]};
BPP8: rgbo3 <= {8'h0,rgbo3[63:8]};
BPP12: rgbo3 <= {12'h0,rgbo3[63:12]};
BPP16: rgbo3 <= {16'h0,rgbo3[63:16]};
BPP20: rgbo3 <= {20'h0,rgbo3[63:20]};
BPP32: rgbo3 <= {32'h0,rgbo3[63:32]};
BPP4: rgbo3 <= {4'h0,rgbo3[MDW-1:4]};
BPP8: rgbo3 <= {8'h0,rgbo3[MDW-1:8]};
BPP12: rgbo3 <= {12'h0,rgbo3[MDW-1:12]};
BPP16: rgbo3 <= {16'h0,rgbo3[MDW-1:16]};
BPP20: rgbo3 <= {20'h0,rgbo3[MDW-1:20]};
BPP32: rgbo3 <= {32'h0,rgbo3[MDW-1:32]};
default: rgbo3 <= {16'h0,rgbo3[MDW-1:16]};
endcase
end
 
855,7 → 949,7
assign dat[119:108] = pixelRow[9] ? 12'hEA4 : 12'h000;
*/
 
rtfVideoFifo3 #(64) uf1
rtfVideoFifo3 #(MDW) uf1
(
.wrst(fifo_wrst),
.wclk(m_clk_i),

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