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/trunk/rtl/verilog/rtfBitmapController.v
1,11 → 1,14
`timescale 1ns / 1ps
// ============================================================================
// Bitmap Controller (416h x 262v x 8bpp):
// Bitmap Controller
// - Displays a bitmap from memory.
// - the video mode timing to be 1680x1050
//
//
// (C) 2008,2010,2011 Robert Finch
// robfinch<remove>@opencores.org
// __
// \\__/ o\ (C) 2008-2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
//
// This source file is free software: you can redistribute it and/or modify
23,217 → 26,404
//
//
// The default base screen address is:
// $20000 - the second 128 kb of RAM
// $4100000 - the second 4MiB of RAM
//
//
// Verilog 1995
// Webpack 9.2i xc3s1200-4fg320
// 64 slices / 118 LUTs / 175.009 MHz
// 72 ff's / 2 BRAM (2048x16)
//
// ============================================================================
 
module rtfBitmapController(
rst_i, clk_i, bte_o, cti_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o,
vclk, eol, eof, blank, rgbo, page
rst_i, s_clk_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_adr_i, s_dat_i, s_dat_o, irq_o,
clk_i, bte_o, cti_o, bl_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o,
vclk, hSync, vSync, blank, rgbo, xonoff
);
parameter BM_BASE_ADDR1 = 44'h000_0002_0000;
parameter BM_BASE_ADDR2 = 44'h000_0004_0000;
parameter pIOAddress = 32'hFFDC5000;
parameter BM_BASE_ADDR1 = 32'h0410_0000;
parameter BM_BASE_ADDR2 = 32'h0420_0000;
parameter REG_CTRL = 12'd0;
parameter REG_CTRL2 = 12'd1;
parameter REG_HDISPLAYED = 12'd2;
parameter REG_VDISPLAYED = 12'd3;
parameter REG_PAGE1ADDR = 12'd5;
parameter REG_PAGE2ADDR = 12'd6;
parameter REG_REFDELAY = 12'd7;
 
// SYSCON
input rst_i; // system reset
input clk_i; // system bus interface clock
 
// Peripheral slave port
input s_clk_i;
input s_cyc_i;
input s_stb_i;
output s_ack_o;
input s_we_i;
input [33:0] s_adr_i;
input [31:0] s_dat_i;
output [31:0] s_dat_o;
reg [31:0] s_dat_o;
output irq_o;
 
// Video Master Port
// Used to read memory via burst access
input clk_i; // system bus interface clock
output [1:0] bte_o;
output [2:0] cti_o;
output [5:0] bl_o;
output cyc_o; // video burst request
output stb_o;
input ack_i; // vid_acknowledge from memory
output we_o;
output [ 1:0] sel_o;
output [43:0] adr_o; // address for memory access
input [15:0] dat_i; // memory data input
output [15:0] dat_o;
output [ 3:0] sel_o;
output [33:0] adr_o; // address for memory access
input [31:0] dat_i; // memory data input
output [31:0] dat_o;
 
// Video
input vclk; // Video clock 73.529 MHz
input eol; // end of scan line
input eof; // end of frame
input vclk; // Video clock 85.71 MHz
input hSync; // start/end of scan line
input vSync; // start/end of frame
input blank; // blank the output
output [7:0] rgbo; // 8-bit RGB output
reg [7:0] rgbo;
output [23:0] rgbo; // 8-bit RGB output
reg [23:0] rgbo;
 
input page; // which page to display
input xonoff;
 
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// IO registers
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [1:0] bte_o;
reg [2:0] cti_o;
reg [5:0] bl_o;
reg sync_o;
reg cyc_o;
reg stb_o;
reg we_o;
reg [1:0] sel_o;
reg [43:0] adr_o;
reg [15:0] dat_o;
reg [3:0] sel_o;
reg [33:0] adr_o;
reg [31:0] dat_o;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
wire [11:0] hctr; // horizontal reference counter
wire [11:0] vctr; // vertical reference counter
wire [11:0] vctr1 = vctr + 12'd4;
reg [43:0] baseAddr; // base address register
wire [7:0] rgbo1;
wire cs = s_cyc_i && s_stb_i && (s_adr_i[33:14]==pIOAddress[31:12]);
reg ack,ack1;
always @(posedge clk_i)
begin
ack1 <= cs;
ack <= ack1 & cs;
end
assign s_ack_o = cs ? (s_we_i ? 1'b1 : ack) : 1'b0;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [11:0] hDisplayed,vDisplayed;
reg [33:0] bm_base_addr1,bm_base_addr2;
reg [1:0] color_depth;
wire [8:0] fifo_cnt;
reg onoff;
reg [5:0] Bpp; // bits per pixel, 8,16, or 32
reg [1:0] hres,vres;
reg page;
reg [11:0] hrefdelay;
reg [11:0] vrefdelay;
reg [11:0] hctr; // horizontal reference counter
wire [11:0] hctr1 = hctr - hrefdelay;
reg [11:0] vctr; // vertical reference counter
wire [11:0] vctr1 = vctr - vrefdelay;
reg [33:0] baseAddr; // base address register
wire [31:0] rgbo1;
reg [11:0] pixelRow;
reg [11:0] pixelCol;
wire [31:0] pal_wo;
wire [31:0] pal_o;
 
always @(page)
baseAddr = page ? BM_BASE_ADDR2 : BM_BASE_ADDR1;
always @(page or bm_base_addr1 or bm_base_addr2)
baseAddr = page ? bm_base_addr2 : bm_base_addr1;
 
syncRam512x32_1rw1r upal1
(
.wrst(1'b0),
.wclk(s_clk_i),
.wce(cs & s_adr_i[13]),
.we(s_we_i),
.wadr(s_adr_i[10:2]),
.i(s_dat_i),
.wo(pal_wo),
.rrst(1'b0),
.rclk(vclk),
.rce(1'b1),
.radr({1'b0,rgbo4[7:0]}),
.o(pal_o)
);
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
always @(posedge s_clk_i)
if (rst_i) begin
page <= 1'b0;
hres <= 2'b11;
vres <= 2'b11;
hDisplayed <= 12'd340;
vDisplayed <= 12'd192;
onoff <= 1'b1;
color_depth <= 2'b00;
bm_base_addr1 <= {BM_BASE_ADDR1,2'b00};
bm_base_addr2 <= {BM_BASE_ADDR2,2'b00};
hrefdelay <= 12'd218;
vrefdelay <= 12'd27;
end
else begin
if (cs) begin
if (s_we_i) begin
casex(s_adr_i[13:2])
REG_CTRL:
begin
onoff <= s_dat_i[0];
color_depth <= s_dat_i[10:9];
hres <= s_dat_i[17:16];
vres <= s_dat_i[19:18];
end
REG_CTRL2:
begin
page <= s_dat_i[16];
end
REG_HDISPLAYED: hDisplayed <= s_dat_i[11:0];
REG_VDISPLAYED: vDisplayed <= s_dat_i[11:0];
REG_PAGE1ADDR: bm_base_addr1 <= {s_dat_i,2'b00};
REG_PAGE2ADDR: bm_base_addr2 <= {s_dat_i,2'b00};
REG_REFDELAY:
begin
hrefdelay <= s_dat_i[11:0];
vrefdelay <= s_dat_i[27:16];
end
endcase
end
casex(s_adr_i[13:2])
REG_CTRL:
begin
s_dat_o[0] <= onoff;
s_dat_o[10:9] <= color_depth;
s_dat_o[17:16] <= hres;
s_dat_o[19:18] <= vres;
end
REG_CTRL2:
begin
s_dat_o[16] <= page;
end
REG_HDISPLAYED: s_dat_o <= hDisplayed;
REG_VDISPLAYED: s_dat_o <= vDisplayed;
REG_PAGE1ADDR: s_dat_o <= bm_base_addr1;
REG_PAGE2ADDR: s_dat_o <= bm_base_addr2;
REG_REFDELAY: s_dat_o <= {vrefdelay,4'h0,hrefdelay};
12'b100x_xxxx_xxxx: s_dat_o <= pal_wo;
endcase
end
else
s_dat_o <= 32'd0;
end
 
assign irq_o = 1'b0;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Horizontal and Vertical timing reference counters
// - The memory fetch address is determined from these counters.
// - The counters are setup with negative values so that the zero
// point coincides with the top left of the display.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
wire hSyncEdge, vSyncEdge;
edge_det ed0(.rst(rst_i), .clk(vclk), .ce(1'b1), .i(hSync), .pe(hSyncEdge), .ne(), .ee() );
edge_det ed1(.rst(rst_i), .clk(vclk), .ce(1'b1), .i(vSync), .pe(vSyncEdge), .ne(), .ee() );
 
counter #(12) u1 (.rst(1'b0), .clk(vclk), .ce(1'b1), .ld(eol), .d(12'hEE4), .q(hctr));
counter #(12) u2 (.rst(1'b0), .clk(vclk), .ce(eol), .ld(eof), .d(12'hFDC), .q(vctr));
always @(posedge vclk)
if (rst_i) hctr <= 1;
else if (hSyncEdge) hctr <= 1;
else hctr <= hctr + 1;
 
always @(posedge vclk)
if (rst_i) vctr <= 1;
else if (vSyncEdge) vctr <= 1;
else if (hSyncEdge) vctr <= vctr + 1;
 
 
// Pixel row and column are derived from the horizontal and vertical counts.
 
always @(vctr1)
pixelRow = vctr1[11:2];
always @(hctr)
pixelCol = hctr[11:1];
case(vres)
2'b00: pixelRow <= vctr1[11:0];
2'b01: pixelRow <= vctr1[11:1];
2'b10: pixelRow <= vctr1[11:2];
default: pixelRow <= vctr1[11:2];
endcase
always @(hctr1)
case(hres)
2'b00: pixelCol = hctr1[11:0];
2'b01: pixelCol = hctr1[11:1];
2'b10: pixelCol = hctr1[11:2];
default: pixelCol = hctr1[11:2];
endcase
wire vFetch = vctr1 < vDisplayed;
wire fifo_rst = hctr[11:4]==8'h00;
 
wire vFetch = (vctr < 12'd1050) || (vctr > 12'hFF8);
wire[23:0] rowOffset = pixelRow * hDisplayed;
reg [11:0] fetchCol;
 
// Video Request Block
// 416x262
// - Issue a request for access to memory every 160 clock cycles
// - Reset the request flag once an access has been initiated.
// - 128 bytes (pixels) are read per scan line
// - It takes about 18 clock cycles @ 25 MHz to access 32 bytes of data
// through the memory contoller, or about 53 video clocks
// 83 video clocks with a 16 MHZ memory controller.
 
reg [2:0] vreq;
 
// Must be vclk. vid_req will be active for numerous clock cycles as
// a burst type fetch is used. The ftch and vFetch may only be
// active for a single video clock cycle. vclk must be used so these
// signals are not missed due to a clock domain crossing. We luck
// out here because of the length of time vid_req is active.
//
always @(posedge vclk)
begin
if (vFetch) begin
if (vctr1[1:0]!=2'd3) begin // we only need 13 memory accesses
if (hctr==12'd16) vreq <= 3'b100;
if (hctr==12'd176) vreq <= 3'b101;
if (hctr==12'd336) vreq <= 3'b110;
if (hctr==12'd496) vreq <= 3'b111;
end
else
if (hctr==12'd16) vreq <= 3'b100;
end
if (cyc_o) vreq <= 3'b000;
end
// Cross the clock domain with the request signal
reg do_cyc;
always @(posedge clk_i)
do_cyc <= vreq[2];
 
wire[19:0] rowOffset = pixelRow * 10'd416;
reg [8:0] fetchCol;
 
// - read from assigned video memory address, using burst mode reads
// - 32 pixels at a time are read
// - 64 pixels at a time are read
// - video data is fetched one pixel row in advance
//
reg [3:0] bcnt;
reg [5:0] bcnt;
wire [5:0] bcnt_inc = bcnt + 6'd1;
reg [33:0] adr;
always @(posedge clk_i)
if (rst_i) begin
bte_o <= 2'b00; // linear burst
cti_o <= 3'b000; // classic cycle
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 2'b00;
we_o <= 1'b0;
adr_o <= 44'h000_0000_0000;
dat_o <= 16'h0000;
fetchCol <= 9'd0;
bcnt <= 4'd0;
wb_nack();
fetchCol <= 12'd0;
bcnt <= 6'd0;
end
else begin
if (do_cyc & !cyc_o) begin
cti_o <= 3'b010; // incrementing burst cycle
if (fifo_rst) begin
fetchCol <= 12'd0;
adr <= baseAddr + rowOffset;
end
else if (fifo_cnt < 9'd500 && vFetch && onoff && xonoff && fetchCol < hDisplayed && !cyc_o) begin
cti_o <= 3'b001; // constant address burst
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 2'b11;
bcnt <= 4'd0;
fetchCol <= {vctr1[1:0],vreq[1:0],5'h00};
// This works out to be an even multiple of 32 bytes
adr_o <= baseAddr + rowOffset + 10'd416 + {vctr1[1:0],vreq[1:0],5'h00};
sel_o <= 4'b1111;
bcnt <= 6'd0;
bl_o <= 6'd7;
adr_o <= adr;
end
if (cyc_o & ack_i) begin
adr_o <= adr_o + 32'd2;
fetchCol <= fetchCol + 9'd2;
bcnt <= bcnt + 4'd1;
if (bcnt==4'd14)
case(color_depth)
2'b00: fetchCol <= fetchCol + 12'd4;
2'b01: fetchCol <= fetchCol + 12'd2;
2'b11: fetchCol <= fetchCol + 12'd1;
default: fetchCol <= 12'hFF0;
endcase
bcnt <= bcnt_inc;
if (bl_o==bcnt_inc)
cti_o <= 3'b111; // end of burst
if (bcnt==4'd15) begin
cti_o <= 3'b000; // classic cycles again
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 2'b00;
adr_o <= 44'h000_0000_0000;
else if (bl_o==bcnt) begin
wb_nack();
adr <= adr + 34'd32;
end
end
end
 
task wb_nack;
begin
bte_o <= 2'b00; // linear burst
cti_o <= 3'b000; // classic cycle
bl_o <= 6'd0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
sel_o <= 4'b0000;
we_o <= 1'b0;
adr_o <= 34'h0000_0000;
dat_o <= 32'h0000_0000;
end
endtask
 
reg [11:0] pixelColD1;
reg [31:0] rgbo2,rgbo3,rgbo4;
always @(posedge vclk)
rgbo <= rgbo1;
if (color_depth==2'b00)
rgbo4 <= rgbo2;
else if (color_depth==2'b01)
rgbo4 <= {rgbo3[14:10],3'b0,rgbo3[9:5],3'b0,rgbo3[4:0],3'b0};
else
rgbo4 <= rgbo1;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Video Line Buffer
// - gets written in bursts, but read continuously
// - buffer is used as two halves - one half is displayed (read) while
// the other is fetched (write).
// - only the lower eleven bits of the address are used as an index,
// these bits will match with the addresses generated by the burst
// controller above.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
// Storage for 2048x8 bit pixels (2048x8 data)
reg rd_fifo,rd_fifo1,rd_fifo2;
reg de;
always @(posedge vclk)
if (rd_fifo1)
de <= ~blank;
 
RAMB16_S9_S18 ram0
always @(posedge vclk)
if (onoff & xonoff & de) begin
if (color_depth==2'b00)
rgbo <= pal_o;
else
rgbo <= rgbo4;
end
else
rgbo <= 24'd0;
 
wire vrd;
always @(posedge vclk) pixelColD1 <= pixelCol;
always @(posedge vclk)
if (pixelCol < hDisplayed + 12'd8)
case({color_depth,hres})
4'b0000: rd_fifo1 <= hctr[1:0]==2'b00; // 4 clocks
4'b0001: rd_fifo1 <= hctr[2:0]==3'b000; // 8 clocks
4'b0010: rd_fifo1 <= hctr[3:0]==4'b0000; // 16 clocks
4'b0011: rd_fifo1 <= hctr[3:0]==4'b0000; // unsupported
4'b0100: rd_fifo1 <= hctr[0]==1'b0; // 2 clocks
4'b0101: rd_fifo1 <= hctr[1:0]==2'b00; // 4 clocks
4'b0110: rd_fifo1 <= hctr[2:0]==3'b000; // 8 clocks (twice as often as a byte)
4'b0111: rd_fifo1 <= hctr[2:0]==3'b000;
4'b1000: rd_fifo1 <= 1'b0;
4'b1001: rd_fifo1 <= 1'b0;
4'b1010: rd_fifo1 <= 1'b0;
4'b1011: rd_fifo1 <= 1'b0;
4'b1100: rd_fifo1 <= 1'b1;
4'b1101: rd_fifo1 <= hctr[0]==1'b0;
4'b1110: rd_fifo1 <= hctr[1:0]==2'b00;
4'b1111: rd_fifo1 <= hctr[1:0]==2'b00;
endcase
reg shift,shift1,shift2;
always @(posedge vclk)
if (pixelCol < hDisplayed + 12'd8)
case({color_depth,hres})
// shift four times as often as a load
4'b0000: shift1 <= 1'b1;
4'b0001: shift1 <= hctr[0]==1'b0;
4'b0010: shift1 <= hctr[1:0]==2'b00;
4'b0011: shift1 <= hctr[1:0]==2'b00;
// shift twice as often as a load
4'b0100: shift1 <= 1'b1;
4'b0101: shift1 <= hctr[0]==1'b0;
4'b0110: shift1 <= hctr[1:0]==2'b00;
4'b0111: shift1 <= hctr[1:0]==2'b00;
// unsupported color depth
4'b1000: shift1 <= 1'b0;
4'b1001: shift1 <= 1'b0;
4'b1010: shift1 <= 1'b0;
4'b1011: shift1 <= 1'b0;
// nothing to shift (all loads)
4'b1100: shift1 <= 1'b0;
4'b1101: shift1 <= 1'b0;
4'b1110: shift1 <= 1'b0;
4'b1111: shift1 <= 1'b0;
endcase
always @(posedge vclk) shift2 <= shift1;
always @(posedge vclk) shift <= shift2;
always @(posedge vclk) rd_fifo2 <= rd_fifo1;
always @(posedge vclk) rd_fifo <= rd_fifo2;
always @(posedge vclk)
if (rd_fifo)
rgbo2 <= rgbo1;
else if (shift)
rgbo2 <= {8'h00,rgbo2[31:8]};
always @(posedge vclk)
if (rd_fifo)
rgbo3 <= rgbo1;
else if (shift)
rgbo3 <= {16'h0000,rgbo3[31:16]};
 
rtfVideoFifo uf1
(
.CLKA(vclk),
.ADDRA({pixelRow[0],pixelCol[8:1],~pixelCol[0]}), // <- pixelCol[0] nonsense, we need the highest pixel first
.DIA(8'hFF),
.DIPA(1'b1),
.DOA(rgbo1),
.ENA(1'b1),
.WEA(1'b0),
.SSRA(blank),
 
.CLKB(clk_i),
.ADDRB({~pixelRow[0],fetchCol[8:1]}),
.DIB(dat_i),
.DIPB(2'b11),
.DOB(),
.ENB(cyc_o),
.WEB(ack_i),
.SSRB(1'b0)
.rst(fifo_rst),
.wclk(clk_i),
.wr(cyc_o & ack_i),
.di(dat_i),
.rclk(vclk),
.rd(rd_fifo),
.do(rgbo1),
.cnt(fifo_cnt)
);
 
endmodule
 
/trunk/rtl/verilog/rtfVideoFifo.v
0,0 → 1,64
`timescale 1ns / 1ps
// ============================================================================
// (C) 2008-2013 Robert Finch
// robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// Verilog 1995
//
// ============================================================================
//
module rtfVideoFifo(rst, wclk, wr, di, rclk, rd, do, cnt);
input rst;
input wclk;
input wr;
input [31:0] di;
input rclk;
input rd;
output [31:0] do;
output [8:0] cnt;
reg [8:0] cnt;
 
reg [8:0] wr_ptr;
reg [8:0] rd_ptr,rrd_ptr;
reg [31:0] mem [0:511];
 
always @(posedge wclk)
if (rst)
wr_ptr <= 9'd0;
else if (wr) begin
mem[wr_ptr] <= di;
wr_ptr <= wr_ptr + 9'd1;
end
 
always @(posedge rclk)
if (rst)
rd_ptr <= 9'd0;
else if (rd)
rd_ptr <= rd_ptr + 9'd1;
always @(posedge rclk)
rrd_ptr <= rd_ptr;
 
assign do = mem[rrd_ptr];
 
always @(wr_ptr or rd_ptr)
if (rd_ptr > wr_ptr)
cnt <= wr_ptr + (10'd512 - rd_ptr);
else
cnt <= wr_ptr - rd_ptr;
 
endmodule

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