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Rev 3 → Rev 4

/VHDL/SELF_TEST/RV01_selftest_syn.vhd
0,0 → 1,80
-----------------------------------------------------------------
-- --
-----------------------------------------------------------------
-- --
-- Copyright (C) 2016 Stefano Tonello --
-- --
-- This source file may be used and distributed without --
-- restriction provided that this copyright statement is not --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
-- --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
-- POSSIBILITY OF SUCH DAMAGE. --
-- --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 self-test module
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
 
entity RV01_SELFTEST_SYN is
port(
CLK_100M_i : in std_logic;
RSTN_i : in std_logic;
 
TIE_LOW_o : out std_logic;
TIE_HIGH_o : out std_logic;
DONE_o : out std_logic;
PASS_o : out std_logic
);
end RV01_SELFTEST_SYN;
 
architecture ARC of RV01_SELFTEST_SYN is
 
component RV01_SELFTEST is
port(
CLK_i : in std_logic;
RST_i : in std_logic;
 
DONE_o : out std_logic;
PASS_o : out std_logic
);
end component;
 
signal RST : std_logic;
 
begin
 
RST <= not(RSTN_i);
 
U_SYN: RV01_SELFTEST
port map(
CLK_i => CLK_100M_i,
RST_i => RST,
 
DONE_o => DONE_o,
PASS_o => PASS_o
);
 
TIE_LOW_o <= '0';
 
TIE_HIGH_o <= '1';
 
end ARC;
/VHDL/RV01_cpu_2w_p6.vhd
719,29 → 719,7
RES_o : out SDWORD_T -- result
);
end component;
component RV01_PIPE_A_RMX_X2 is
generic(
NW : natural := 2
);
port(
OPA_V_i : in std_logic;
OPB_V_i : in std_logic;
OPA_i : in SDWORD_T;
OPB_i : in SDWORD_T;
INSTR_i : in DEC_INSTR_T;
IX3_V_i : in std_logic_vector(NW-1 downto 0);
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
IX3_RES0_i : in SDWORD_T;
IX3_RES1_i : in SDWORD_T;
 
OPA_V_o : out std_logic;
OPB_V_o : out std_logic;
OPA_o : out SDWORD_T;
OPB_o : out SDWORD_T
);
end component;
component RV01_PSTLLOG_2W_P6 is
generic(
DXE : std_logic := '1';
/VHDL/RV01_pipe_a.vhd
208,286 → 208,3
RES_o <= RES;
 
end ARC;
 
---------------------------------------------------------------
-- A-pipeline result mux (IX2 stage)
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library WORK;
use WORK.RV01_CONSTS_PKG.all;
use WORK.RV01_TYPES_PKG.all;
use WORK.RV01_FUNCS_PKG.all;
use work.RV01_IDEC_PKG.all;
 
entity RV01_PIPE_A_RMX_X2 is
generic(
NW : natural := 2
);
port(
OPA_V_i : in std_logic;
OPB_V_i : in std_logic;
OPA_i : in SDWORD_T;
OPB_i : in SDWORD_T;
INSTR_i : in DEC_INSTR_T;
IX3_V_i : in std_logic_vector(NW-1 downto 0);
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
IX3_RES0_i : in SDWORD_T;
IX3_RES1_i : in SDWORD_T;
 
OPA_V_o : out std_logic;
OPB_V_o : out std_logic;
OPA_o : out SDWORD_T;
OPB_o : out SDWORD_T
);
end RV01_PIPE_A_RMX_X2;
 
architecture ARC of RV01_PIPE_A_RMX_X2 is
 
signal SELA1,SELB1 : std_logic;
signal UOPA,UOPB : SDWORD_T;
signal UOPA_V,UOPB_V : std_logic;
 
begin
 
------------------------------------
-- Notes
------------------------------------
 
-- Stage IX3 provides (up to) two results per cycle,
-- requiring a mux to select the desired one.
 
-- OPA source selection flag
SELA1 <= IX3_V_i(1) when (
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS1
) else '0';
 
-- Updated OPA operand source mux
UOPA <= IX3_RES1_i when (SELA1 = '1') else IX3_RES0_i;
 
-- Updated OPA operand valid flag (flag is set if there's
-- a valid value for it from IX3 stage).
 
UOPA_V <= '1' when (
(
IX3_V_i(0) = '1' and
IX3_INSTR_i(0).WRD = '1' and
IX3_INSTR_i(0).RD = INSTR_i.RS1
) or (
IX3_V_i(1) = '1' and
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS1
)
) else '0';
 
-- OPB source selection flag
SELB1 <= IX3_V_i(1) when (
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS2
) else '0';
 
-- Updated OPB operand source mux
UOPB <= IX3_RES1_i when (SELB1 = '1') else IX3_RES0_i;
-- Updated OPB operand valid flag (flag is set if there's
-- a valid value for it from IX3 stage).
 
UOPB_V <= '1' when (
(
IX3_V_i(0) = '1' and
IX3_INSTR_i(0).WRD = '1' and
IX3_INSTR_i(0).RD = INSTR_i.RS2
) or (
IX3_V_i(1) = '1' and
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS2
)
) else '0';
OPA_V_o <= OPA_V_i or UOPA_V;
OPB_V_o <= OPB_V_i or UOPB_V;
OPA_o <= OPA_i when (OPA_V_i = '1') else UOPA;
 
OPB_o <= OPB_i when (OPB_V_i = '1') else UOPB;
end ARC;
 
---------------------------------------------------------------
-- A-pipeline result mux (IX1 stage)
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library WORK;
use WORK.RV01_CONSTS_PKG.all;
use WORK.RV01_TYPES_PKG.all;
use WORK.RV01_FUNCS_PKG.all;
use work.RV01_IDEC_PKG.all;
 
entity RV01_PIPE_A_RMX_X1 is
generic(
NW : natural := 2
);
port(
OPA_V_i : in std_logic;
OPB_V_i : in std_logic;
OPA_i : in SDWORD_T;
OPB_i : in SDWORD_T;
INSTR_i : in DEC_INSTR_T;
IX2_V_i : in std_logic_vector(NW-1 downto 0);
IX2_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
IX2_RES0_i : in SDWORD_T;
IX2_RES1_i : in SDWORD_T;
IX3_V_i : in std_logic_vector(NW-1 downto 0);
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
IX3_RES0_i : in SDWORD_T;
IX3_RES1_i : in SDWORD_T;
 
OPA_V_o : out std_logic;
OPB_V_o : out std_logic;
OPA_o : out SDWORD_T;
OPB_o : out SDWORD_T
);
end RV01_PIPE_A_RMX_X1;
 
architecture ARC of RV01_PIPE_A_RMX_X1 is
 
signal SELA0_X2,SELB0_X2 : std_logic;
signal SELA0_X3,SELB0_X3 : std_logic;
signal SELA1_X2,SELB1_X2 : std_logic;
signal SELA1_X3,SELB1_X3 : std_logic;
signal UOPA,UOPB : SDWORD_T;
signal UOPA_V,UOPB_V : std_logic;
 
begin
 
------------------------------------
-- Notes
------------------------------------
 
-- Stages IX2 and IX3 provide (up to) two results per
-- cycle, each, requiring a mux to select the desired one.
 
-- OPA source selection flag
 
SELA0_X2 <= IX2_V_i(0) when (
IX2_INSTR_i(0).WRD = '1' and
IX2_INSTR_i(0).RD = INSTR_i.RS1
) else '0';
 
SELA1_X2 <= IX2_V_i(1) when (
IX2_INSTR_i(1).WRD = '1' and
IX2_INSTR_i(1).RD = INSTR_i.RS1
) else '0';
 
SELA0_X3 <= IX3_V_i(0) when (
IX3_INSTR_i(0).WRD = '1' and
IX3_INSTR_i(0).RD = INSTR_i.RS1
) else '0';
 
SELA1_X3 <= IX3_V_i(1) when (
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS1
) else '0';
 
-- Updated OPA operand source mux
process(
SELA0_X2,SELA1_X2,SELA0_X3,SELA1_X3,
IX2_RES0_i,IX2_RES1_i,IX3_RES0_i,IX3_RES1_i
)
variable S : std_logic_vector(4-1 downto 0);
begin
S := SELA1_X3 & SELA0_X3 & SELA1_X2 & SELA0_X2;
case S is
when "0001"|"0101"|"1001"|"1101" =>
UOPA <= IX2_RES0_i;
when "0010"|"0011"|"0110"|"0111"|"1010"|"1011"|"1110"|"1111" =>
UOPA <= IX2_RES1_i;
when "0100" =>
UOPA <= IX3_RES0_i;
when others =>
UOPA <= IX3_RES1_i;
end case;
end process;
 
-- Updated OPA operand valid flag (flag is set if there's
-- a valid value for it from IX2 or IX3 stage).
 
UOPA_V <=
SELA0_X2 or
SELA1_X2 or
SELA0_X3 or
SELA1_X3;
 
-- OPB source selection flag
 
SELB0_X2 <= IX2_V_i(0) when (
IX2_INSTR_i(0).WRD = '1' and
IX2_INSTR_i(0).RD = INSTR_i.RS2
) else '0';
 
-- OPA source selection flag
SELB1_X2 <= IX2_V_i(1) when (
IX2_INSTR_i(1).WRD = '1' and
IX2_INSTR_i(1).RD = INSTR_i.RS2
) else '0';
 
-- OPA source selection flag
SELB0_X3 <= IX3_V_i(0) when (
IX3_INSTR_i(0).WRD = '1' and
IX3_INSTR_i(0).RD = INSTR_i.RS2
) else '0';
 
SELB1_X3 <= IX3_V_i(1) when (
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS2
) else '0';
 
-- Updated OPB operand source mux
process(
SELB0_X2,SELB1_X2,SELB0_X3,SELB1_X3,
IX2_RES0_i,IX2_RES1_i,IX3_RES0_i,IX3_RES1_i
)
variable S : std_logic_vector(4-1 downto 0);
begin
S := SELB1_X3 & SELB0_X3 & SELB1_X2 & SELB0_X2;
case S is
when "0001"|"0101"|"1001"|"1101" =>
UOPB <= IX2_RES0_i;
when "0010"|"0011"|"0110"|"0111"|"1010"|"1011"|"1110"|"1111" =>
UOPB <= IX2_RES1_i;
when "0100" =>
UOPB <= IX3_RES0_i;
when others =>
UOPB <= IX3_RES1_i;
end case;
end process;
-- Updated OPB operand valid flag (flag is set if there's
-- a valid value for it from IX2 or IX3 stages).
 
UOPB_V <=
SELB0_X2 or
SELB1_X2 or
SELB0_X3 or
SELB1_X3;
OPA_V_o <= OPA_V_i or UOPA_V;
OPB_V_o <= OPB_V_i or UOPB_V;
OPA_o <= OPA_i when (OPA_V_i = '1') else UOPA;
 
OPB_o <= OPB_i when (OPB_V_i = '1') else UOPB;
end ARC;
/VHDL/RV01_pipe_a_rmx_x2.vhd
0,0 → 1,136
-----------------------------------------------------------------
-- --
-----------------------------------------------------------------
-- --
-- Copyright (C) 2017 Stefano Tonello --
-- --
-- This source file may be used and distributed without --
-- restriction provided that this copyright statement is not --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
-- --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
-- BUSINESS REQERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
-- POSSIBILITY OF SUCH DAMAGE. --
-- --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- A-pipeline result mux (IX2 stage)
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library WORK;
use WORK.RV01_CONSTS_PKG.all;
use WORK.RV01_TYPES_PKG.all;
use WORK.RV01_FUNCS_PKG.all;
use work.RV01_IDEC_PKG.all;
 
entity RV01_PIPE_A_RMX_X2 is
generic(
NW : natural := 2
);
port(
OPA_V_i : in std_logic;
OPB_V_i : in std_logic;
OPA_i : in SDWORD_T;
OPB_i : in SDWORD_T;
INSTR_i : in DEC_INSTR_T;
IX3_V_i : in std_logic_vector(NW-1 downto 0);
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
IX3_RES0_i : in SDWORD_T;
IX3_RES1_i : in SDWORD_T;
 
OPA_V_o : out std_logic;
OPB_V_o : out std_logic;
OPA_o : out SDWORD_T;
OPB_o : out SDWORD_T
);
end RV01_PIPE_A_RMX_X2;
 
architecture ARC of RV01_PIPE_A_RMX_X2 is
 
signal SELA1,SELB1 : std_logic;
signal UOPA,UOPB : SDWORD_T;
signal UOPA_V,UOPB_V : std_logic;
 
begin
 
------------------------------------
-- Notes
------------------------------------
 
-- Stage IX3 provides (up to) two results per cycle,
-- requiring a mux to select the desired one.
 
-- OPA source selection flag
SELA1 <= IX3_V_i(1) when (
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS1
) else '0';
 
-- Updated OPA operand source mux
UOPA <= IX3_RES1_i when (SELA1 = '1') else IX3_RES0_i;
 
-- Updated OPA operand valid flag (flag is set if there's
-- a valid value for it from IX3 stage).
 
UOPA_V <= '1' when (
(
IX3_V_i(0) = '1' and
IX3_INSTR_i(0).WRD = '1' and
IX3_INSTR_i(0).RD = INSTR_i.RS1
) or (
IX3_V_i(1) = '1' and
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS1
)
) else '0';
 
-- OPB source selection flag
SELB1 <= IX3_V_i(1) when (
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS2
) else '0';
 
-- Updated OPB operand source mux
UOPB <= IX3_RES1_i when (SELB1 = '1') else IX3_RES0_i;
-- Updated OPB operand valid flag (flag is set if there's
-- a valid value for it from IX3 stage).
 
UOPB_V <= '1' when (
(
IX3_V_i(0) = '1' and
IX3_INSTR_i(0).WRD = '1' and
IX3_INSTR_i(0).RD = INSTR_i.RS2
) or (
IX3_V_i(1) = '1' and
IX3_INSTR_i(1).WRD = '1' and
IX3_INSTR_i(1).RD = INSTR_i.RS2
)
) else '0';
OPA_V_o <= OPA_V_i or UOPA_V;
OPB_V_o <= OPB_V_i or UOPB_V;
OPA_o <= OPA_i when (OPA_V_i = '1') else UOPA;
 
OPB_o <= OPB_i when (OPB_V_i = '1') else UOPB;
end ARC;

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