URL
https://opencores.org/ocsvn/s1_core/s1_core/trunk
Subversion Repositories s1_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/s1_core/trunk/docs
- from Rev 105 to Rev 111
- ↔ Reverse comparison
Rev 105 → Rev 111
/REQUIREMENTS.txt
9,7 → 9,8
- sed stream editor; |
- for simulations: Icarus Verilog (free software) |
or Synopsys VCS MX (commercial); |
- for synthesis: Icarus Verilog (free software) or |
- for synthesis: Xilinx XST (commercial, some versions |
are free), Icarus Verilog (free software) or |
Synopsys Design Compiler (commercial). |
|
As you can easily understand, whatever GNU/Linux or |
51,3 → 52,4
GNU/Linux x86 PC; please check on the Download Area of the |
Simply RISC website at http://www.srisc.com . |
|
|
/SIMULATION.txt
4,8 → 4,9
To run a simulation using the free software Icarus Verilog |
simulator use the following commands: |
|
build_icarus |
run_icarus |
s1_sim_build icarus |
compile_test hello |
s1_sim_run icarus |
|
If you want to use a commercial tool such as Synopsys VCS then |
set up your PATH enviroment variable so that you are able to |
12,8 → 13,9
find the "vcs" executable, and then type in the following |
commands: |
|
build_vcs |
run_vcs |
s1_sim_build vcs |
compile_test hello |
s1_simrun vcs |
|
Within this design the only visible difference between Icarus |
and VCS is the speed: the commercial tool could be hundreds of |
/INSTALL.txt
3,7 → 3,7
|
To install the package just extract it: |
|
tar zxvf s1.tar.gz |
tar zxvf s1_core.tar.gz |
|
then edit the top-level "sourceme" file to reflect the locations |
of the S1 design (we call "S1 root directory" the one containing |
11,8 → 11,7
the first one is mandatory, the second path is needed only if you |
want to update the SPARC Core source file bundled with this tarball |
with an updated version of the T1 design released by the OpenSPARC |
community (to see how to update it, please read UPDATING.txt |
). |
community (to see how to update it, please read UPDATING.txt). |
|
After that just use on your GNU/Linux or Unix box a bash shell |
to source this file: |
/SYNTHESIS.txt
5,17 → 5,23
used for simulations, you can still use the free Icarus |
Verilog software (that will target an FPGA application) |
or a commercial Design Compiler tool from Synopsys (that |
will be used for ASIC). |
will be used for ASIC). In addition there is also a good |
synthesis tool for FPGAs from Xilinx named XST (could be |
"Xilinx Synthesis Tool"). |
|
To synthesize using XST: |
|
s1_synth xst |
|
With Icarus you will use the "fpga" target, to do so |
just run: |
|
build_fpga |
s1_synth fpga |
|
If you want to use Synopsys Design Compiler instead you |
have to use: |
|
build_dc |
s1_synth dc |
|
Please note that the commercial tools are NOT supported, and |
they will probably not work unless you fix all the required |
22,12 → 28,10
parameters properly (we are focusing on free software since |
we want to build up a community of developers around the S1). |
|
The results for these two kinds of scripts are in the |
directories: |
The results for these scripts are in the directories: |
|
run/synth/xst/ |
run/synth/fpga/ |
run/synth/dc/ |
|
and |
|
run/synth/dc/ |
|
/README.txt
1,7 → 1,7
Simply RISC S1 Core |
=================== |
|
This is the README file for the S1 Core (codename "Sirocco"); |
This is the README file for the Simply RISC S1 Core; |
all the informations you need are contained in the text files |
that you can find in the "docs" subdirectory: |
|
21,5 → 21,5
Please note that from OpenCores http://www.opencores.org or the |
Simply RISC website at http://www.srisc.com you can always |
download a single PDF specification that is just a collection of |
the text files included in the CVS tree and listed above. |
the text files included in the SVN tree and listed above. |
|