URL
https://opencores.org/ocsvn/s1_core/s1_core/trunk
Subversion Repositories s1_core
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- This comparison shows the changes necessary to convert path
/s1_core/trunk/docs
- from Rev 111 to Rev 114
- ↔ Reverse comparison
Rev 111 → Rev 114
/INSTALL.txt
1,5 → 1,5
Simply RISC S1 Core - Quick Installation Guide |
============================================== |
S1 Core - Quick Installation Guide |
================================== |
|
To install the package just extract it: |
|
/LICENSE.txt
1,5 → 1,5
Simply RISC S1 Core - License for Design and Documentation |
========================================================== |
S1 Core - License for Design and Documentation |
============================================== |
|
The S1 Core is a free hardware design released under the |
GNU General Public License (GPL) version, 2 unless otherwise |
/README.txt
1,9 → 1,9
Simply RISC S1 Core |
=================== |
S1 Core README |
============== |
|
This is the README file for the Simply RISC S1 Core; |
all the informations you need are contained in the text files |
that you can find in the "docs" subdirectory: |
This is the README file for the S1 Core; all the information |
you need are contained in the text files that you can find in |
the "docs" subdirectory: |
|
- README.txt Summary (this file) |
- INSTALL.txt Quick Installation Guide |
18,8 → 18,7
|
Probably now you just have to read the docs/INSTALL.txt file. |
|
Please note that from OpenCores http://www.opencores.org or the |
Simply RISC website at http://www.srisc.com you can always |
download a single PDF specification that is just a collection of |
the text files included in the SVN tree and listed above. |
Please note that from OpenCores http://www.opencores.org you can |
always download a single PDF specification that is just a collection |
of the text files included in the SVN tree and listed above. |
|
/REQUIREMENTS.txt
1,5 → 1,5
Simply RISC S1 Core - System Requirements |
========================================= |
S1 Core - System Requirements |
============================= |
|
You can run simulation and synthesis of the S1 Core |
almost on any machine: all you need is a Unix-like |
16,8 → 16,7
As you can easily understand, whatever GNU/Linux or |
Unix machine should be suitable for your purposes; |
we haven't tried on Windows with Cygwin but we suspect |
that it could work (please let us know your experience |
at support@srisc.com and we'll list it here). |
that it could work. |
|
Infact since the only tool you need for simulation and |
synthesis is Icarus Verilog, and since it is free |
49,7 → 48,6
there's an x86 to sparc64 GCC cross-compiler available |
on the web so you should be able to compile test programs |
for the S1 Core using not only a SPARC machine but whatever |
GNU/Linux x86 PC; please check on the Download Area of the |
Simply RISC website at http://www.srisc.com . |
GNU/Linux x86 PC. |
|
|
/SIMULATION.txt
1,5 → 1,5
Simply RISC S1 Core - Simulation Environment |
============================================ |
S1 Core - Simulation Environment |
================================ |
|
To run a simulation using the free software Icarus Verilog |
simulator use the following commands: |
/SPEC.txt
1,5 → 1,5
Simply RISC S1 Core - Functional Specification |
============================================== |
S1 Core - Functional Specification |
================================== |
|
Preface |
------- |
8,7 → 8,7
Wishbone Bridge, a Reset Controller and an Interrupt |
Controller. |
___________________________________ |
| Simply RISC S1 Core | |
| S1 Core | |
| _______ _____ ________ ________ | |
|| || || || || |
|| Reset || Int || SPARC ||Wishbone|| |
35,7 → 35,7
kernel are ready for the T1. |
There's also a complete GNU/Linux distribution, Ubuntu, |
that comes ready for the SPARC Core of the T1 and could be |
used in a seamless way also for Simply RISC S1 based micros. |
used in a seamless way also for S1 based micros. |
|
S1 Memory Map |
------------- |
/SUPPORT.txt
1,7 → 1,7
Simply RISC S1 Core - Support and References |
============================================ |
S1 Core - Support and References |
================================ |
|
The S1 Core has been developed by Simply RISC LLP and |
The S1 Core has been developed by Fabrizio Fazzino and |
the OpenCores community, and it's been released as |
Free Hardware Design under the GPL license version 2. |
You have all the freedom granted by this license, but |
10,8 → 10,8
1) all the files bundled with this package come |
WITHOUT WARRANTY, so USE THEM AT YOUR OWN RISK; |
|
2) you do NOT have the right to pretend the support |
you need from Simply RISC LLP. |
2) you do NOT have the right to demand the support |
you need from Fabrizio Fazzino. |
|
Anyway we will try to provide all the free support |
that we can, and now we try to list how to ask for |
50,19 → 50,3
discuss with real experts about your problems with |
the Wishbone interconnect protocol. |
|
If you still need support or you want to take part |
in the development of the S1 Core, then you can |
contact us at |
|
support@srisc.com |
|
and we will try to help you if possible. If you find |
something that can be corrected and/or improved in |
the design or in the documentation please let us know |
and we will fix it in the next release. |
|
To see if there is a new release available just check |
from time to time on the Simply RISC website: |
|
http://www.srisc.com |
|
/SYNTHESIS.txt
1,5 → 1,5
Simply RISC S1 Core - Synthesis Environment |
=========================================== |
S1 Core - Synthesis Environment |
=============================== |
|
The scripts to run synthesis are similar to the ones |
used for simulations, you can still use the free Icarus |
/TODO.txt
1,5 → 1,5
Simply RISC S1 Core - To Do List |
================================ |
S1 Core - To Do List |
==================== |
|
This is the list of the higher priority tasks: |
- synth problem: Icarus assertion failed |
/UPDATING.txt
1,5 → 1,5
Simply RISC S1 Core - OpenSPARC sources updating |
================================================ |
S1 Core - OpenSPARC sources updating |
==================================== |
|
To update the source files of the SPARC Core to the latest |
version provided by Sun Microsystems with their OpenSPARC |
/other/ACCESSES.txt
1,5 → 1,5
Simply RISC S1 Core - Boot Code |
=============================== |
S1 Core - Boot Code |
=================== |
|
This is the disassembled boot code; the original source code can be |
found inside the official OpenSPARC T1 tarball, in the file: |
/other/BLOCKS.txt
1,5 → 1,5
Simply RISC S1 Core - Blocks of the SPARC Core |
============================================== |
S1 Core - Blocks of the SPARC Core |
================================== |
|
When you are in the OpenSPARC environment and you run |
"rsyn sparc" to synthetize just the SPARC Core, you |