URL
https://opencores.org/ocsvn/s1_core/s1_core/trunk
Subversion Repositories s1_core
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/s1_core/trunk/hdl/behav
- from Rev 103 to Rev 105
- ↔ Reverse comparison
Rev 103 → Rev 105
/testbench/testbench.v
0,0 → 1,186
/* |
* Simply RISC S1 Testbench |
* |
* (C) 2007 Simply RISC LLP |
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com> |
* |
* LICENSE: |
* This is a Free Hardware Design; you can redistribute it and/or |
* modify it under the terms of the GNU General Public License |
* version 2 as published by the Free Software Foundation. |
* The above named program is distributed in the hope that it will |
* be useful, but WITHOUT ANY WARRANTY; without even the implied |
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
* See the GNU General Public License for more details. |
* |
* DESCRIPTION: |
* This is the testbench for the functional verification of the |
* S1 Core: it makes and instance of the S1 module to make it |
* possible to access one or more memory harnesses. |
*/ |
|
`include "s1_defs.h" |
|
module testbench (); |
|
/* |
* Wires |
*/ |
|
// Interrupt Requests |
wire[63:0] sys_irq; |
|
// Wishbone Master inputs / Wishbone Slave ouputs |
wire wb_ack; // Ack |
wire[(`WB_DATA_WIDTH-1):0] wb_datain; // Data In |
|
// Wishbone Master outputs / Wishbone Slave inputs |
wire wb_cycle; // Cycle Start |
wire wb_strobe; // Strobe Request |
wire wb_we_o; // Write Enable |
wire[`WB_ADDR_WIDTH-1:0] wb_addr; // Address Bus |
wire[`WB_DATA_WIDTH-1:0] wb_dataout; // Data Out |
wire[`WB_DATA_WIDTH/8-1:0] wb_sel; // Select Output |
|
// Separate Cycle, Strobe and Ack wires for ROM and RAM memory harnesses |
wire wb_cycle_ram; |
wire wb_cycle_rom; |
wire wb_strobe_ram; |
wire wb_strobe_rom; |
wire wb_ack_ram; |
wire wb_ack_rom; |
|
// Decode the address and select the proper memory bank |
|
assign wb_cycle_rom = ( (wb_addr[39:12]==28'hFFF0000) ? wb_cycle : 0 ); |
assign wb_strobe_rom = ( (wb_addr[39:12]==28'hFFF0000) ? wb_strobe : 0 ); |
|
assign wb_cycle_ram = ( (wb_addr[39:16]==24'h000004) ? wb_cycle : 0 ); |
assign wb_strobe_ram = ( (wb_addr[39:16]==24'h000004) ? wb_strobe : 0 ); |
|
assign wb_ack = wb_ack_ram | wb_ack_rom; |
|
/* |
* Registers |
*/ |
|
// System signals |
reg sys_clock; |
reg sys_reset; |
|
/* |
* Behavior |
*/ |
|
always #1 sys_clock = ~sys_clock; |
assign sys_irq = 64'b0; |
|
initial begin |
|
// Display start message |
$display("INFO: TBENCH: Starting Simply RISC S1 Core simulation..."); |
|
// Create VCD trace file |
$dumpfile("trace.vcd"); |
$dumpvars(); |
|
// Run the simulation |
sys_clock <= 1'b1; |
sys_reset <= 1'b1; |
#1000 |
sys_reset <= 1'b0; |
#49000 |
$display("INFO: TBENCH: Completed Simply RISC S1 Core simulation!"); |
$finish; |
|
end |
|
/* |
* Module instances |
*/ |
|
// Simply RISC S1 Core |
s1_top s1_top_0 ( |
|
// System inputs |
.sys_clock_i(sys_clock), |
.sys_reset_i(sys_reset), |
.sys_irq_i(sys_irq), |
|
// Wishbone Master inputs |
.wbm_ack_i(wb_ack), |
.wbm_data_i(wb_datain), |
|
// Wishbone Master outputs |
.wbm_cycle_o(wb_cycle), |
.wbm_strobe_o(wb_strobe), |
.wbm_we_o(wb_we), |
.wbm_addr_o(wb_addr), |
.wbm_data_o(wb_dataout), |
.wbm_sel_o(wb_sel) |
|
); |
|
// Wishbone memory harness used as ROM |
mem_harness rom_harness ( |
|
// System inputs |
.sys_clock_i(sys_clock), |
.sys_reset_i(sys_reset), |
|
// Wishbone Slave inputs |
.wbs_addr_i(wb_addr), |
.wbs_data_i(wb_dataout), |
.wbs_cycle_i(wb_cycle_rom), |
.wbs_strobe_i(wb_strobe_rom), |
.wbs_sel_i(wb_sel), |
.wbs_we_i(wb_we), |
|
// Wishbone Slave outputs |
.wbs_data_o(wb_datain), |
.wbs_ack_o(wb_ack_rom) |
|
); |
|
// Wishbone memory harness used as RAM |
mem_harness ram_harness ( |
|
// System inputs |
.sys_clock_i(sys_clock), |
.sys_reset_i(sys_reset), |
|
// Wishbone Slave inputs |
.wbs_addr_i(wb_addr), |
.wbs_data_i(wb_dataout), |
.wbs_cycle_i(wb_cycle_ram), |
.wbs_strobe_i(wb_strobe_ram), |
.wbs_sel_i(wb_sel), |
.wbs_we_i(wb_we), |
|
// Wishbone Slave outputs |
.wbs_data_o(wb_datain), |
.wbs_ack_o(wb_ack_ram) |
|
); |
|
/* |
* Parameters for memory harnesses |
*/ |
|
// ROM has Physical Address range [0xFFF0000000:0xFFF0000FFF] |
// so size is 4 KByte and requires 12 address bits |
// 3 of which are ignored being a 64-bit memory => addr_bits=9 |
// (it was section RED_SEC in the official OpenSPARC-T1 testbench) |
defparam rom_harness.addr_bits = 9; |
defparam rom_harness.memfilename = "rom_harness.hex"; |
defparam rom_harness.memdefaultcontent = 64'h0100000001000000; |
|
// RAM has Physical Address range [0x0000040000:0x000004FFFF] |
// so size is 64 KByte and requires 16 address bits |
// 3 of which are ignored being a 64-bit memory => addr_bits=13 |
// (it was section RED_EXT_SEC in the official OpenSPARC-T1 testbench) |
defparam ram_harness.addr_bits = 13; |
defparam ram_harness.memfilename = "ram_harness.hex"; |
defparam ram_harness.memdefaultcontent = 64'h0100000001000000; |
|
endmodule |
testbench/testbench.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: testbench/mem_harness.v
===================================================================
--- testbench/mem_harness.v (nonexistent)
+++ testbench/mem_harness.v (revision 105)
@@ -0,0 +1,141 @@
+/*
+ * Memory Harness with Wishbone Slave interface
+ *
+ * (C) Copyleft 2007 Simply RISC LLP
+ * AUTHOR: Fabrizio Fazzino
+ *
+ * LICENSE:
+ * This is a Free Hardware Design; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ * The above named program is distributed in the hope that it will
+ * be useful, but WITHOUT ANY WARRANTY; without even the implied
+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * DESCRIPTION:
+ * Filename is a parameter, and the corresponding file content
+ * must follow the rules stated in Verilog standard for the
+ * $readmemh() system task.
+ * For instance if you don't change the default name you just
+ * have to put a text file named "memory.hex" in your simulation
+ * directory with the following content inside:
+ *
+ * // We start from address zero by default:
+ * 1234567812345678
+ * FEDCBA9876543210
+ * // Now we jump to doubleword number 10 (i.e. address 80):
+ * @ 10
+ * 02468ACE13579BDF
+ *
+ * This memory harness was originally based upon a Wishbone Slave
+ * model written by Rudolf Usselmann but now I've
+ * written it again entirely from scratch.
+ */
+
+module mem_harness (
+ sys_clock_i, sys_reset_i,
+ wbs_addr_i, wbs_data_i, wbs_data_o, wbs_cycle_i, wbs_strobe_i,
+ wbs_sel_i, wbs_we_i, wbs_ack_o
+ );
+
+ // System inputs
+ input sys_clock_i; // System Clock
+ input sys_reset_i; // System Reset
+
+ // Wishbone Slave interface inputs
+ input wbs_cycle_i; // Wishbone Cycle
+ input wbs_strobe_i; // Wishbone Strobe
+ input[63:0] wbs_addr_i; // Wishbone Address
+ input[63:0] wbs_data_i; // Wishbone Data Input
+ input wbs_we_i; // Wishbone Write Enable
+ input[7:0] wbs_sel_i; // Wishbone Byte Select
+
+ // Wishbone Slave interface registered outputs
+ output wbs_ack_o; // Wishbone Ack
+ reg wbs_ack_o; // Wishbone Ack
+ output[63:0] wbs_data_o; // Wishbone Data Output
+ reg[63:0] wbs_data_o; // Wishbone Data Output
+
+ // Parameters
+ parameter addr_bits = 20;
+ parameter addr_max = (1<
testbench/mem_harness.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: testbench/s1_defs.h
===================================================================
--- testbench/s1_defs.h (nonexistent)
+++ testbench/s1_defs.h (revision 105)
@@ -0,0 +1,48 @@
+/*
+ * Simply RISC S1 Definitions
+ *
+ * (C) Copyleft 2007 Simply RISC LLP
+ * AUTHOR: Fabrizio Fazzino
+ *
+ * LICENSE:
+ * This is a Free Hardware Design; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ * The above named program is distributed in the hope that it will
+ * be useful, but WITHOUT ANY WARRANTY; without even the implied
+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * DESCRIPTION:
+ * Simple constant definitions used by the S1 Core design.
+ */
+
+`include "t1_defs.h"
+`timescale 1ns/100ps
+
+// Size of the buses
+`define WB_ADDR_WIDTH 64
+`define WB_DATA_WIDTH 64
+
+// States of the FSM of the bridge
+`define STATE_WAKEUP 4'b0000
+`define STATE_IDLE 4'b0001
+`define STATE_REQUEST_LATCHED 4'b0010
+`define STATE_PACKET_LATCHED 4'b0011
+`define STATE_REQUEST_GRANTED 4'b0100
+`define STATE_ACCESS2_BEGIN 4'b0101
+`define STATE_ACCESS2_END 4'b0110
+`define STATE_ACCESS3_BEGIN 4'b0111
+`define STATE_ACCESS3_END 4'b1000
+`define STATE_ACCESS4_BEGIN 4'b1001
+`define STATE_ACCESS4_END 4'b1010
+`define STATE_PACKET_READY 4'b1011
+
+// Constants used by the timer of the Reset Controller
+`define TIMER_BITS 16
+`define RESET_CYCLES_1 100
+`define RESET_CYCLES_2 1000
+`define RESET_CYCLES_3 2000
+`define RESET_CYCLES_4 3000
+`define GCLK_CYCLES 900
+
testbench/s1_defs.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sparc_libs/u1_lib.v
===================================================================
--- sparc_libs/u1_lib.v (nonexistent)
+++ sparc_libs/u1_lib.v (revision 105)
@@ -0,0 +1,4332 @@
+// ========== Copyright Header Begin ==========================================
+//
+// OpenSPARC T1 Processor File: u1.behV
+// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
+//
+// The above named program is free software; you can redistribute it and/or
+// modify it under the terms of the GNU General Public
+// License version 2 as published by the Free Software Foundation.
+//
+// The above named program is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public
+// License along with this work; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// ========== Copyright Header End ============================================
+////////////////////////////////////////////////////////////////////////
+//
+// basic gates {
+//
+////////////////////////////////////////////////////////////////////////
+
+
+//bw_u1_inv_0p6x
+//
+//
+
+module bw_u1_inv_0p6x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_1x
+//
+//
+
+module bw_u1_inv_1x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_1p4x
+//
+//
+
+module bw_u1_inv_1p4x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_2x
+//
+//
+
+module bw_u1_inv_2x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_3x
+//
+//
+
+module bw_u1_inv_3x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_4x
+//
+//
+
+module bw_u1_inv_4x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+
+//bw_u1_inv_5x
+//
+//
+
+module bw_u1_inv_5x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_8x
+//
+//
+
+module bw_u1_inv_8x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_10x
+//
+//
+
+module bw_u1_inv_10x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_15x
+//
+//
+
+module bw_u1_inv_15x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_20x
+//
+//
+
+module bw_u1_inv_20x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_30x
+//
+//
+
+module bw_u1_inv_30x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_inv_40x
+//
+//
+
+module bw_u1_inv_40x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+//bw_u1_invh_15x
+//
+//
+
+module bw_u1_invh_15x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+//bw_u1_invh_25x
+//
+//
+
+module bw_u1_invh_25x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_invh_30x
+//
+//
+
+module bw_u1_invh_30x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_invh_50x
+//
+//
+
+module bw_u1_invh_50x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+//bw_u1_invh_60x
+//
+//
+
+module bw_u1_invh_60x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ~( a );
+
+endmodule
+
+
+
+
+//bw_u1_nand2_0p4x
+//
+//
+module bw_u1_nand2_0p4x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_0p6x
+//
+//
+module bw_u1_nand2_0p6x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_1x
+//
+//
+module bw_u1_nand2_1x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_1p4x
+//
+//
+module bw_u1_nand2_1p4x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_2x
+//
+//
+module bw_u1_nand2_2x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_3x
+//
+//
+module bw_u1_nand2_3x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_4x
+//
+//
+module bw_u1_nand2_4x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_5x
+//
+//
+module bw_u1_nand2_5x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_7x
+//
+//
+module bw_u1_nand2_7x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_10x
+//
+//
+module bw_u1_nand2_10x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand2_15x
+//
+//
+module bw_u1_nand2_15x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a & b );
+
+endmodule
+
+
+//bw_u1_nand3_0p4x
+//
+//
+module bw_u1_nand3_0p4x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+
+
+//bw_u1_nand3_0p6x
+//
+//
+module bw_u1_nand3_0p6x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+
+//bw_u1_nand3_1x
+
+//
+//
+module bw_u1_nand3_1x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+//bw_u1_nand3_1p4x
+
+//
+//
+module bw_u1_nand3_1p4x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+//bw_u1_nand3_2x
+
+//
+//
+module bw_u1_nand3_2x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+//bw_u1_nand3_3x
+
+//
+//
+module bw_u1_nand3_3x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+//bw_u1_nand3_4x
+
+//
+//
+module bw_u1_nand3_4x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+//bw_u1_nand3_5x
+
+//
+//
+module bw_u1_nand3_5x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+//bw_u1_nand3_7x
+
+//
+//
+module bw_u1_nand3_7x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+//bw_u1_nand3_10x
+
+//
+//
+module bw_u1_nand3_10x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a & b & c );
+
+endmodule
+
+
+//bw_u1_nand4_0p6x
+
+//
+//
+module bw_u1_nand4_0p6x (
+ z,
+ a,
+ b,
+ c,
+ d );
+
+ output z;
+ input a;
+ input b;
+ input c;
+ input d;
+
+ assign z = ~( a & b & c & d );
+
+endmodule
+
+
+//bw_u1_nand4_1x
+//
+//
+module bw_u1_nand4_1x (
+ z,
+ a,
+ b,
+ c,
+ d );
+
+ output z;
+ input a;
+ input b;
+ input c;
+ input d;
+
+ assign z = ~( a & b & c & d );
+
+endmodule
+
+
+//bw_u1_nand4_1p4x
+//
+//
+module bw_u1_nand4_1p4x (
+ z,
+ a,
+ b,
+ c,
+ d );
+
+ output z;
+ input a;
+ input b;
+ input c;
+ input d;
+
+ assign z = ~( a & b & c & d );
+
+endmodule
+
+
+//bw_u1_nand4_2x
+//
+//
+module bw_u1_nand4_2x (
+ z,
+ a,
+ b,
+ c,
+ d );
+
+ output z;
+ input a;
+ input b;
+ input c;
+ input d;
+
+ assign z = ~( a & b & c & d );
+
+endmodule
+
+
+//bw_u1_nand4_3x
+//
+//
+module bw_u1_nand4_3x (
+ z,
+ a,
+ b,
+ c,
+ d );
+
+ output z;
+ input a;
+ input b;
+ input c;
+ input d;
+
+ assign z = ~( a & b & c & d );
+
+endmodule
+
+
+//bw_u1_nand4_4x
+//
+//
+module bw_u1_nand4_4x (
+ z,
+ a,
+ b,
+ c,
+ d );
+
+ output z;
+ input a;
+ input b;
+ input c;
+ input d;
+
+ assign z = ~( a & b & c & d );
+
+endmodule
+
+
+//bw_u1_nand4_6x
+//
+//
+
+module bw_u1_nand4_6x (
+ z,
+ a,
+ b,
+ c,
+ d );
+
+ output z;
+ input a;
+ input b;
+ input c;
+ input d;
+
+
+ nand( z, a, b,c,d);
+
+endmodule
+
+//bw_u1_nand4_8x
+//
+//
+
+module bw_u1_nand4_8x (
+ z,
+ a,
+ b,
+ c,
+ d );
+
+ output z;
+ input a;
+ input b;
+ input c;
+ input d;
+
+
+ nand( z, a, b,c,d);
+
+endmodule
+
+//bw_u1_nor2_0p6x
+//
+//
+
+module bw_u1_nor2_0p6x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+//bw_u1_nor2_1x
+//
+//
+
+module bw_u1_nor2_1x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+//bw_u1_nor2_1p4x
+//
+//
+
+module bw_u1_nor2_1p4x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+//bw_u1_nor2_2x
+//
+//
+
+module bw_u1_nor2_2x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+//bw_u1_nor2_3x
+//
+//
+
+module bw_u1_nor2_3x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+//bw_u1_nor2_4x
+//
+//
+
+module bw_u1_nor2_4x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+//bw_u1_nor2_6x
+//
+//
+
+module bw_u1_nor2_6x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+//bw_u1_nor2_8x
+//
+//
+
+module bw_u1_nor2_8x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+//bw_u1_nor2_12x
+//
+//
+
+module bw_u1_nor2_12x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a | b );
+
+endmodule
+
+
+
+
+//bw_u1_nor3_0p6x
+//
+//
+
+module bw_u1_nor3_0p6x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a | b | c );
+
+endmodule
+
+
+//bw_u1_nor3_1x
+//
+//
+
+module bw_u1_nor3_1x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a | b | c );
+
+endmodule
+
+
+//bw_u1_nor3_1p4x
+//
+//
+
+module bw_u1_nor3_1p4x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a | b | c );
+
+endmodule
+
+
+//bw_u1_nor3_2x
+//
+//
+
+module bw_u1_nor3_2x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a | b | c );
+
+endmodule
+
+
+//bw_u1_nor3_3x
+//
+//
+
+module bw_u1_nor3_3x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a | b | c );
+
+endmodule
+
+
+//bw_u1_nor3_4x
+//
+//
+
+module bw_u1_nor3_4x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a | b | c );
+
+endmodule
+
+
+//bw_u1_nor3_6x
+//
+//
+
+module bw_u1_nor3_6x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a | b | c );
+
+endmodule
+
+
+//bw_u1_nor3_8x
+//
+//
+
+module bw_u1_nor3_8x (
+ z,
+ a,
+ b,
+ c );
+
+ output z;
+ input a;
+ input b;
+ input c;
+
+ assign z = ~( a | b | c );
+
+endmodule
+
+
+//bw_u1_aoi21_0p4x
+//
+//
+module bw_u1_aoi21_0p4x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 & b2 ) | ( a ));
+
+endmodule
+//bw_u1_aoi21_1x
+//
+//
+module bw_u1_aoi21_1x (
+
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 & b2 ) | ( a ));
+
+endmodule
+//bw_u1_aoi21_2x
+//
+//
+module bw_u1_aoi21_2x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 & b2 ) | ( a ));
+
+endmodule
+//bw_u1_aoi21_4x
+//
+//
+module bw_u1_aoi21_4x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 & b2 ) | ( a ));
+
+endmodule
+//bw_u1_aoi21_8x
+//
+//
+module bw_u1_aoi21_8x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 & b2 ) | ( a ));
+
+endmodule
+//bw_u1_aoi21_12x
+//
+//
+module bw_u1_aoi21_12x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 & b2 ) | ( a ));
+
+endmodule
+//bw_u1_aoi22_0p4x
+//
+//
+module bw_u1_aoi22_0p4x (
+ z,
+ a1,
+ a2,
+ b1,
+ b2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+
+ assign z = ~(( a1 & a2 ) | ( b1 & b2 ));
+
+endmodule
+//bw_u1_aoi22_1x
+//
+//
+module bw_u1_aoi22_1x (
+ z,
+ b1,
+ b2,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input a1;
+ input a2;
+
+
+ assign z = ~(( a1 & a2 ) | ( b1 & b2 ));
+
+endmodule
+//bw_u1_aoi22_2x
+//
+//
+module bw_u1_aoi22_2x (
+
+
+ z,
+ b1,
+ b2,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input a1;
+ input a2;
+
+ assign z = ~(( a1 & a2 ) | ( b1 & b2 ));
+
+endmodule
+//bw_u1_aoi22_4x
+//
+//
+module bw_u1_aoi22_4x (
+
+ z,
+ b1,
+ b2,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input a1;
+ input a2;
+
+ assign z = ~(( a1 & a2 ) | ( b1 & b2 ));
+
+endmodule
+//bw_u1_aoi22_8x
+//
+//
+module bw_u1_aoi22_8x (
+
+ z,
+ b1,
+ b2,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input a1;
+ input a2;
+
+ assign z = ~(( a1 & a2 ) | ( b1 & b2 ));
+
+endmodule
+//bw_u1_aoi211_0p3x
+//
+//
+module bw_u1_aoi211_0p3x (
+
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+ assign z = ~(( c1 & c2 ) | (a)| (b));
+
+endmodule
+
+//bw_u1_aoi211_1x
+//
+//
+module bw_u1_aoi211_1x (
+
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+ assign z = ~(( c1 & c2 ) | (a)| (b));
+
+endmodule
+
+//bw_u1_aoi211_2x
+//
+//
+module bw_u1_aoi211_2x (
+
+
+
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+
+ assign z = ~(( c1 & c2 ) | (a)| (b));
+
+endmodule
+
+//bw_u1_aoi211_4x
+//
+//
+module bw_u1_aoi211_4x (
+
+
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+
+
+ assign z = ~(( c1 & c2 ) | (a)| (b));
+
+endmodule
+
+//bw_u1_aoi211_8x
+//
+//
+module bw_u1_aoi211_8x (
+
+
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+
+
+ assign z = ~(( c1 & c2 ) | (a)| (b));
+
+endmodule
+
+//bw_u1_oai21_0p4x
+//
+//
+module bw_u1_oai21_0p4x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 | b2 ) & ( a ));
+
+endmodule
+
+
+
+//bw_u1_oai21_1x
+//
+//
+module bw_u1_oai21_1x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 | b2 ) & ( a ));
+
+endmodule
+
+
+
+//bw_u1_oai21_2x
+//
+//
+module bw_u1_oai21_2x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 | b2 ) & ( a ));
+
+endmodule
+
+
+
+//bw_u1_oai21_4x
+//
+//
+module bw_u1_oai21_4x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 | b2 ) & ( a ));
+
+endmodule
+
+
+
+//bw_u1_oai21_8x
+//
+//
+module bw_u1_oai21_8x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 | b2 ) & ( a ));
+
+endmodule
+
+
+
+//bw_u1_oai21_12x
+//
+//
+module bw_u1_oai21_12x (
+ z,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 | b2 ) & ( a ));
+
+endmodule
+
+
+
+//bw_u1_oai22_0p4x
+//
+module bw_u1_oai22_0p4x (
+ z,
+ a1,
+ a2,
+ b1,
+ b2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+
+ assign z = ~(( a1 | a2 ) & ( b1 | b2 ));
+
+endmodule
+
+//bw_u1_oai22_1x
+//
+module bw_u1_oai22_1x (
+ z,
+ a1,
+ a2,
+ b1,
+ b2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+
+ assign z = ~(( a1 | a2 ) & ( b1 | b2 ));
+
+endmodule
+
+//bw_u1_oai22_2x
+//
+module bw_u1_oai22_2x (
+ z,
+ a1,
+ a2,
+ b1,
+ b2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+
+ assign z = ~(( a1 | a2 ) & ( b1 | b2 ));
+
+endmodule
+
+//bw_u1_oai22_4x
+//
+module bw_u1_oai22_4x (
+ z,
+ a1,
+ a2,
+ b1,
+ b2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+
+ assign z = ~(( a1 | a2 ) & ( b1 | b2 ));
+
+endmodule
+
+//bw_u1_oai22_8x
+//
+module bw_u1_oai22_8x (
+ z,
+ a1,
+ a2,
+ b1,
+ b2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+
+ assign z = ~(( a1 | a2 ) & ( b1 | b2 ));
+
+endmodule
+
+//bw_u1_oai211_0p3x
+//
+//
+module bw_u1_oai211_0p3x (
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b));
+
+endmodule
+
+//bw_u1_oai211_1x
+//
+//
+module bw_u1_oai211_1x (
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b));
+
+endmodule
+
+//bw_u1_oai211_2x
+//
+//
+module bw_u1_oai211_2x (
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b));
+
+endmodule
+
+//bw_u1_oai211_4x
+//
+//
+module bw_u1_oai211_4x (
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b));
+
+endmodule
+
+//bw_u1_oai211_8x
+//
+//
+module bw_u1_oai211_8x (
+ z,
+ c1,
+ c2,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b));
+
+endmodule
+
+//bw_u1_aoi31_1x
+//
+//
+module bw_u1_aoi31_1x (
+
+
+ z,
+ b1,
+ b2,
+ b3,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a;
+
+ assign z = ~(( b1 & b2&b3 ) | ( a ));
+
+endmodule
+//bw_u1_aoi31_2x
+//
+//
+module bw_u1_aoi31_2x (
+
+ z,
+ b1,
+ b2,
+ b3,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a;
+
+ assign z = ~(( b1 & b2&b3 ) | ( a ));
+
+endmodule
+//bw_u1_aoi31_4x
+//
+//
+module bw_u1_aoi31_4x (
+ z,
+ b1,
+ b2,
+ b3,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a;
+
+ assign z = ~(( b1 & b2&b3 ) | ( a ));
+
+endmodule
+//bw_u1_aoi31_8x
+//
+//
+module bw_u1_aoi31_8x (
+
+ z,
+ b1,
+ b2,
+ b3,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a;
+
+ assign z = ~(( b1 & b2&b3 ) | ( a ));
+
+endmodule
+//bw_u1_aoi32_1x
+//
+//
+module bw_u1_aoi32_1x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+
+ assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 ));
+
+endmodule
+
+//bw_u1_aoi32_2x
+//
+//
+module bw_u1_aoi32_2x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+
+
+
+ assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 ));
+
+endmodule
+
+//bw_u1_aoi32_4x
+//
+//
+module bw_u1_aoi32_4x (
+
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+
+
+
+ assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 ));
+
+endmodule
+
+//bw_u1_aoi32_8x
+//
+//
+module bw_u1_aoi32_8x (
+
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+
+
+ assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 ));
+
+endmodule
+
+//bw_u1_aoi33_1x
+//
+//
+module bw_u1_aoi33_1x (
+
+
+
+
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2,
+ a3 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+ input a3;
+
+ assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 ));
+
+endmodule
+
+
+//bw_u1_aoi33_2x
+//
+//
+module bw_u1_aoi33_2x (
+
+
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2,
+ a3 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+ input a3;
+
+
+ assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 ));
+
+endmodule
+
+
+//bw_u1_aoi33_4x
+//
+//
+module bw_u1_aoi33_4x (
+
+
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2,
+ a3 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+ input a3;
+
+
+
+ assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 ));
+
+endmodule
+
+
+//bw_u1_aoi33_8x
+//
+//
+module bw_u1_aoi33_8x (
+
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2,
+ a3 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+ input a3;
+
+
+
+ assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 ));
+
+endmodule
+
+
+//bw_u1_aoi221_1x
+//
+//
+module bw_u1_aoi221_1x (
+
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( c1 & c2 ) | (b1&b2)| (a));
+
+endmodule
+
+
+//bw_u1_aoi221_2x
+//
+//
+module bw_u1_aoi221_2x (
+
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a;
+
+
+ assign z = ~(( c1 & c2 ) | (b1&b2)| (a));
+
+endmodule
+
+
+//bw_u1_aoi221_4x
+//
+//
+module bw_u1_aoi221_4x (
+
+
+
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a;
+
+
+ assign z = ~(( c1 & c2 ) | (b1&b2)| (a));
+
+endmodule
+
+
+//bw_u1_aoi221_8x
+//
+//
+module bw_u1_aoi221_8x (
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a;
+
+
+ assign z = ~(( c1 & c2 ) | (b1&b2)| (a));
+
+endmodule
+
+
+//bw_u1_aoi222_1x
+//
+//
+module bw_u1_aoi222_1x (
+
+ z,
+ a1,
+ a2,
+ b1,
+ b2,
+ c1,
+ c2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+ input c1;
+ input c2;
+
+ assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2));
+
+endmodule
+
+//bw_u1_aoi222_2x
+//
+//
+module bw_u1_aoi222_2x (
+
+ z,
+ a1,
+ a2,
+ b1,
+ b2,
+ c1,
+ c2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+ input c1;
+ input c2;
+
+ assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2));
+
+endmodule
+
+
+//bw_u1_aoi222_4x
+//
+//
+module bw_u1_aoi222_4x (
+
+ z,
+ a1,
+ a2,
+ b1,
+ b2,
+ c1,
+ c2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+ input c1;
+ input c2;
+
+ assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2));
+
+endmodule
+
+
+//bw_u1_aoi311_1x
+//
+//
+module bw_u1_aoi311_1x (
+
+ z,
+ c1,
+ c2,
+ c3,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input c3;
+ input b;
+ input a;
+
+ assign z = ~(( c1 & c2& c3 ) | (a)| (b));
+
+endmodule
+
+
+
+
+//bw_u1_aoi311_2x
+//
+//
+module bw_u1_aoi311_2x (
+ z,
+ c1,
+ c2,
+ c3,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input c3;
+ input b;
+ input a;
+
+ assign z = ~(( c1 & c2& c3 ) | (a)| (b));
+
+endmodule
+
+
+
+
+//bw_u1_aoi311_4x
+//
+//
+module bw_u1_aoi311_4x (
+ z,
+ c1,
+ c2,
+ c3,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input c3;
+ input b;
+ input a;
+
+
+ assign z = ~(( c1 & c2& c3 ) | (a)| (b));
+
+endmodule
+
+
+
+
+//bw_u1_aoi311_8x
+//
+//
+module bw_u1_aoi311_8x (
+ z,
+ c1,
+ c2,
+ c3,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input c3;
+ input b;
+ input a;
+
+ assign z = ~(( c1 & c2& c3 ) | (a)| (b));
+
+endmodule
+
+
+
+
+//bw_u1_oai31_1x
+//
+//
+module bw_u1_oai31_1x (
+ z,
+ b1,
+ b2,
+ b3,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a;
+
+ assign z = ~(( b1 | b2|b3 ) & ( a ));
+
+endmodule
+
+
+
+
+//bw_u1_oai31_2x
+//
+//
+module bw_u1_oai31_2x (
+ z,
+ b1,
+ b2,
+ b3,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a;
+
+ assign z = ~(( b1 | b2|b3 ) & ( a ));
+
+endmodule
+
+
+
+
+//bw_u1_oai31_4x
+//
+//
+module bw_u1_oai31_4x (
+ z,
+ b1,
+ b2,
+ b3,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a;
+
+ assign z = ~(( b1 | b2|b3 ) & ( a ));
+
+endmodule
+
+
+
+
+//bw_u1_oai31_8x
+//
+//
+module bw_u1_oai31_8x (
+ z,
+ b1,
+ b2,
+ b3,
+ a );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a;
+
+ assign z = ~(( b1 | b2|b3 ) & ( a ));
+
+endmodule
+
+
+
+
+//bw_u1_oai32_1x
+//
+//
+module bw_u1_oai32_1x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+
+ assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 ));
+
+endmodule
+
+
+
+//bw_u1_oai32_2x
+//
+//
+module bw_u1_oai32_2x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+
+ assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 ));
+
+endmodule
+
+
+
+//bw_u1_oai32_4x
+//
+//
+module bw_u1_oai32_4x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+
+ assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 ));
+
+endmodule
+
+
+
+//bw_u1_oai32_8x
+//
+//
+module bw_u1_oai32_8x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+
+ assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 ));
+
+endmodule
+
+
+
+//bw_u1_oai33_1x
+//
+//
+module bw_u1_oai33_1x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2,
+ a3 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+ input a3;
+
+ assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 ));
+
+endmodule
+
+
+//bw_u1_oai33_2x
+//
+//
+module bw_u1_oai33_2x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2,
+ a3 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+ input a3;
+
+ assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 ));
+
+endmodule
+
+
+//bw_u1_oai33_4x
+//
+//
+module bw_u1_oai33_4x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2,
+ a3 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+ input a3;
+
+ assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 ));
+
+endmodule
+
+
+//bw_u1_oai33_8x
+//
+//
+module bw_u1_oai33_8x (
+ z,
+ b1,
+ b2,
+ b3,
+ a1,
+ a2,
+ a3 );
+
+ output z;
+ input b1;
+ input b2;
+ input b3;
+ input a1;
+ input a2;
+ input a3;
+
+ assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 ));
+
+endmodule
+
+
+//bw_u1_oai221_1x
+//
+//
+module bw_u1_oai221_1x (
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2));
+
+endmodule
+
+//bw_u1_oai221_2x
+//
+//
+module bw_u1_oai221_2x (
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2));
+
+endmodule
+
+//bw_u1_oai221_4x
+//
+//
+module bw_u1_oai221_4x (
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2));
+
+endmodule
+
+//bw_u1_oai221_8x
+//
+//
+module bw_u1_oai221_8x (
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2));
+
+endmodule
+
+//bw_u1_oai222_1x
+//
+//
+module bw_u1_oai222_1x (
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a1,
+ a2 );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a1;
+ input a2;
+
+ assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2));
+
+endmodule
+
+
+//bw_u1_oai222_2x
+//
+//
+module bw_u1_oai222_2x (
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a1,
+ a2 );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a1;
+ input a2;
+
+ assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2));
+
+endmodule
+
+
+//bw_u1_oai222_4x
+//
+//
+module bw_u1_oai222_4x (
+ z,
+ c1,
+ c2,
+ b1,
+ b2,
+ a1,
+ a2 );
+
+ output z;
+ input c1;
+ input c2;
+ input b1;
+ input b2;
+ input a1;
+ input a2;
+
+ assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2));
+
+endmodule
+
+
+//bw_u1_oai311_1x
+//
+//
+module bw_u1_oai311_1x (
+ z,
+ c1,
+ c2,
+ c3,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input c3;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2|c3 ) & ( a ) & (b));
+
+endmodule
+
+
+//bw_u1_oai311_2x
+//
+//
+module bw_u1_oai311_2x (
+ z,
+ c1,
+ c2,
+ c3,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input c3;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2|c3 ) & ( a ) & (b));
+
+endmodule
+
+
+//bw_u1_oai311_4x
+//
+//
+module bw_u1_oai311_4x (
+ z,
+ c1,
+ c2,
+ c3,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input c3;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2 | c3 ) & ( a ) & (b));
+
+endmodule
+
+
+//bw_u1_oai311_8x
+//
+//
+module bw_u1_oai311_8x (
+ z,
+ c1,
+ c2,
+ c3,
+ b,
+ a );
+
+ output z;
+ input c1;
+ input c2;
+ input c3;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2|c3 ) & ( a ) & (b));
+
+endmodule
+
+
+//bw_u1_muxi21_0p6x
+
+
+
+module bw_u1_muxi21_0p6x (z, d0, d1, s);
+output z;
+input d0, d1, s;
+
+ assign z = s ? ~d1 : ~d0;
+endmodule
+
+
+//bw_u1_muxi21_1x
+
+
+
+module bw_u1_muxi21_1x (z, d0, d1, s);
+output z;
+input d0, d1, s;
+
+ assign z = s ? ~d1 : ~d0;
+endmodule
+
+
+
+
+
+
+
+//bw_u1_muxi21_2x
+
+
+
+module bw_u1_muxi21_2x (z, d0, d1, s);
+output z;
+input d0, d1, s;
+
+ assign z = s ? ~d1 : ~d0;
+endmodule
+
+
+//bw_u1_muxi21_4x
+
+
+
+module bw_u1_muxi21_4x (z, d0, d1, s);
+output z;
+input d0, d1, s;
+
+ assign z = s ? ~d1 : ~d0;
+endmodule
+
+
+
+
+//bw_u1_muxi21_6x
+
+
+module bw_u1_muxi21_6x (z, d0, d1, s);
+output z;
+input d0, d1, s;
+
+ assign z = s ? ~d1 : ~d0;
+endmodule
+
+//bw_u1_muxi31d_4x
+//
+
+module bw_u1_muxi31d_4x (z, d0, d1, d2, s0, s1, s2);
+output z;
+input d0, d1, d2, s0, s1, s2;
+ zmuxi31d_prim i0 ( z, d0, d1, d2, s0, s1, s2 );
+endmodule
+
+//bw_u1_muxi41d_4x
+//
+
+module bw_u1_muxi41d_4x (z, d0, d1, d2, d3, s0, s1, s2, s3);
+output z;
+input d0, d1, d2, d3, s0, s1, s2, s3;
+ zmuxi41d_prim i0 ( z, d0, d1, d2, d3, s0, s1, s2, s3 );
+endmodule
+
+//bw_u1_muxi41d_6x
+//
+
+module bw_u1_muxi41d_6x (z, d0, d1, d2, d3, s0, s1, s2, s3);
+output z;
+input d0, d1, d2, d3, s0, s1, s2, s3;
+ zmuxi41d_prim i0 ( z, d0, d1, d2, d3, s0, s1, s2, s3 );
+endmodule
+
+
+//bw_u1_xor2_0p6x
+//
+//
+module bw_u1_xor2_0p6x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ( a ^ b );
+
+endmodule
+//bw_u1_xor2_1x
+//
+//
+module bw_u1_xor2_1x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ( a ^ b );
+
+endmodule
+//bw_u1_xor2_2x
+//
+//
+module bw_u1_xor2_2x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ( a ^ b );
+
+endmodule
+//bw_u1_xor2_4x
+//
+//
+module bw_u1_xor2_4x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ( a ^ b );
+
+endmodule
+//bw_u1_xnor2_0p6x
+//
+//
+module bw_u1_xnor2_0p6x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a ^ b );
+
+endmodule
+//bw_u1_xnor2_1x
+//
+//
+module bw_u1_xnor2_1x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a ^ b );
+
+endmodule
+//bw_u1_xnor2_2x
+//
+//
+module bw_u1_xnor2_2x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a ^ b );
+
+endmodule
+//bw_u1_xnor2_4x
+//
+//
+module bw_u1_xnor2_4x (
+ z,
+ a,
+ b );
+
+ output z;
+ input a;
+ input b;
+
+ assign z = ~( a ^ b );
+
+endmodule
+
+//bw_u1_buf_1x
+//
+
+module bw_u1_buf_1x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+//bw_u1_buf_5x
+//
+
+module bw_u1_buf_5x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+
+//bw_u1_buf_10x
+//
+
+module bw_u1_buf_10x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+
+//bw_u1_buf_15x
+//
+
+module bw_u1_buf_15x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+
+//bw_u1_buf_20x
+//
+
+module bw_u1_buf_20x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+
+//bw_u1_buf_30x
+//
+
+module bw_u1_buf_30x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+
+//bw_u1_buf_40x
+//
+
+module bw_u1_buf_40x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+
+//bw_u1_ao2222_1x
+//
+//
+module bw_u1_ao2222_1x (
+
+ z,
+ a1,
+ a2,
+ b1,
+ b2,
+ c1,
+ c2,
+ d1,
+ d2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+ input c1;
+ input c2;
+ input d1;
+ input d2;
+
+ assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2));
+
+endmodule
+
+
+//bw_u1_ao2222_2x
+//
+//
+module bw_u1_ao2222_2x (
+
+ z,
+ a1,
+ a2,
+ b1,
+ b2,
+ c1,
+ c2,
+ d1,
+ d2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+ input c1;
+ input c2;
+ input d1;
+ input d2;
+
+ assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2));
+
+endmodule
+
+//bw_u1_ao2222_4x
+//
+//
+module bw_u1_ao2222_4x (
+
+ z,
+ a1,
+ a2,
+ b1,
+ b2,
+ c1,
+ c2,
+ d1,
+ d2 );
+
+ output z;
+ input a1;
+ input a2;
+ input b1;
+ input b2;
+ input c1;
+ input c2;
+ input d1;
+ input d2;
+
+ assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2));
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////
+//
+// flipflops {
+//
+////////////////////////////////////////////////////////////////////////
+
+// scanable D-flipflop with scanout
+
+module bw_u1_soff_1x (q, so, ck, d, se, sd);
+output q, so;
+input ck, d, se, sd;
+ zsoff_prim i0 ( q, so, ck, d, se, sd );
+endmodule
+
+module bw_u1_soff_2x (q, so, ck, d, se, sd);
+output q, so;
+input ck, d, se, sd;
+ zsoff_prim i0 ( q, so, ck, d, se, sd );
+endmodule
+
+module bw_u1_soff_4x (q, so, ck, d, se, sd);
+output q, so;
+input ck, d, se, sd;
+ zsoff_prim i0 ( q, so, ck, d, se, sd );
+endmodule
+
+module bw_u1_soff_8x (q, so, ck, d, se, sd);
+output q, so;
+input ck, d, se, sd;
+ zsoff_prim i0 ( q, so, ck, d, se, sd );
+endmodule
+
+// fast scanable D-flipflop with scanout with inverted Q output
+
+module bw_u1_soffi_4x (q_l, so, ck, d, se, sd);
+output q_l, so;
+input ck, d, se, sd;
+ zsoffi_prim i0 ( q_l, so, ck, d, se, sd );
+endmodule
+
+module bw_u1_soffi_8x (q_l, so, ck, d, se, sd);
+output q_l, so;
+input ck, d, se, sd;
+ zsoffi_prim i0 ( q_l, so, ck, d, se, sd );
+endmodule
+
+// scanable D-flipflop with scanout with 2-to-1 input mux
+
+module bw_u1_soffm2_4x (q, so, ck, d0, d1, s, se, sd);
+output q, so;
+input ck, d0, d1, s, se, sd;
+ zsoffm2_prim i0 ( q, so, ck, d0, d1, s, se, sd );
+endmodule
+
+module bw_u1_soffm2_8x (q, so, ck, d0, d1, s, se, sd);
+output q, so;
+input ck, d0, d1, s, se, sd;
+ zsoffm2_prim i0 ( q, so, ck, d0, d1, s, se, sd );
+endmodule
+
+// scanable D-flipflop with scanout with sync reset-bar
+
+module bw_u1_soffr_2x (q, so, ck, d, se, sd, r_l);
+output q, so;
+input ck, d, se, sd, r_l;
+ zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l );
+endmodule
+
+module bw_u1_soffr_4x (q, so, ck, d, se, sd, r_l);
+output q, so;
+input ck, d, se, sd, r_l;
+ zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l );
+endmodule
+
+module bw_u1_soffr_8x (q, so, ck, d, se, sd, r_l);
+output q, so;
+input ck, d, se, sd, r_l;
+ zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l );
+endmodule
+
+//bw_u1_soffasr_2x
+
+module bw_u1_soffasr_2x (q, so, ck, d, r_l, s_l, se, sd);
+output q, so;
+input ck, d, r_l, s_l, se, sd;
+ zsoffasr_prim i0 (q, so, ck, d, r_l, s_l, se, sd);
+endmodule
+
+
+//bw_u1_ckbuf_1p5x
+
+
+module bw_u1_ckbuf_1p5x (clk, rclk);
+output clk;
+input rclk;
+ buf (clk, rclk);
+endmodule
+
+
+//bw_u1_ckbuf_3x
+
+
+module bw_u1_ckbuf_3x (clk, rclk);
+output clk;
+input rclk;
+ buf (clk, rclk);
+endmodule
+
+//bw_u1_ckbuf_4p5x
+
+
+module bw_u1_ckbuf_4p5x (clk, rclk);
+output clk;
+input rclk;
+ buf (clk, rclk);
+endmodule
+
+
+//bw_u1_ckbuf_6x
+
+
+module bw_u1_ckbuf_6x (clk, rclk);
+output clk;
+input rclk;
+ buf (clk, rclk);
+endmodule
+
+//bw_u1_ckbuf_7x
+//
+
+module bw_u1_ckbuf_7x (clk, rclk);
+output clk;
+input rclk;
+ buf (clk, rclk);
+endmodule
+
+//bw_u1_ckbuf_8x
+//
+module bw_u1_ckbuf_8x (clk, rclk);
+output clk;
+input rclk;
+ buf (clk, rclk);
+endmodule
+
+
+//bw_u1_ckbuf_11x
+//
+
+module bw_u1_ckbuf_11x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+//bw_u1_ckbuf_14x
+//
+
+module bw_u1_ckbuf_14x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+//bw_u1_ckbuf_17x
+//
+
+module bw_u1_ckbuf_17x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+
+
+
+//bw_u1_ckbuf_19x
+//
+
+module bw_u1_ckbuf_19x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+
+
+
+//bw_u1_ckbuf_22x
+//
+
+module bw_u1_ckbuf_22x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+//bw_u1_ckbuf_25x
+//
+
+module bw_u1_ckbuf_25x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+
+//bw_u1_ckbuf_28x
+//
+
+module bw_u1_ckbuf_28x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+
+//bw_u1_ckbuf_30x
+//
+
+module bw_u1_ckbuf_30x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+//bw_u1_ckbuf_33x
+//
+
+module bw_u1_ckbuf_33x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+//bw_u1_ckbuf_40x
+//
+
+module bw_u1_ckbuf_40x (clk, rclk);
+output clk;
+input rclk;
+
+ assign clk = ( rclk );
+
+endmodule
+
+
+// gated clock buffers
+
+
+module bw_u1_ckenbuf_6x (clk, rclk, en_l, tm_l);
+output clk;
+input rclk, en_l, tm_l;
+ zckenbuf_prim i0 ( clk, rclk, en_l, tm_l );
+endmodule
+
+module bw_u1_ckenbuf_14x (clk, rclk, en_l, tm_l);
+output clk;
+input rclk, en_l, tm_l;
+ zckenbuf_prim i0 ( clk, rclk, en_l, tm_l );
+endmodule
+
+////////////////////////////////////////////////////////////////////////
+//
+// half cells
+//
+////////////////////////////////////////////////////////////////////////
+
+
+
+module bw_u1_zhinv_0p6x (z, a);
+output z;
+input a;
+ not (z, a);
+endmodule
+
+
+module bw_u1_zhinv_1x (z, a);
+output z;
+input a;
+ not (z, a);
+endmodule
+
+
+
+module bw_u1_zhinv_1p4x (z, a);
+output z;
+input a;
+ not (z, a);
+endmodule
+
+
+module bw_u1_zhinv_2x (z, a);
+output z;
+input a;
+ not (z, a);
+endmodule
+
+
+
+module bw_u1_zhinv_3x (z, a);
+output z;
+input a;
+ not (z, a);
+endmodule
+
+
+
+module bw_u1_zhinv_4x (z, a);
+output z;
+input a;
+ not (z, a);
+endmodule
+
+
+
+module bw_u1_zhnand2_0p4x (z, a, b);
+output z;
+input a, b;
+ nand (z, a, b);
+endmodule
+
+
+module bw_u1_zhnand2_0p6x (z, a, b);
+output z;
+input a, b;
+ nand (z, a, b);
+endmodule
+
+
+module bw_u1_zhnand2_1x (z, a, b);
+output z;
+input a, b;
+ nand (z, a, b);
+endmodule
+
+
+module bw_u1_zhnand2_1p4x (z, a, b);
+output z;
+input a, b;
+ nand (z, a, b);
+endmodule
+
+
+module bw_u1_zhnand2_2x (z, a, b);
+output z;
+input a, b;
+ nand (z, a, b);
+endmodule
+
+
+module bw_u1_zhnand2_3x (z, a, b);
+output z;
+input a, b;
+ nand (z, a, b);
+endmodule
+
+
+module bw_u1_zhnand3_0p6x (z, a, b, c);
+output z;
+input a, b, c;
+ nand (z, a, b, c);
+endmodule
+
+module bw_u1_zhnand3_1x (z, a, b, c);
+output z;
+input a, b, c;
+ nand (z, a, b, c);
+endmodule
+
+module bw_u1_zhnand3_2x (z, a, b, c);
+output z;
+input a, b, c;
+ nand (z, a, b, c);
+endmodule
+
+
+module bw_u1_zhnand4_0p6x (z, a, b, c, d);
+output z;
+input a, b, c, d;
+ nand (z, a, b, c, d);
+endmodule
+
+module bw_u1_zhnand4_1x (z, a, b, c, d);
+output z;
+input a, b, c, d;
+ nand (z, a, b, c, d);
+endmodule
+
+module bw_u1_zhnand4_2x (z, a, b, c, d);
+output z;
+input a, b, c, d;
+ nand (z, a, b, c, d);
+endmodule
+
+
+
+module bw_u1_zhnor2_0p6x (z, a, b);
+output z;
+input a, b;
+ nor (z, a, b);
+endmodule
+
+module bw_u1_zhnor2_1x (z, a, b);
+output z;
+input a, b;
+ nor (z, a, b);
+endmodule
+
+module bw_u1_zhnor2_2x (z, a, b);
+output z;
+input a, b;
+ nor (z, a, b);
+endmodule
+
+
+
+module bw_u1_zhnor3_0p6x (z, a, b, c);
+output z;
+input a, b, c;
+ nor (z, a, b, c);
+endmodule
+
+
+module bw_u1_zhaoi21_0p4x (z,b1,b2,a);
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 & b2 ) | ( a ));
+
+endmodule
+
+
+
+module bw_u1_zhaoi21_1x (z, a, b1, b2);
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 & b2 ) | ( a ));
+
+endmodule
+
+
+
+module bw_u1_zhoai21_1x (z,b1,b2,a );
+
+ output z;
+ input b1;
+ input b2;
+ input a;
+
+ assign z = ~(( b1 | b2 ) & ( a ));
+
+endmodule
+
+
+
+
+module bw_u1_zhoai211_0p3x (z, a, b, c1, c2);
+ output z;
+ input c1;
+ input c2;
+ input b;
+ input a;
+
+ assign z = ~(( c1 | c2 ) & ( a ) & (b));
+
+endmodule
+
+
+
+
+
+module bw_u1_zhoai211_1x (z, a, b, c1, c2);
+output z;
+input a, b, c1, c2;
+ assign z = ~(( c1 | c2 ) & ( a ) & (b));
+
+endmodule
+
+
+
+
+
+/////////////// Scan data lock up latch ///////////////
+
+module bw_u1_scanlg_2x (so, sd, ck, se);
+output so;
+input sd, ck, se;
+
+reg so_l;
+
+ assign so = ~so_l;
+ always @ ( ck or sd or se )
+ if (~ck) so_l <= ~(sd & se) ;
+
+endmodule
+
+module bw_u1_scanl_2x (so, sd, ck);
+output so;
+input sd, ck;
+
+reg so_l;
+
+ assign so = ~so_l;
+ always @ ( ck or sd )
+ if (~ck) so_l <= ~sd ;
+
+endmodule
+
+
+
+////////////////// Synchronizer ////////////////
+
+module bw_u1_syncff_4x (q, so, ck, d, se, sd);
+output q, so;
+input ck, d, se, sd;
+
+reg q_r;
+ always @ (posedge ck)
+ q_r <= se ? sd : d;
+ assign q = q_r;
+ assign so = q_r;
+
+endmodule
+
+
+
+
+////////////////////////////////////////////////////////////////////////
+//
+// non library cells
+//
+////////////////////////////////////////////////////////////////////////
+
+// These cells are used only in custom DP macros
+// Do not use in any block design without prior permission
+
+
+module bw_u1_zzeccxor2_5x (z, a, b);
+ output z;
+ input a, b;
+ assign z = ( a ^ b );
+
+endmodule
+
+
+
+module bw_u1_zzmulcsa42_5x (sum, carry, cout, a, b, c, d, cin);
+output sum, carry, cout;
+input a, b, c, d, cin;
+wire and_cin_b, or_cin_b, xor_a_c_d, and_or_cin_b_xor_a_c_d;
+wire and_a_c, and_a_d, and_c_d;
+ assign sum = cin ^ a ^ b ^ c ^ d;
+ assign carry = cin & b | (cin | b) & (a ^ c ^ d);
+ assign cout = a & c | a & d | c & d;
+endmodule
+
+
+
+module bw_u1_zzmulcsa32_5x (sum, cout, a, b, c);
+output sum, cout;
+input a, b, c;
+wire and_a_b, and_a_c, and_b_c;
+ assign sum = a ^ b ^ c ;
+ assign cout = a & b | a & c | b & c ;
+endmodule
+
+
+
+module bw_u1_zzmulppmuxi21_2x ( z, d0, d1, s );
+output z;
+input d0, d1, s;
+ assign z = s ? ~d1 : ~d0;
+endmodule
+
+
+
+module bw_u1_zzmulnand2_2x ( z, a, b );
+output z;
+input a;
+input b;
+ assign z = ~( a & b );
+endmodule
+
+
+
+// Primitives
+
+
+
+
+module zmuxi31d_prim (z, d0, d1, d2, s0, s1, s2);
+output z;
+input d0, d1, d2, s0, s1, s2;
+// for Blacktie
+`ifdef VERPLEX
+ $constraint dp_1h3 ($one_hot ({s0,s1,s2}));
+`endif
+wire [2:0] sel = {s0,s1,s2}; // 0in one_hot
+reg z;
+ always @ (s2 or d2 or s1 or d1 or s0 or d0)
+ casez ({s2,d2,s1,d1,s0,d0})
+ 6'b0?0?10: z = 1'b1;
+ 6'b0?0?11: z = 1'b0;
+ 6'b0?100?: z = 1'b1;
+ 6'b0?110?: z = 1'b0;
+ 6'b0?1010: z = 1'b1;
+ 6'b0?1111: z = 1'b0;
+ 6'b100?0?: z = 1'b1;
+ 6'b110?0?: z = 1'b0;
+ 6'b100?10: z = 1'b1;
+ 6'b110?11: z = 1'b0;
+ 6'b10100?: z = 1'b1;
+ 6'b11110?: z = 1'b0;
+ 6'b101010: z = 1'b1;
+ 6'b111111: z = 1'b0;
+ default: z = 1'bx;
+ endcase
+endmodule
+
+
+
+
+
+
+
+module zmuxi41d_prim (z, d0, d1, d2, d3, s0, s1, s2, s3);
+output z;
+input d0, d1, d2, d3, s0, s1, s2, s3;
+// for Blacktie
+`ifdef VERPLEX
+ $constraint dp_1h4 ($one_hot ({s0,s1,s2,s3}));
+`endif
+wire [3:0] sel = {s0,s1,s2,s3}; // 0in one_hot
+reg z;
+ always @ (s3 or d3 or s2 or d2 or s1 or d1 or s0 or d0)
+ casez ({s3,d3,s2,d2,s1,d1,s0,d0})
+ 8'b0?0?0?10: z = 1'b1;
+ 8'b0?0?0?11: z = 1'b0;
+ 8'b0?0?100?: z = 1'b1;
+ 8'b0?0?110?: z = 1'b0;
+ 8'b0?0?1010: z = 1'b1;
+ 8'b0?0?1111: z = 1'b0;
+ 8'b0?100?0?: z = 1'b1;
+ 8'b0?110?0?: z = 1'b0;
+ 8'b0?100?10: z = 1'b1;
+ 8'b0?110?11: z = 1'b0;
+ 8'b0?10100?: z = 1'b1;
+ 8'b0?11110?: z = 1'b0;
+ 8'b0?101010: z = 1'b1;
+ 8'b0?111111: z = 1'b0;
+ 8'b100?0?0?: z = 1'b1;
+ 8'b110?0?0?: z = 1'b0;
+ 8'b100?0?10: z = 1'b1;
+ 8'b110?0?11: z = 1'b0;
+ 8'b100?100?: z = 1'b1;
+ 8'b110?110?: z = 1'b0;
+ 8'b100?1010: z = 1'b1;
+ 8'b110?1111: z = 1'b0;
+ 8'b10100?0?: z = 1'b1;
+ 8'b11110?0?: z = 1'b0;
+ 8'b10100?10: z = 1'b1;
+ 8'b11110?11: z = 1'b0;
+ 8'b1010100?: z = 1'b1;
+ 8'b1111110?: z = 1'b0;
+ 8'b10101010: z = 1'b1;
+ 8'b11111111: z = 1'b0;
+ default: z = 1'bx;
+ endcase
+endmodule
+
+
+
+module zsoff_prim (q, so, ck, d, se, sd);
+output q, so;
+input ck, d, se, sd;
+reg q_r;
+ always @ (posedge ck)
+ q_r <= se ? sd : d;
+ assign q = q_r;
+ assign so = q_r ;
+endmodule
+
+
+module zsoffr_prim (q, so, ck, d, se, sd, r_l);
+output q, so;
+input ck, d, se, sd, r_l;
+reg q_r;
+ always @ (posedge ck)
+ q_r <= se ? sd : (d & r_l) ;
+ assign q = q_r;
+ assign so = q_r;
+endmodule
+
+
+module zsoffi_prim (q_l, so, ck, d, se, sd);
+output q_l, so;
+input ck, d, se, sd;
+reg q_r;
+ always @ (posedge ck)
+ q_r <= se ? sd : d;
+ assign q_l = ~q_r;
+ assign so = q_r;
+endmodule
+
+
+
+module zsoffm2_prim (q, so, ck, d0, d1, s, se, sd);
+output q, so;
+input ck, d0, d1, s, se, sd;
+reg q_r;
+ always @ (posedge ck)
+ q_r <= se ? sd : (s ? d1 : d0) ;
+ assign q = q_r;
+ assign so = q_r;
+endmodule
+
+module zsoffasr_prim (q, so, ck, d, r_l, s_l, se, sd);
+ output q, so;
+ input ck, d, r_l, s_l, se, sd;
+
+ // asynchronous reset and asynchronous set
+ // (priority: r_l > s_l > se > d)
+ reg q;
+ wire so;
+
+ always @ (posedge ck or negedge r_l or negedge s_l) begin
+ if(~r_l) q <= 1'b0;
+ else if (~s_l) q <= r_l;
+ else if (se) q <= r_l & s_l & sd;
+ else q <= r_l & s_l & (~se) & d;
+ end
+
+ assign so = q | ~se;
+
+endmodule
+
+
+
+module zckenbuf_prim (clk, rclk, en_l, tm_l);
+output clk;
+input rclk, en_l, tm_l;
+reg clken;
+
+ always @ (rclk or en_l or tm_l)
+ if (!rclk) //latch opens on rclk low phase
+ clken <= ~en_l | ~tm_l;
+ assign clk = clken & rclk;
+
+endmodule
+
+module bw_mckbuf_40x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_33x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_30x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_28x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_25x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_22x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_19x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_17x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_14x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_11x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_8x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_7x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_6x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_4p5x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_3x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+module bw_mckbuf_1p5x (clk, rclk, en);
+output clk;
+input rclk;
+input en;
+
+ assign clk = rclk & en ;
+
+endmodule
+
+//bw_u1_minbuf_1x
+//
+
+module bw_u1_minbuf_1x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+//bw_u1_minbuf_4x
+//
+
+module bw_u1_minbuf_4x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+//bw_u1_minbuf_5x
+//
+
+module bw_u1_minbuf_5x (
+ z,
+ a );
+
+ output z;
+ input a;
+
+ assign z = ( a );
+
+endmodule
+
+module bw_u1_ckenbuf_4p5x (clk, rclk, en_l, tm_l);
+output clk;
+input rclk, en_l, tm_l;
+ zckenbuf_prim i0 ( clk, rclk, en_l, tm_l );
+endmodule
+
+// dummy fill modules to get rid of DFT "CAP" property errors (bug 5487)
+
+module bw_u1_fill_1x(\vdd! );
+input \vdd! ;
+endmodule
+
+module bw_u1_fill_2x(\vdd! );
+input \vdd! ;
+endmodule
+
+module bw_u1_fill_3x(\vdd! );
+input \vdd! ;
+endmodule
+
+module bw_u1_fill_4x(\vdd! );
+input \vdd! ;
+endmodule
Index: sparc_libs/m1_lib.v
===================================================================
--- sparc_libs/m1_lib.v (nonexistent)
+++ sparc_libs/m1_lib.v (revision 105)
@@ -0,0 +1,1034 @@
+// ========== Copyright Header Begin ==========================================
+//
+// OpenSPARC T1 Processor File: m1.behV
+// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
+//
+// The above named program is free software; you can redistribute it and/or
+// modify it under the terms of the GNU General Public
+// License version 2 as published by the Free Software Foundation.
+//
+// The above named program is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public
+// License along with this work; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// ========== Copyright Header End ============================================
+////////////////////////////////////////////////////////////////////////
+// 64 bit nor gate with first 32 bits out
+
+module zznor64_32 ( znor64, znor32, a );
+ input [63:0] a;
+ output znor64;
+ output znor32;
+
+ assign znor32 = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]
+ | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]
+ | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]);
+
+ assign znor64 = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]
+ | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]
+ | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]
+ | a[32] | a[33] | a[34] | a[35] | a[36] | a[37] | a[38] | a[39]
+ | a[40] | a[41] | a[42] | a[43] | a[44] | a[45] | a[46] | a[47]
+ | a[48] | a[49] | a[50] | a[51] | a[52] | a[53] | a[54] | a[55]
+ | a[56] | a[57] | a[58] | a[59] | a[60] | a[61] | a[62] | a[63]);
+
+endmodule // zznor64_32
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 36 bit or gate
+
+module zzor36 ( z, a );
+ input [35:0] a;
+ output z;
+
+ assign z = (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]
+ | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]
+ | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]
+ | a[32] | a[33] | a[34] | a[35]);
+
+endmodule // zzor36
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 32 bit or gate
+
+module zzor32 ( z, a );
+ input [31:0] a;
+ output z;
+
+ assign z = (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]
+ | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]
+ | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]);
+
+endmodule // zzor32
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 24 bit nor gate
+
+module zznor24 ( z, a );
+ input [23:0] a;
+ output z;
+
+ assign z = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]
+ | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]);
+
+endmodule // zznor24
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 16 bit nor gate
+
+module zznor16 ( z, a );
+ input [15:0] a;
+ output z;
+
+ assign z = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]);
+
+endmodule // zznor16
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 8 bit or gate
+
+module zzor8 ( z, a );
+ input [7:0] a;
+ output z;
+
+ assign z = (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]);
+
+endmodule // zzor8
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Description: This block implements the adder for the sparc FPU.
+// It takes two operands and a carry bit. It adds them together
+// and sends the output to adder_out.
+
+module zzadd13 ( rs1_data, rs2_data, cin, adder_out );
+
+ input [12:0] rs1_data; // 1st input operand
+ input [12:0] rs2_data; // 2nd input operand
+ input cin; // carry in
+
+ output [12:0] adder_out; // result of adder
+
+ assign adder_out = rs1_data + rs2_data + cin;
+
+endmodule // zzadd13
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Description: This block implements the adder for the sparc FPU.
+// It takes two operands and a carry bit. It adds them together
+// and sends the output to adder_out.
+
+module zzadd56 ( rs1_data, rs2_data, cin, adder_out );
+
+ input [55:0] rs1_data; // 1st input operand
+ input [55:0] rs2_data; // 2nd input operand
+ input cin; // carry in
+
+ output [55:0] adder_out; // result of adder
+
+ assign adder_out = rs1_data + rs2_data + cin;
+
+endmodule // zzadd56
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+module zzadd48 ( rs1_data, rs2_data, cin, adder_out );
+
+ input [47:0] rs1_data; // 1st input operand
+ input [47:0] rs2_data; // 2nd input operand
+ input cin; // carry in
+
+ output [47:0] adder_out; // result of adder
+
+ assign adder_out = rs1_data + rs2_data + cin;
+
+endmodule // zzadd48
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// This adder is primarily used in the multiplier.
+// The cin to out path is optimized.
+
+module zzadd34c ( rs1_data, rs2_data, cin, adder_out );
+
+ input [33:0] rs1_data;
+ input [33:0] rs2_data;
+ input cin;
+
+ output [33:0] adder_out;
+
+ assign adder_out = rs1_data + rs2_data + cin;
+
+
+endmodule // zzadd34c
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+module zzadd32 ( rs1_data, rs2_data, cin, adder_out, cout );
+
+ input [31:0] rs1_data; // 1st input operand
+ input [31:0] rs2_data; // 2nd input operand
+ input cin; // carry in
+
+ output [31:0] adder_out; // result of adder
+ output cout; // carry out
+
+ assign {cout, adder_out} = rs1_data + rs2_data + cin;
+
+endmodule // zzadd32
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+module zzadd18 ( rs1_data, rs2_data, cin, adder_out, cout );
+
+ input [17:0] rs1_data; // 1st input operand
+ input [17:0] rs2_data; // 2nd input operand
+ input cin; // carry in
+
+ output [17:0] adder_out; // result of adder
+ output cout; // carry out
+
+ assign {cout, adder_out} = rs1_data + rs2_data + cin;
+
+endmodule // zzadd18
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+module zzadd8 ( rs1_data, rs2_data, cin, adder_out, cout );
+
+ input [7:0] rs1_data; // 1st input operand
+ input [7:0] rs2_data; // 2nd input operand
+ input cin; // carry in
+
+ output [7:0] adder_out; // result of add & decrement
+ output cout; // carry out
+
+ assign {cout, adder_out} = rs1_data + rs2_data + cin;
+
+endmodule // zzadd8
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Special 4-operand 32b adder used in spu_shamd5
+// Description: This block implements the 4-operand 32-bit adder for SPU
+// It takes four 32-bit operands. It add them together and
+// output the 32-bit results to adder_out. The overflow of
+// 32th bit and higher will be ignored.
+
+module zzadd32op4 ( rs1_data, rs2_data, rs3_data, rs4_data, adder_out );
+
+ input [31:0] rs1_data; // 1st input operand
+ input [31:0] rs2_data; // 2nd input operand
+ input [31:0] rs3_data; // 3rd input operand
+ input [31:0] rs4_data; // 4th input operand
+
+ output [31:0] adder_out; // result of add
+
+ assign adder_out = rs1_data + rs2_data + rs3_data + rs4_data;
+
+endmodule // zzadd32op4
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Description: This block implements the adder for the sparc alu.
+// It takes two operands and a carry bit. It adds them together
+// and sends the output to adder_out. It outputs the overflow
+// and carry condition codes for both 64 bit and 32 bit operations.
+
+module zzadd64 ( rs1_data, rs2_data, cin, adder_out, cout32, cout64 );
+
+ input [63:0] rs1_data; // 1st input operand
+ input [63:0] rs2_data; // 2nd input operand
+ input cin; // carry in
+
+ output [63:0] adder_out; // result of adder
+ output cout32; // carry out from lower 32 bit add
+ output cout64; // carry out from 64 bit add
+
+ assign {cout32, adder_out[31:0]} = rs1_data[31:0] + rs2_data[31:0] + cin;
+ assign {cout64, adder_out[63:32]} = rs1_data[63:32] + rs2_data[63:32] + cout32;
+
+endmodule // zzadd64
+
+
+
+///////////////////////////////////////////////////////////////////////
+/*
+// Description: This is the ffu VIS adder. It can do either
+// 2 16 bit adds or 1 32 bit add.
+*/
+
+module zzadd32v (/*AUTOARG*/
+ // Outputs
+ z,
+ // Inputs
+ a, b, cin, add32
+ ) ;
+ input [31:0] a;
+ input [31:0] b;
+ input cin;
+ input add32;
+
+ output [31:0] z;
+
+ wire cout15; // carry out from lower 16 bit add
+ wire cin16; // carry in to the upper 16 bit add
+ wire cout31; // carry out from the upper 16 bit add
+
+ assign cin16 = (add32)? cout15: cin;
+
+ assign {cout15, z[15:0]} = a[15:0]+b[15:0]+ cin;
+ assign {cout31, z[31:16]} = a[31:16]+b[31:16]+ cin16;
+
+endmodule // zzadd32v
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 64-bit incrementer
+
+module zzinc64 ( in, out );
+
+ input [63:0] in;
+
+ output [63:0] out; // result of increment
+
+ assign out = in + 1'b1;
+
+endmodule // zzinc64
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 48-bit incrementer
+
+module zzinc48 ( in, out, overflow );
+
+ input [47:0] in;
+
+ output [47:0] out; // result of increment
+ output overflow; // overflow
+
+ assign out = in + 1'b1;
+ assign overflow = ~in[47] & out[47];
+
+endmodule // zzinc48
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 32-bit incrementer
+
+module zzinc32 ( in, out );
+
+ input [31:0] in;
+
+ output [31:0] out; // result of increment
+
+ assign out = in + 1'b1;
+
+endmodule // zzinc32
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+module zzecc_exu_chkecc2 ( q,ce, ue, ne, d, p, vld );
+ input [63:0] d;
+ input [7:0] p;
+ input vld;
+ output [6:0] q;
+ output ce,
+ ue,
+ ne;
+
+ wire parity;
+
+ assign ce = vld & parity;
+
+ assign ue = vld & ~parity & (q[6] | q[5] | q[4] | q[3] | q[2] | q[1] | q[0]);
+
+ assign ne = ~vld | ~(parity | q[6] | q[5] | q[4] | q[3] | q[2] | q[1] | q[0]);
+
+
+ assign q[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8] ^ d[10]
+ ^ d[11] ^ d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23]
+ ^ d[25] ^ d[26] ^ d[28] ^ d[30] ^ d[32] ^ d[34] ^ d[36]
+ ^ d[38] ^ d[40] ^ d[42] ^ d[44] ^ d[46] ^ d[48] ^ d[50]
+ ^ d[52] ^ d[54] ^ d[56] ^ d[57] ^ d[59] ^ d[61] ^ d[63]
+ ^ p[0] ;
+
+ assign q[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[9] ^ d[10]
+ ^ d[12] ^ d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24]
+ ^ d[25] ^ d[27] ^ d[28] ^ d[31] ^ d[32] ^ d[35] ^ d[36]
+ ^ d[39] ^ d[40] ^ d[43] ^ d[44] ^ d[47] ^ d[48] ^ d[51]
+ ^ d[52] ^ d[55] ^ d[56] ^ d[58] ^ d[59] ^ d[62] ^ d[63]
+ ^ p[1] ;
+
+ assign q[2] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
+ ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[22] ^ d[23] ^ d[24]
+ ^ d[25] ^ d[29] ^ d[30] ^ d[31] ^ d[32] ^ d[37] ^ d[38]
+ ^ d[39] ^ d[40] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[53]
+ ^ d[54] ^ d[55] ^ d[56] ^ d[60] ^ d[61] ^ d[62] ^ d[63]
+ ^ p[2] ;
+
+ assign q[3] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
+ ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24]
+ ^ d[25] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38]
+ ^ d[39] ^ d[40] ^ d[49] ^ d[50] ^ d[51] ^ d[52] ^ d[53]
+ ^ d[54] ^ d[55] ^ d[56] ^ p[3] ;
+
+ assign q[4] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17]
+ ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24]
+ ^ d[25] ^ d[41] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46]
+ ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[52] ^ d[53]
+ ^ d[54] ^ d[55] ^ d[56] ^ p[4] ;
+
+ assign q[5] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^ d[32]
+ ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] ^ d[39]
+ ^ d[40] ^ d[41] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46]
+ ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[52] ^ d[53]
+ ^ d[54] ^ d[55] ^ d[56] ^ p[5] ;
+
+ assign q[6] = d[57] ^ d[58] ^ d[59] ^ d[60] ^ d[61] ^ d[62] ^ d[63] ^ p[6] ;
+
+ assign parity = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]
+ ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15]
+ ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23]
+ ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31]
+ ^ d[32] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] ^ d[39]
+ ^ d[40] ^ d[41] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47]
+ ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[52] ^ d[53] ^ d[54] ^ d[55]
+ ^ d[56] ^ d[57] ^ d[58] ^ d[59] ^ d[60] ^ d[61] ^ d[62] ^ d[63]
+ ^ p[0] ^ p[1] ^ p[2] ^ p[3] ^ p[4] ^ p[5] ^ p[6] ^ p[7];
+
+endmodule // zzecc_exu_chkecc2
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+module zzecc_sctag_24b_gen ( din, dout, parity ) ;
+
+// Input Ports
+input [23:0] din ;
+
+// Output Ports
+output [23:0] dout ;
+output [5:0] parity ;
+
+wire [23:0] dout ;
+wire [5:0] parity ;
+
+// Local Reg and Wires
+wire p1 ;
+wire p2 ;
+wire p4 ;
+wire p8 ;
+wire p16 ;
+wire p30 ;
+
+
+//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+// |1 |2 |3 |4 |5 |6 |7 |8 |9 |10|11|12|13|14|15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |
+// |P1|P2|D0|P4|D1|D2|D3|P8|D4|D5|D6|D7|D8|D9|D10|P16|D11|D12|D13|D14|D15|D16|D17|D18|D19|D20|D21|D22|D23|P30|
+//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+//P1 | | |* | |* | |* | |* | |* | |* | | * | | * | | * | | * | | * | | * | | * | | * | |
+//P2 | | |* | | |* |* | | |* |* | | |* | * | | | * | * | | | * | * | | | * | * | | | |
+//P4 | | | | |* |* |* | | | | |* |* |* | * | | | | | * | * | * | * | | | | | * | * | |
+//P8 | | | | | | | | |* |* |* |* |* |* | * | | | | | | | | | * | * | * | * | * | * | |
+//P16 | | | | | | | | | | | | | | | | | * | * | * | * | * | * | * | * | * | * | * | * | * | |
+//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+//p30 | | |* | |* |* | | |* |* | |* | | | * | | * | * | | * | | | * | * | | | * | | * | |
+//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+
+
+assign p1 = din[0] ^ din[1] ^ din[3] ^ din[4] ^ din[6] ^ din[8] ^
+ din[10] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[19] ^
+ din[21] ^ din[23] ;
+
+assign p2 = din[0] ^ din[2] ^ din[3] ^ din[5] ^ din[6] ^ din[9] ^
+ din[10] ^ din[12] ^ din[13] ^ din[16] ^ din[17] ^ din[20] ^
+ din[21] ;
+
+assign p4 = din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[8] ^ din[9] ^
+ din[10] ^ din[14] ^ din[15] ^ din[16] ^ din[17] ^ din[22] ^
+ din[23] ;
+
+assign p8 = din[4] ^ din[5] ^ din[6] ^ din[7] ^ din[8] ^ din[9] ^
+ din[10] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^
+ din[23] ;
+
+assign p16 = din[11] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
+ din[17] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^
+ din[23] ;
+
+assign p30 = din[0] ^ din[1] ^ din[2] ^ din[4] ^ din[5] ^
+ din[7] ^ din[10] ^ din[11] ^ din[12] ^ din[14] ^
+ din[17] ^ din[18] ^ din[21] ^ din[23] ;
+
+assign dout = din ;
+assign parity = {p30, p16, p8, p4, p2, p1} ;
+
+endmodule
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+module zzecc_sctag_30b_cor ( din, parity, dout, corrected_bit ) ;
+
+// Input Ports
+input [23:0] din ;
+input [4:0] parity ;
+
+// Output Ports
+output [23:0] dout ;
+output [4:0] corrected_bit ;
+
+wire [23:0] dout ;
+wire [4:0] corrected_bit ;
+
+// Local Reg and Wires
+wire p1 ;
+wire p2 ;
+wire p4 ;
+wire p8 ;
+wire p16 ;
+wire [23:0] error_bit ;
+
+
+//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+// |1 |2 |3 |4 |5 |6 |7 |8 |9 |10|11|12|13|14|15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |
+// |P1|P2|D0|P4|D1|D2|D3|P8|D4|D5|D6|D7|D8|D9|D10|P16|D11|D12|D13|D14|D15|D16|D17|D18|D19|D20|D21|D22|D23|P30|
+//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+//P1 |* | |* | |* | |* | |* | |* | |* | | * | | * | | * | | * | | * | | * | | * | | * | |
+//P2 | |* |* | | |* |* | | |* |* | | |* | * | | | * | * | | | * | * | | | * | * | | | |
+//P4 | | | |* |* |* |* | | | | |* |* |* | * | | | | | * | * | * | * | | | | | * | * | |
+//P8 | | | | | | | |* |* |* |* |* |* |* | * | | | | | | | | | * | * | * | * | * | * | |
+//P16 | | | | | | | | | | | | | | | | * | * | * | * | * | * | * | * | * | * | * | * | * | * | |
+//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+//p30 |* |* |* |* |* |* |* |* |* |* |* |* |* |* | * | * | * | * | * | * | * | * | * | * | * | * | * | * | * | * |
+//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+
+
+assign p1 = parity[0] ^
+ din[0] ^ din[1] ^ din[3] ^ din[4] ^ din[6] ^ din[8] ^
+ din[10] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[19] ^
+ din[21] ^ din[23] ;
+
+assign p2 = parity[1] ^
+ din[0] ^ din[2] ^ din[3] ^ din[5] ^ din[6] ^ din[9] ^
+ din[10] ^ din[12] ^ din[13] ^ din[16] ^ din[17] ^ din[20] ^
+ din[21] ;
+
+assign p4 = parity[2] ^
+ din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[8] ^ din[9] ^
+ din[10] ^ din[14] ^ din[15] ^ din[16] ^ din[17] ^ din[22] ^
+ din[23] ;
+
+assign p8 = parity[3] ^
+ din[4] ^ din[5] ^ din[6] ^ din[7] ^ din[8] ^ din[9] ^
+ din[10] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^
+ din[23] ;
+
+assign p16 = parity[4] ^
+ din[11] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
+ din[17] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^
+ din[23] ;
+
+assign error_bit[0] = !p16 & !p8 & !p4 & p2 & p1 ; // 3
+assign error_bit[1] = !p16 & !p8 & p4 & !p2 & p1 ; // 5
+assign error_bit[2] = !p16 & !p8 & p4 & p2 & !p1 ; // 6
+assign error_bit[3] = !p16 & !p8 & p4 & p2 & p1 ; // 7
+assign error_bit[4] = !p16 & p8 & !p4 & !p2 & p1 ; // 9
+assign error_bit[5] = !p16 & p8 & !p4 & p2 & !p1 ; // 10
+assign error_bit[6] = !p16 & p8 & !p4 & p2 & p1 ; // 11
+assign error_bit[7] = !p16 & p8 & p4 & !p2 & !p1 ; // 12
+assign error_bit[8] = !p16 & p8 & p4 & !p2 & p1 ; // 13
+assign error_bit[9] = !p16 & p8 & p4 & p2 & !p1 ; // 14
+assign error_bit[10] = !p16 & p8 & p4 & p2 & p1 ; // 15
+assign error_bit[11] = p16 & !p8 & !p4 & !p2 & p1 ; // 17
+assign error_bit[12] = p16 & !p8 & !p4 & p2 & !p1 ; // 18
+assign error_bit[13] = p16 & !p8 & !p4 & p2 & p1 ; // 19
+assign error_bit[14] = p16 & !p8 & p4 & !p2 & !p1 ; // 20
+assign error_bit[15] = p16 & !p8 & p4 & !p2 & p1 ; // 21
+assign error_bit[16] = p16 & !p8 & p4 & p2 & !p1 ; // 22
+assign error_bit[17] = p16 & !p8 & p4 & p2 & p1 ; // 23
+assign error_bit[18] = p16 & p8 & !p4 & !p2 & !p1 ; // 24
+assign error_bit[19] = p16 & p8 & !p4 & !p2 & p1 ; // 25
+assign error_bit[20] = p16 & p8 & !p4 & p2 & !p1 ; // 26
+assign error_bit[21] = p16 & p8 & !p4 & p2 & p1 ; // 27
+assign error_bit[22] = p16 & p8 & p4 & !p2 & !p1 ; // 28
+assign error_bit[23] = p16 & p8 & p4 & !p2 & p1 ; // 29
+
+assign dout = din ^ error_bit ;
+assign corrected_bit = {p16, p8, p4, p2, p1} ;
+
+endmodule
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+//Module Name: zzecc_sctag_ecc39
+//Function: Error Detection and Correction
+//
+//
+
+module zzecc_sctag_ecc39 ( dout, cflag, pflag, parity, din);
+
+ //Output: 32bit corrected data
+ output[31:0] dout;
+ output [5:0] cflag;
+ output pflag;
+
+ //Input: 32bit data din
+ input [31:0] din;
+ input [6:0] parity;
+
+ wire c0,c1,c2,c3,c4,c5;
+ wire [31:0] err_bit_pos;
+
+ //refer to the comments in parity_gen_32b.v for the position description
+
+ assign c0= parity[0]^(din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8])
+ ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19])
+ ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]);
+
+ assign c1= parity[1]^(din[0]^din[2])^(din[3]^din[5])^(din[6]^din[9])
+ ^(din[10]^din[12])^(din[13]^din[16])^(din[17]^din[20])
+ ^(din[21]^din[24])^(din[25]^din[27])^(din[28]^din[31]);
+
+ assign c2= parity[2]^(din[1]^din[2])^(din[3]^din[7])^(din[8]^din[9])
+ ^(din[10]^din[14])^(din[15]^din[16])^(din[17]^din[22])
+ ^(din[23]^din[24])^(din[25]^din[29])^(din[30]^din[31]);
+
+ assign c3= parity[3]^(din[4]^din[5])^(din[6]^din[7])^(din[8]^din[9])
+ ^(din[10]^din[18])^(din[19]^din[20])^(din[21]^din[22])
+ ^(din[23]^din[24])^din[25];
+
+ assign c4= parity[4]^(din[11]^din[12])^(din[13]^din[14])^
+ (din[15]^din[16])^(din[17]^din[18])^(din[19]^din[20])^
+ (din[21]^din[22])^(din[23]^din[24])^din[25];
+
+ assign c5= parity[5]^(din[26]^din[27])^(din[28]^din[29])^
+ (din[30]^din[31]);
+
+ //generate total parity flag
+ assign pflag= c0 ^
+ (( (((parity[1]^parity[2])^(parity[3]^parity[4])) ^
+ ((parity[5]^parity[6])^(din[2]^din[5]))) ^
+ (((din[7]^din[9])^(din[12]^din[14])) ^
+ ((din[16]^din[18])^(din[20]^din[22]))) ) ^
+ ((din[24]^din[27])^(din[29]^din[31])) );
+
+ assign cflag= {c5,c4,c3,c2,c1,c0};
+
+ //6 to 32 decoder
+ assign err_bit_pos[0] = (c0)&(c1)&(~c2)&(~c3)&(~c4)&(~c5);
+ assign err_bit_pos[1] = (c0)&(~c1)&(c2)&(~c3)&(~c4)&(~c5);
+ assign err_bit_pos[2] = (~c0)&(c1)&(c2)&(~c3)&(~c4)&(~c5);
+ assign err_bit_pos[3] = (c0)&(c1)&(c2)&(~c3)&(~c4)&(~c5);
+ assign err_bit_pos[4] = (c0)&(~c1)&(~c2)&(c3)&(~c4)&(~c5);
+ assign err_bit_pos[5] = (~c0)&(c1)&(~c2)&(c3)&(~c4)&(~c5);
+ assign err_bit_pos[6] = (c0)&(c1)&(~c2)&(c3)&(~c4)&(~c5);
+ assign err_bit_pos[7] = (~c0)&(~c1)&(c2)&(c3)&(~c4)&(~c5);
+ assign err_bit_pos[8] = (c0)&(~c1)&(c2)&(c3)&(~c4)&(~c5);
+ assign err_bit_pos[9] = (~c0)&(c1)&(c2)&(c3)&(~c4)&(~c5);
+ assign err_bit_pos[10] = (c0)&(c1)&(c2)&(c3)&(~c4)&(~c5);
+ assign err_bit_pos[11] = (c0)&(~c1)&(~c2)&(~c3)&(c4)&(~c5);
+ assign err_bit_pos[12] = (~c0)&(c1)&(~c2)&(~c3)&(c4)&(~c5);
+ assign err_bit_pos[13] = (c0)&(c1)&(~c2)&(~c3)&(c4)&(~c5);
+ assign err_bit_pos[14] = (~c0)&(~c1)&(c2)&(~c3)&(c4)&(~c5);
+ assign err_bit_pos[15] = (c0)&(~c1)&(c2)&(~c3)&(c4)&(~c5);
+ assign err_bit_pos[16] = (~c0)&(c1)&(c2)&(~c3)&(c4)&(~c5);
+ assign err_bit_pos[17] = (c0)&(c1)&(c2)&(~c3)&(c4)&(~c5);
+ assign err_bit_pos[18] = (~c0)&(~c1)&(~c2)&(c3)&(c4)&(~c5);
+ assign err_bit_pos[19] = (c0)&(~c1)&(~c2)&(c3)&(c4)&(~c5);
+ assign err_bit_pos[20] = (~c0)&(c1)&(~c2)&(c3)&(c4)&(~c5);
+ assign err_bit_pos[21] = (c0)&(c1)&(~c2)&(c3)&(c4)&(~c5);
+ assign err_bit_pos[22] = (~c0)&(~c1)&(c2)&(c3)&(c4)&(~c5);
+ assign err_bit_pos[23] = (c0)&(~c1)&(c2)&(c3)&(c4)&(~c5);
+ assign err_bit_pos[24] = (~c0)&(c1)&(c2)&(c3)&(c4)&(~c5);
+ assign err_bit_pos[25] = (c0)&(c1)&(c2)&(c3)&(c4)&(~c5);
+ assign err_bit_pos[26] = (c0)&(~c1)&(~c2)&(~c3)&(~c4)&(c5);
+ assign err_bit_pos[27] = (~c0)&(c1)&(~c2)&(~c3)&(~c4)&(c5);
+ assign err_bit_pos[28] = (c0)&(c1)&(~c2)&(~c3)&(~c4)&(c5);
+ assign err_bit_pos[29] = (~c0)&(~c1)&(c2)&(~c3)&(~c4)&(c5);
+ assign err_bit_pos[30] = (c0)&(~c1)&(c2)&(~c3)&(~c4)&(c5);
+ assign err_bit_pos[31] = (~c0)&(c1)&(c2)&(~c3)&(~c4)&(c5);
+
+ //correct the error bit, it can only correct one error bit.
+
+ assign dout = din ^ err_bit_pos;
+
+endmodule // zzecc_sctag_ecc39
+
+
+////////////////////////////////////////////////////////////////////////////////
+//Module Name: zzecc_sctag_pgen_32b
+//Function: Generate 7 parity bits for 32bits input data
+//
+
+module zzecc_sctag_pgen_32b ( dout, parity, din);
+
+ //Output: 32bit dout and 7bit parity bit
+ output[31:0] dout;
+ output [6:0] parity;
+
+ //Input: 32bit data din
+ input [31:0] din;
+
+ //input data passing through this module
+ assign dout = din ;
+
+ //generate parity bits based on the hamming codes
+ //the method to generate parity bit is shown as follows
+ //1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
+ //P1 P2 d0 P4 d1 d2 d3 P8 d4 d5 d6 d7 d8 d9 d10 P16 d11 d12 d13
+ //
+ // 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
+ //d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 P32 d26 d27 d28
+ //
+ // 36 37 38
+ //d29 d30 d31
+ //For binary numbers B1-B2-B3-B4-B5-B6:
+ //B1=1 for (1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,...)
+ //B2=1 for (2,3,6,7,10,11,14,15,18,19,22,23,26,27,30,31,34,35,38,39...)
+ //B3=1 for (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31,36,37,38,39....)
+ //B4=1 for (8,9,10,11,12,13,14,15,24,25,26,27,28,29,30,31,40,41,42,....)
+ //B5=1 for (16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,48,49,...)
+ //B6=1 for (32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49...)
+ //Parity bit P1,P2,P4,P8,P16,P32 can be generated from the above group of
+ //bits B1=1,B2=1,B3=1,B4=1,B5=1,B6=1 respectively.
+
+ //use parity[5:0] to stand for P1,P2,P4,P8,P16,P32
+ assign parity[0] = (din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8])
+ ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19])
+ ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]);
+ //
+ assign parity[1] = (din[0]^din[2])^(din[3]^din[5])^(din[6]^din[9])
+ ^(din[10]^din[12])^(din[13]^din[16])^(din[17]^din[20])
+ ^(din[21]^din[24])^(din[25]^din[27])^(din[28]^din[31]);
+ //
+ assign parity[2] = (din[1]^din[2])^(din[3]^din[7])^(din[8]^din[9])
+ ^(din[10]^din[14])^(din[15]^din[16])^(din[17]^din[22])
+ ^(din[23]^din[24])^(din[25]^din[29])^(din[30]^din[31]);
+ //
+ assign parity[3] = (din[4]^din[5])^(din[6]^din[7])^(din[8]^din[9])
+ ^(din[10]^din[18])^(din[19]^din[20])^(din[21]^din[22])
+ ^(din[23]^din[24])^din[25];
+ //
+ assign parity[4] = (din[11]^din[12])^(din[13]^din[14])^(din[15]^din[16])
+ ^(din[17]^din[18])^(din[19]^din[20])^(din[21]^din[22])
+ ^(din[23]^din[24])^din[25];
+ //
+ assign parity[5] = (din[26]^din[27])^(din[28]^din[29])^(din[30]^din[31]);
+
+ //the last parity bit is the xor of all 38bits
+ //assign parity[6] = (^din)^(^parity[5:0]);
+ //it can be further simplified as:
+ //din= d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
+ //p0 = x x x x x x x x x x
+ //p1 = x x x x x x x x x
+ //p2 = x x x x x x x x x
+ //p3 = x x x x x x x
+ //p4 = x x x x x
+ //p5 =
+ //-------------------------------------------------------------------
+ //Total 3 3 3 4 3 3 4 3 4 4 5 3 3 4 3 4
+ //
+ //din=d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31
+ //p0= x x x x x x x x
+ //p1= x x x x x x x x x
+ //p2= x x x x x x x x x
+ //p3= x x x x x x x x
+ //p4= x x x x x x x x x x
+ //p5= x x x x x x
+ //-------------------------------------------------------------------
+ //total 4 5 3 4 4 5 4 5 5 6 3 3 4 3 4 4
+
+ //so total=even number, the corresponding bit will not show up in the
+ //final xor tree.
+ assign parity[6] = din[0] ^ din[1] ^ din[2] ^ din[4] ^ din[5] ^ din[7]
+ ^ din[10] ^ din[11] ^ din[12] ^ din[14] ^ din[17]
+ ^ din[18] ^ din[21] ^ din[23] ^ din[24] ^ din[26]
+ ^ din[27] ^ din[29];
+
+endmodule // zzecc_sctag_pgen_32b
+
+////////////////////////////////////////////////////////////////////////////////
+// 34 bit parity tree
+
+module zzpar34 ( z, d );
+ input [33:0] d;
+ output z;
+
+ assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]
+ ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15]
+ ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23]
+ ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31]
+ ^ d[32] ^ d[33];
+
+endmodule // zzpar34
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 32 bit parity tree
+
+module zzpar32 ( z, d );
+ input [31:0] d;
+ output z;
+
+ assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]
+ ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15]
+ ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23]
+ ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
+
+endmodule // zzpar32
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 28 bit parity tree
+
+module zzpar28 ( z, d );
+ input [27:0] d;
+ output z;
+
+ assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]
+ ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15]
+ ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23]
+ ^ d[24] ^ d[25] ^ d[26] ^ d[27];
+
+endmodule // zzpar28
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 16 bit parity tree
+
+module zzpar16 ( z, d );
+ input [15:0] d;
+ output z;
+
+ assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]
+ ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15];
+
+endmodule // zzpar16
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 8 bit parity tree
+
+module zzpar8 ( z, d );
+ input [7:0] d;
+ output z;
+
+ assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7];
+
+endmodule // zzpar8
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// 64 -> 6 priority encoder
+// Bit 63 has the highest priority
+
+module zzpenc64 (/*AUTOARG*/
+ // Outputs
+ z,
+ // Inputs
+ a
+ );
+
+ input [63:0] a;
+ output [5:0] z;
+
+ integer i;
+ reg [5:0] z;
+
+ always @ (a)
+ begin
+ z = 6'b0;
+ for (i=0;i<64;i=i+1)
+ if (a[i])
+ z = i;
+ end
+
+endmodule // zzpenc64
+
+////////////////////////////////////////////////////////////////////////////////
+// 4-bit 60x buffers
+
+module zzbufh_60x4 (/*AUTOARG*/
+ // Outputs
+ z,
+ // Inputs
+ a
+ );
+
+ input [3:0] a;
+ output [3:0] z;
+
+ assign z = a;
+
+endmodule //zzbufh_60x4
+
+// LVT modules added below
+
+module zzadd64_lv ( rs1_data, rs2_data, cin, adder_out, cout32, cout64 );
+
+ input [63:0] rs1_data; // 1st input operand
+ input [63:0] rs2_data; // 2nd input operand
+ input cin; // carry in
+
+ output [63:0] adder_out; // result of adder
+ output cout32; // carry out from lower 32 bit add
+ output cout64; // carry out from 64 bit add
+
+ assign {cout32, adder_out[31:0]} = rs1_data[31:0] + rs2_data[31:0] + cin;
+ assign {cout64, adder_out[63:32]} = rs1_data[63:32] + rs2_data[63:32] + cout32;
+
+endmodule // zzadd64_lv
+
+module zzpar8_lv ( z, d );
+ input [7:0] d;
+ output z;
+
+ assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7];
+
+endmodule // zzpar8_lv
+
+
+module zzpar32_lv ( z, d );
+ input [31:0] d;
+ output z;
+
+ assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]
+ ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15]
+ ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23]
+ ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
+
+endmodule // zzpar32_lv
+
+
+
+module zznor64_32_lv ( znor64, znor32, a );
+ input [63:0] a;
+ output znor64;
+ output znor32;
+
+ assign znor32 = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]
+ | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]
+ | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]);
+
+ assign znor64 = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]
+ | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]
+ | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]
+ | a[32] | a[33] | a[34] | a[35] | a[36] | a[37] | a[38] | a[39]
+ | a[40] | a[41] | a[42] | a[43] | a[44] | a[45] | a[46] | a[47]
+ | a[48] | a[49] | a[50] | a[51] | a[52] | a[53] | a[54] | a[55]
+ | a[56] | a[57] | a[58] | a[59] | a[60] | a[61] | a[62] | a[63]);
+
+endmodule // zznor64_32_lv
+
+////////////////////////////////////////////////////////////////////////////////
+// 64 -> 6 priority encoder
+// Bit 63 has the highest priority
+// LVT version
+
+module zzpenc64_lv (/*AUTOARG*/
+ // Outputs
+ z,
+ // Inputs
+ a
+ );
+
+ input [63:0] a;
+ output [5:0] z;
+
+ integer i;
+ reg [5:0] z;
+
+ always @ (a)
+ begin
+ z = 6'b0;
+ for (i=0;i<64;i=i+1)
+ if (a[i])
+ z = i;
+ end
+
+endmodule // zzpenc64_lv
+
+////////////////////////////////////////////////////////////////////////////////
+// 36 bit or gate
+// LVT version
+
+module zzor36_lv ( z, a );
+ input [35:0] a;
+ output z;
+
+ assign z = (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]
+ | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]
+ | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]
+ | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]
+ | a[32] | a[33] | a[34] | a[35]);
+
+endmodule // zzor36_lv
+
+////////////////////////////////////////////////////////////////////////////////
+// 34 bit parity tree
+// LVT version
+
+module zzpar34_lv ( z, d );
+ input [33:0] d;
+ output z;
+
+ assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]
+ ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15]
+ ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23]
+ ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31]
+ ^ d[32] ^ d[33];
+
+endmodule // zzpar34_lv
+
+