Subversion Repositories s1_core

/spc2wbm.v

spc2wbm.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: s1_top.v =================================================================== --- s1_top.v (nonexistent) +++ s1_top.v (revision 105) @@ -0,0 +1,325 @@ +/* + * Simply RISC S1 Core Top-Level + * + * (C) 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * This block implements the top-level of the S1 Core. + * It is just a schematic with four instances: + * 1) one single SPARC Core of the OpenSPARC T1; + * 2) a SPARC Core to Wishbone Master bridge; + * 3) a Reset Controller; + * 4) an Interrupt Controller. + * + */ + +`include "s1_defs.h" + +module s1_top ( + sys_clock_i, sys_reset_i, sys_irq_i, + wbm_ack_i, wbm_data_i, + wbm_cycle_o, wbm_strobe_o, wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o + ); + + /* + * Inputs + */ + + // System inputs + input sys_clock_i; // System Clock + input sys_reset_i; // System Reset + input[63:0] sys_irq_i; // Interrupt Requests + + // Wishbone Interconnect Master Interface inputs + input wbm_ack_i; // Ack + input[(`WB_DATA_WIDTH-1):0] wbm_data_i; // Data In + + /* + * Outputs + */ + + // Wishbone Interconnect Master Interface outputs + output wbm_cycle_o; // Cycle Start + output wbm_strobe_o; // Strobe Request + output wbm_we_o; // Write Enable + output[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus + output[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out + output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output + + /* + * Wires + */ + + // Wires connected to SPARC Core outputs + + // pcx + wire [4:0] spc_pcx_req_pq; // processor to pcx request + wire spc_pcx_atom_pq; // processor to pcx atomic request + wire [`PCX_WIDTH-1:0] spc_pcx_data_pa; // processor to pcx packet + + // shadow scan + wire spc_sscan_so; // From ifu of sparc_ifu.v + wire spc_scanout0; // From test_stub of test_stub_bist.v + wire spc_scanout1; // From test_stub of test_stub_bist.v + + // bist + wire tst_ctu_mbist_done; // From test_stub of test_stub_two_bist.v + wire tst_ctu_mbist_fail; // From test_stub of test_stub_two_bist.v + + // fuse + wire spc_efc_ifuse_data; // From ifu of sparc_ifu.v + wire spc_efc_dfuse_data; // From ifu of sparc_ifu.v + + // Wires connected to SPARC Core inputs + + // cpx interface + wire [4:0] pcx_spc_grant_px; // pcx to processor grant info + wire cpx_spc_data_rdy_cx2; // cpx data inflight to sparc + wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet + wire wbm_spc_stall; // Stall requests + wire wbm_spc_resume; // Resume requests + + wire [3:0] const_cpuid; + wire [7:0] const_maskid; // To ifu of sparc_ifu.v + + // sscan + wire ctu_tck; // To ifu of sparc_ifu.v + wire ctu_sscan_se; // To ifu of sparc_ifu.v + wire ctu_sscan_snap; // To ifu of sparc_ifu.v + wire [3:0] ctu_sscan_tid; // To ifu of sparc_ifu.v + + // bist + wire ctu_tst_mbist_enable; // To test_stub of test_stub_bist.v + + // efuse + wire efc_spc_fuse_clk1; + wire efc_spc_fuse_clk2; + wire efc_spc_ifuse_ashift; + wire efc_spc_ifuse_dshift; + wire efc_spc_ifuse_data; + wire efc_spc_dfuse_ashift; + wire efc_spc_dfuse_dshift; + wire efc_spc_dfuse_data; + + // scan and macro test + wire ctu_tst_macrotest; // To test_stub of test_stub_bist.v + wire ctu_tst_scan_disable; // To test_stub of test_stub_bist.v + wire ctu_tst_short_chain; // To test_stub of test_stub_bist.v + wire global_shift_enable; // To test_stub of test_stub_two_bist.v + wire ctu_tst_scanmode; // To test_stub of test_stub_two_bist.v + wire spc_scanin0; + wire spc_scanin1; + + // clk + wire cluster_cken; // To spc_hdr of cluster_header.v + wire gclk; // To spc_hdr of cluster_header.v + + // reset + wire cmp_grst_l; + wire cmp_arst_l; + wire ctu_tst_pre_grst_l; // To test_stub of test_stub_bist.v + + wire adbginit_l; // To spc_hdr of cluster_header.v + wire gdbginit_l; // To spc_hdr of cluster_header.v + + // Reset signal from the reset controller to the bridge + wire sys_reset_final; + + // Interrupt Source from the interrupt controller to the bridge + wire[5:0] sys_interrupt_source; + + /* + * SPARC Core module instance + */ + + sparc sparc_0 ( + + // Wires connected to SPARC Core outputs + .spc_pcx_req_pq(spc_pcx_req_pq), + .spc_pcx_atom_pq(spc_pcx_atom_pq), + .spc_pcx_data_pa(spc_pcx_data_pa), + .spc_sscan_so(spc_sscan_so), + .spc_scanout0(spc_scanout0), + .spc_scanout1(spc_scanout1), + .tst_ctu_mbist_done(tst_ctu_mbist_done), + .tst_ctu_mbist_fail(tst_ctu_mbist_fail), + .spc_efc_ifuse_data(spc_efc_ifuse_data), + .spc_efc_dfuse_data(spc_efc_dfuse_data), + + // Wires connected to SPARC Core inputs + .pcx_spc_grant_px(pcx_spc_grant_px), + .cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2), + .cpx_spc_data_cx2(cpx_spc_data_cx2), + .wbm_spc_stall(wbm_spc_stall), + .wbm_spc_resume(wbm_spc_resume), + .const_cpuid(const_cpuid), + .const_maskid(const_maskid), + .ctu_tck(ctu_tck), + .ctu_sscan_se(ctu_sscan_se), + .ctu_sscan_snap(ctu_sscan_snap), + .ctu_sscan_tid(ctu_sscan_tid), + .ctu_tst_mbist_enable(ctu_tst_mbist_enable), + .efc_spc_fuse_clk1(efc_spc_fuse_clk1), + .efc_spc_fuse_clk2(efc_spc_fuse_clk2), + .efc_spc_ifuse_ashift(efc_spc_ifuse_ashift), + .efc_spc_ifuse_dshift(efc_spc_ifuse_dshift), + .efc_spc_ifuse_data(efc_spc_ifuse_data), + .efc_spc_dfuse_ashift(efc_spc_dfuse_ashift), + .efc_spc_dfuse_dshift(efc_spc_dfuse_dshift), + .efc_spc_dfuse_data(efc_spc_dfuse_data), + .ctu_tst_macrotest(ctu_tst_macrotest), + .ctu_tst_scan_disable(ctu_tst_scan_disable), + .ctu_tst_short_chain(ctu_tst_short_chain), + .global_shift_enable(global_shift_enable), + .ctu_tst_scanmode(ctu_tst_scanmode), + .spc_scanin0(spc_scanin0), + .spc_scanin1(spc_scanin1), + .cluster_cken(cluster_cken), + .gclk(gclk), + .cmp_grst_l(cmp_grst_l), + .cmp_arst_l(cmp_arst_l), + .ctu_tst_pre_grst_l(ctu_tst_pre_grst_l), + .adbginit_l(adbginit_l), + .gdbginit_l(gdbginit_l) + + ); + + /* + * SPARC Core to Wishbone Master bridge + */ + + spc2wbm spc2wbm_0 ( + + // Top-level system inputs + .sys_clock_i(sys_clock_i), + .sys_reset_i(sys_reset_final), + .sys_interrupt_source_i(sys_interrupt_source), + + // Bridge inputs connected to SPARC Core outputs + .spc_req_i(spc_pcx_req_pq), + .spc_atom_i(spc_pcx_atom_pq), + .spc_packetout_i(spc_pcx_data_pa), + + // Bridge outputs connected to SPARC Core inputs + .spc_grant_o(pcx_spc_grant_px), + .spc_ready_o(cpx_spc_data_rdy_cx2), + .spc_packetin_o(cpx_spc_data_cx2), + .spc_stall_o(wbm_spc_stall), + .spc_resume_o(wbm_spc_resume), + + // Top-level Wishbone Interconnect inputs + .wbm_ack_i(wbm_ack_i), + .wbm_data_i(wbm_data_i), + + // Top-level Wishbone Interconnect outputs + .wbm_cycle_o(wbm_cycle_o), + .wbm_strobe_o(wbm_strobe_o), + .wbm_we_o(wbm_we_o), + .wbm_addr_o(wbm_addr_o), + .wbm_data_o(wbm_data_o), + .wbm_sel_o(wbm_sel_o) + + ); + + /* + * Reset Controller + */ + + rst_ctrl rst_ctrl_0 ( + + // Top-level system inputs + .sys_clock_i(sys_clock_i), + .sys_reset_i(sys_reset_i), + + // Reset Controller outputs connected to SPARC Core inputs + .cluster_cken_o(cluster_cken), + .gclk_o(gclk), + .cmp_grst_o(cmp_grst_l), + .cmp_arst_o(cmp_arst_l), + .ctu_tst_pre_grst_o(ctu_tst_pre_grst_l), + .adbginit_o(adbginit_l), + .gdbginit_o(gdbginit_l), + .sys_reset_final_o(sys_reset_final) + + ); + + /* + * Interrupt Controller + */ + + int_ctrl int_ctrl_0 ( + + // Top-level system inputs + .sys_clock_i(sys_clock_i), + .sys_reset_i(sys_reset_final), + .sys_irq_i(sys_irq_i), + + // Interrupt Controller outputs connected to bridge inputs + .sys_interrupt_source_o(sys_interrupt_source) + + ); + + /* + * Continuous assignments + */ + + assign const_cpuid = 4'h0; + assign const_maskid = 8'h20; + + // sscan + assign ctu_tck = 1'b0; + assign ctu_sscan_se = 1'b0; + assign ctu_sscan_snap = 1'b0; + assign ctu_sscan_tid = 4'h1; + + // bist + assign ctu_tst_mbist_enable = 1'b0; + + // efuse + assign efc_spc_fuse_clk1 = 1'b0; // Activity + assign efc_spc_fuse_clk2 = 1'b0; // Activity + assign efc_spc_ifuse_ashift = 1'b0; + assign efc_spc_ifuse_dshift = 1'b0; + assign efc_spc_ifuse_data = 1'b0; // Activity + assign efc_spc_dfuse_ashift = 1'b0; + assign efc_spc_dfuse_dshift = 1'b0; + assign efc_spc_dfuse_data = 1'b0; // Activity + + // scan and macro test + assign ctu_tst_macrotest = 1'b0; + assign ctu_tst_scan_disable = 1'b0; + assign ctu_tst_short_chain = 1'b0; + assign global_shift_enable = 1'b0; + assign ctu_tst_scanmode = 1'b0; + assign spc_scanin0 = 1'b0; + assign spc_scanin1 = 1'b0; + + /* + + The following signals are handled by the Reset Controller: + + // clk + assign cluster_cken = ...; + assign gclk = ...; + + // reset + assign cmp_grst_l = ...; + assign cmp_arst_l = ...; + assign ctu_tst_pre_grst_l = ...; + + assign adbginit_l = ...; + assign gdbginit_l = ...; + + */ + +endmodule

s1_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: s1_defs.h =================================================================== --- s1_defs.h (nonexistent) +++ s1_defs.h (revision 105) @@ -0,0 +1,52 @@ +/* + * Simply RISC S1 Definitions + * + * (C) Copyleft 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * Simple constant definitions used by the S1 Core design. + */ + +`include "t1_defs.h" +`timescale 1ns/100ps + +`define FPGA_SYN +`define FPGA_SYN_1THREAD +`define FPGA_SYN_NO_SPU + +// Size of the buses +`define WB_ADDR_WIDTH 64 +`define WB_DATA_WIDTH 64 + +// States of the FSM of the bridge +`define STATE_WAKEUP 4'b0000 +`define STATE_IDLE 4'b0001 +`define STATE_REQUEST_LATCHED 4'b0010 +`define STATE_PACKET_LATCHED 4'b0011 +`define STATE_REQUEST_GRANTED 4'b0100 +`define STATE_ACCESS2_BEGIN 4'b0101 +`define STATE_ACCESS2_END 4'b0110 +`define STATE_ACCESS3_BEGIN 4'b0111 +`define STATE_ACCESS3_END 4'b1000 +`define STATE_ACCESS4_BEGIN 4'b1001 +`define STATE_ACCESS4_END 4'b1010 +`define STATE_PACKET_READY 4'b1011 + +// Constants used by the timer of the Reset Controller +`define TIMER_BITS 16 +`define RESET_CYCLES_1 100 +`define RESET_CYCLES_2 1000 +`define RESET_CYCLES_3 2000 +`define RESET_CYCLES_4 3000 +`define GCLK_CYCLES 900 +

s1_defs.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rst_ctrl.v =================================================================== --- rst_ctrl.v (nonexistent) +++ rst_ctrl.v (revision 105) @@ -0,0 +1,166 @@ +/* + * Reset Controller + * + * (C) Copyleft 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * This block implements the Reset Controller used by the S1 Core + * to wake up the SPARC Core of the OpenSPARC T1; its behavior was + * reverse-engineered from the OpenSPARC waveforms. + */ + +`include "s1_defs.h" + +module rst_ctrl ( + sys_clock_i, sys_reset_i, + cluster_cken_o, gclk_o, cmp_grst_o, cmp_arst_o, + ctu_tst_pre_grst_o, adbginit_o, gdbginit_o, + sys_reset_final_o + ); + + /* + * Inputs + */ + + // System inputs + input sys_clock_i; // System Clock + input sys_reset_i; // System Reset + + /* + * Registered Outputs + */ + + output gclk_o; + + /* + * Registered Outputs + */ + + // SPARC Core inputs + output cluster_cken_o; + reg cluster_cken_o; + output cmp_grst_o; + reg cmp_grst_o; + output cmp_arst_o; + reg cmp_arst_o; + output ctu_tst_pre_grst_o; + reg ctu_tst_pre_grst_o; + output adbginit_o; + reg adbginit_o; + output gdbginit_o; + reg gdbginit_o; + output sys_reset_final_o; + reg sys_reset_final_o; + + /* + * Registers + */ + + // Counter used as a timer to strobe the reset signals + reg[`TIMER_BITS-1:0] cycle_counter; + + /* + * Procedural blocks + */ + + // This process handles the timer counter + always @(posedge sys_clock_i) + begin + if(sys_reset_i==1'b1) + begin + cycle_counter = 0; + end + else + begin + if(cycle_counter[`TIMER_BITS-1]==1'b0) + begin + cycle_counter = cycle_counter+1; + end + end + end + + // This other process assigns the proper values to the outputs + // (that are used as system inputs by the SPARC Core) + always @(posedge sys_clock_i) + begin + if(sys_reset_i==1) + begin + cluster_cken_o <= 0; + cmp_grst_o <= 0; + cmp_arst_o <= 0; + ctu_tst_pre_grst_o <= 0; + adbginit_o <= 0; + gdbginit_o <= 0; + sys_reset_final_o <= 1; + end + else + begin + if(cycle_counter<`RESET_CYCLES_1) + begin + cluster_cken_o <= 0; + cmp_grst_o <= 0; + cmp_arst_o <= 0; + ctu_tst_pre_grst_o <= 0; + adbginit_o <= 0; + gdbginit_o <= 0; + sys_reset_final_o <= 1; + end + else + if(cycle_counter<`RESET_CYCLES_2) + begin + cluster_cken_o <= 0; + cmp_grst_o <= 0; + cmp_arst_o <= 1; // <-- + ctu_tst_pre_grst_o <= 0; + adbginit_o <= 1; // <-- + gdbginit_o <= 0; + sys_reset_final_o <= 1; + end + else + if(cycle_counter<`RESET_CYCLES_3) + begin + cluster_cken_o <= 1; // <-- + cmp_grst_o <= 0; + cmp_arst_o <= 1; + ctu_tst_pre_grst_o <= 1; // <-- + adbginit_o <= 1; + gdbginit_o <= 0; + sys_reset_final_o <= 1; + end + else + if(cycle_counter<`RESET_CYCLES_4) + begin + cluster_cken_o <= 1; + cmp_grst_o <= 1; // <-- + cmp_arst_o <= 1; + ctu_tst_pre_grst_o <= 1; + adbginit_o <= 1; + gdbginit_o <= 1; // <-- + sys_reset_final_o <= 1; + end + else + begin + cluster_cken_o <= 1; + cmp_grst_o <= 1; + cmp_arst_o <= 1; + ctu_tst_pre_grst_o <= 1; + adbginit_o <= 1; + gdbginit_o <= 1; + sys_reset_final_o <= 0; // <-- + end + end + end + + assign gclk_o = (cycle_counter>`GCLK_CYCLES) & sys_clock_i; + +endmodule

rst_ctrl.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: int_ctrl.v =================================================================== --- int_ctrl.v (nonexistent) +++ int_ctrl.v (revision 105) @@ -0,0 +1,114 @@ +/* + * Interrupt Controller + * + * (C) 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * This block implements the Interrupt Controller used by the S1 + * to detect if some peripheral raised an interrupt request. + * A proper interrupt packet is sent to the SPARC Core by the + * bridge with one of the 64 interrupt sources (provided by this + * controller) encoded in the 6-bit Interrupt Source field. + * Please note that IRQ 0 is reserved for Power-On Reset (handled + * directly by the bridge) so up to 63 external peripherals can be + * connected to the S1. + * Note also that currently the interrupt vector is hardwired to + * all zeroes. + */ + +module int_ctrl ( + sys_clock_i, sys_reset_i, sys_irq_i, + sys_interrupt_source_o + ); + + // System inputs + input sys_clock_i; + input sys_reset_i; + + // Incoming Interrupt Requests + input[63:0] sys_irq_i; + + // Encoded Interrupt Source + output[5:0] sys_interrupt_source_o; + reg[5:0] sys_interrupt_source_o; + + // Encoding of the source using priority and ignoring IRQ 0 + always @(posedge sys_clock_i) begin + if(sys_reset_i==1) sys_interrupt_source_o = 0; + else if(sys_irq_i[63]) sys_interrupt_source_o = 63; + else if(sys_irq_i[62]) sys_interrupt_source_o = 62; + else if(sys_irq_i[61]) sys_interrupt_source_o = 61; + else if(sys_irq_i[60]) sys_interrupt_source_o = 60; + else if(sys_irq_i[59]) sys_interrupt_source_o = 59; + else if(sys_irq_i[58]) sys_interrupt_source_o = 58; + else if(sys_irq_i[57]) sys_interrupt_source_o = 57; + else if(sys_irq_i[56]) sys_interrupt_source_o = 56; + else if(sys_irq_i[55]) sys_interrupt_source_o = 55; + else if(sys_irq_i[54]) sys_interrupt_source_o = 54; + else if(sys_irq_i[53]) sys_interrupt_source_o = 53; + else if(sys_irq_i[52]) sys_interrupt_source_o = 52; + else if(sys_irq_i[51]) sys_interrupt_source_o = 51; + else if(sys_irq_i[50]) sys_interrupt_source_o = 50; + else if(sys_irq_i[49]) sys_interrupt_source_o = 49; + else if(sys_irq_i[48]) sys_interrupt_source_o = 48; + else if(sys_irq_i[47]) sys_interrupt_source_o = 47; + else if(sys_irq_i[46]) sys_interrupt_source_o = 46; + else if(sys_irq_i[45]) sys_interrupt_source_o = 45; + else if(sys_irq_i[44]) sys_interrupt_source_o = 44; + else if(sys_irq_i[43]) sys_interrupt_source_o = 43; + else if(sys_irq_i[42]) sys_interrupt_source_o = 42; + else if(sys_irq_i[41]) sys_interrupt_source_o = 41; + else if(sys_irq_i[40]) sys_interrupt_source_o = 40; + else if(sys_irq_i[39]) sys_interrupt_source_o = 39; + else if(sys_irq_i[38]) sys_interrupt_source_o = 38; + else if(sys_irq_i[37]) sys_interrupt_source_o = 37; + else if(sys_irq_i[36]) sys_interrupt_source_o = 36; + else if(sys_irq_i[35]) sys_interrupt_source_o = 35; + else if(sys_irq_i[34]) sys_interrupt_source_o = 34; + else if(sys_irq_i[33]) sys_interrupt_source_o = 33; + else if(sys_irq_i[32]) sys_interrupt_source_o = 32; + else if(sys_irq_i[31]) sys_interrupt_source_o = 31; + else if(sys_irq_i[30]) sys_interrupt_source_o = 30; + else if(sys_irq_i[29]) sys_interrupt_source_o = 29; + else if(sys_irq_i[28]) sys_interrupt_source_o = 28; + else if(sys_irq_i[27]) sys_interrupt_source_o = 27; + else if(sys_irq_i[26]) sys_interrupt_source_o = 26; + else if(sys_irq_i[25]) sys_interrupt_source_o = 25; + else if(sys_irq_i[24]) sys_interrupt_source_o = 24; + else if(sys_irq_i[23]) sys_interrupt_source_o = 23; + else if(sys_irq_i[22]) sys_interrupt_source_o = 22; + else if(sys_irq_i[21]) sys_interrupt_source_o = 21; + else if(sys_irq_i[20]) sys_interrupt_source_o = 20; + else if(sys_irq_i[19]) sys_interrupt_source_o = 19; + else if(sys_irq_i[18]) sys_interrupt_source_o = 18; + else if(sys_irq_i[17]) sys_interrupt_source_o = 17; + else if(sys_irq_i[16]) sys_interrupt_source_o = 16; + else if(sys_irq_i[15]) sys_interrupt_source_o = 15; + else if(sys_irq_i[14]) sys_interrupt_source_o = 14; + else if(sys_irq_i[13]) sys_interrupt_source_o = 13; + else if(sys_irq_i[12]) sys_interrupt_source_o = 12; + else if(sys_irq_i[11]) sys_interrupt_source_o = 11; + else if(sys_irq_i[10]) sys_interrupt_source_o = 10; + else if(sys_irq_i[9]) sys_interrupt_source_o = 9; + else if(sys_irq_i[8]) sys_interrupt_source_o = 8; + else if(sys_irq_i[7]) sys_interrupt_source_o = 7; + else if(sys_irq_i[6]) sys_interrupt_source_o = 6; + else if(sys_irq_i[5]) sys_interrupt_source_o = 5; + else if(sys_irq_i[4]) sys_interrupt_source_o = 4; + else if(sys_irq_i[3]) sys_interrupt_source_o = 3; + else if(sys_irq_i[2]) sys_interrupt_source_o = 2; + else if(sys_irq_i[1]) sys_interrupt_source_o = 1; + else sys_interrupt_source_o = 0; + end + +endmodule

int_ctrl.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: t1_defs.h =================================================================== --- t1_defs.h (nonexistent) +++ t1_defs.h (revision 105) @@ -0,0 +1,839 @@ +/* +* ========== Copyright Header Begin ========================================== +* +* OpenSPARC T1 Processor File: iop.h +* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +* +* The above named program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public +* License version 2 as published by the Free Software Foundation. +* +* The above named program is distributed in the hope that it will be +* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +* +* You should have received a copy of the GNU General Public +* License along with this work; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +* +* ========== Copyright Header End ============================================ +*/ +//-*- verilog -*- +//////////////////////////////////////////////////////////////////////// +/* +// +// Description: Global header file that contain definitions that +// are common/shared at the IOP chip level +*/ +//////////////////////////////////////////////////////////////////////// + + +// Address Map Defines +// =================== +`define ADDR_MAP_HI 39 +`define ADDR_MAP_LO 32 +`define IO_ADDR_BIT 39 + +// CMP space +`define DRAM_DATA_LO 8'h00 +`define DRAM_DATA_HI 8'h7f + +// IOP space +`define JBUS1 8'h80 +`define RESERVED_5 8'h81 //`define HASH_TBL_NRAM_CSR 8'h81 +`define RESERVED_1 8'h82 +`define RESERVED_6_LO 8'h83 //`define ENET_MAC_CSR 8'h83 + //`define ENET_ING_CSR 8'h84 + //`define ENET_EGR_CMD_CSR 8'h85 +`define RESERVED_6_HI 8'h86 //`define ENET_EGR_DP_CSR 8'h86 +`define RESERVED_2_LO 8'h87 +`define RESERVED_2_HI 8'h92 +`define RESERVED_7 8'h93 //`define BSC_CSR 8'h93 +`define RESERVED_3 8'h94 +`define RESERVED_8 8'h95 //`define RAND_GEN_CSR 8'h95 +`define CLOCK_UNIT_CSR 8'h96 +`define DRAM_CSR 8'h97 +`define IOB_MAN_CSR 8'h98 +`define TAP_CSR 8'h99 +`define RESERVED_4_L0 8'h9a +`define RESERVED_4_HI 8'h9d +`define CPU_ASI 8'h9e +`define IOB_INT_CSR 8'h9f + +// L2 space +`define L2C_CSR_LO 8'ha0 +`define L2C_CSR_HI 8'hbf + +// More IOP space +`define JBUS2_LO 8'hc0 +`define JBUS2_HI 8'hfe +`define SPI_CSR 8'hff + + +//Cache Crossbar Width and Field Defines +//====================================== +`define PCX_WIDTH 124 //PCX payload packet width +`define CPX_WIDTH 145 //CPX payload packet width + +`define PCX_VLD 123 //PCX packet valid +`define PCX_RQ_HI 122 //PCX request type field +`define PCX_RQ_LO 118 +`define PCX_NC 117 //PCX non-cacheable bit +`define PCX_R 117 //PCX read/!write bit +`define PCX_CP_HI 116 //PCX cpu_id field +`define PCX_CP_LO 114 +`define PCX_TH_HI 113 //PCX Thread field +`define PCX_TH_LO 112 +`define PCX_BF_HI 111 //PCX buffer id field +`define PCX_INVALL 111 +`define PCX_BF_LO 109 +`define PCX_WY_HI 108 //PCX replaced L1 way field +`define PCX_WY_LO 107 +`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01 +`define PCX_P_LO 107 +`define PCX_SZ_HI 106 //PCX load/store size field +`define PCX_SZ_LO 104 +`define PCX_ERR_HI 106 //PCX error field +`define PCX_ERR_LO 104 +`define PCX_AD_HI 103 //PCX address field +`define PCX_AD_LO 64 +`define PCX_DA_HI 63 //PCX Store data +`define PCX_DA_LO 0 + +`define PCX_SZ_1B 3'b000 // encoding for 1B access +`define PCX_SZ_2B 3'b001 // encoding for 2B access +`define PCX_SZ_4B 3'b010 // encoding for 4B access +`define PCX_SZ_8B 3'b011 // encoding for 8B access +`define PCX_SZ_16B 3'b111 // encoding for 16B access + +`define CPX_VLD 144 //CPX payload packet valid + +`define CPX_RQ_HI 143 //CPX Request type +`define CPX_RQ_LO 140 +`define CPX_ERR_HI 139 //CPX error field +`define CPX_ERR_LO 137 +`define CPX_NC 136 //CPX non-cacheable +`define CPX_R 136 //CPX read/!write bit +`define CPX_TH_HI 135 //CPX thread ID field +`define CPX_TH_LO 134 + +//bits 133:128 are shared by different fields +//for different packet types. + +`define CPX_IN_HI 133 //CPX Interrupt source +`define CPX_IN_LO 128 + +`define CPX_WYVLD 133 //CPX replaced way valid +`define CPX_WY_HI 132 //CPX replaced I$/D$ way +`define CPX_WY_LO 131 +`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits +`define CPX_BF_LO 128 + +`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits +`define CPX_SI_LO 128 //used for invalidates + +`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01 +`define CPX_P_LO 130 + +`define CPX_ASI 130 //CPX forward request to ASI +`define CPX_IF4B 130 +`define CPX_IINV 124 +`define CPX_DINV 123 +`define CPX_INVPA5 122 +`define CPX_INVPA4 121 +`define CPX_CPUID_HI 120 +`define CPX_CPUID_LO 118 +`define CPX_INV_PA_HI 116 +`define CPX_INV_PA_LO 112 +`define CPX_INV_IDX_HI 117 +`define CPX_INV_IDX_LO 112 + +`define CPX_DA_HI 127 //CPX data payload +`define CPX_DA_LO 0 + +`define LOAD_RQ 5'b00000 +`define IMISS_RQ 5'b10000 +`define STORE_RQ 5'b00001 +`define CAS1_RQ 5'b00010 +`define CAS2_RQ 5'b00011 +`define SWAP_RQ 5'b00110 +`define STRLOAD_RQ 5'b00100 +`define STRST_RQ 5'b00101 +`define STQ_RQ 5'b00111 +`define INT_RQ 5'b01001 +`define FWD_RQ 5'b01101 +`define FWD_RPY 5'b01110 +`define RSVD_RQ 5'b11111 + +`define LOAD_RET 4'b0000 +`define INV_RET 4'b0011 +`define ST_ACK 4'b0100 +`define AT_ACK 4'b0011 +`define INT_RET 4'b0111 +`define TEST_RET 4'b0101 +`define FP_RET 4'b1000 +`define IFILL_RET 4'b0001 +`define EVICT_REQ 4'b0011 +`define ERR_RET 4'b1100 +`define STRLOAD_RET 4'b0010 +`define STRST_ACK 4'b0110 +`define FWD_RQ_RET 4'b1010 +`define FWD_RPY_RET 4'b1011 +`define RSVD_RET 4'b1111 + +//End cache crossbar defines + + +// Number of COS supported by EECU +`define EECU_COS_NUM 2 + + +// +// BSC bus sizes +// ============= +// + +// General +`define BSC_ADDRESS 40 +`define MAX_XFER_LEN 7'b0 +`define XFER_LEN_WIDTH 6 + +// CTags +`define BSC_CTAG_SZ 12 +`define EICU_CTAG_PRE 5'b11101 +`define EICU_CTAG_REM 7 +`define EIPU_CTAG_PRE 3'b011 +`define EIPU_CTAG_REM 9 +`define EECU_CTAG_PRE 8'b11010000 +`define EECU_CTAG_REM 4 +`define EEPU_CTAG_PRE 6'b010000 +`define EEPU_CTAG_REM 6 +`define L2C_CTAG_PRE 2'b00 +`define L2C_CTAG_REM 10 +`define JBI_CTAG_PRE 2'b10 +`define JBI_CTAG_REM 10 +// reinstated temporarily +`define PCI_CTAG_PRE 7'b1101100 +`define PCI_CTAG_REM 5 + + +// CoS +`define EICU_COS 1'b0 +`define EIPU_COS 1'b1 +`define EECU_COS 1'b0 +`define EEPU_COS 1'b1 +`define PCI_COS 1'b0 + +// L2$ Bank +`define BSC_L2_BNK_HI 8 +`define BSC_L2_BNK_LO 6 + +// L2$ Req +`define BSC_L2_REQ_SZ 62 +`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code +`define BSC_L2_BUS 64 +`define BSC_L2_CTAG_HI 61 +`define BSC_L2_CTAG_LO 50 +`define BSC_L2_ADD_HI 49 +`define BSC_L2_ADD_LO 10 +`define BSC_L2_LEN_HI 9 +`define BSC_L2_LEN_LO 3 +`define BSC_L2_ALLOC 2 +`define BSC_L2_COS 1 +`define BSC_L2_READ 0 + +// L2$ Ack +`define L2_BSC_ACK_SZ 16 +`define L2_BSC_BUS 64 +`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address +`define L2_BSC_CBA_LO 13 +`define L2_BSC_READ 12 +`define L2_BSC_CTAG_HI 11 +`define L2_BSC_CTAG_LO 0 + +// Enet Egress Command Unit +`define EECU_REQ_BUS 44 +`define EECU_REQ_SZ 44 +`define EECU_R_QID_HI 43 +`define EECU_R_QID_LO 40 +`define EECU_R_ADD_HI 39 +`define EECU_R_ADD_LO 0 + +`define EECU_ACK_BUS 64 +`define EECU_ACK_SZ 5 +`define EECU_A_NACK 4 +`define EECU_A_QID_HI 3 +`define EECU_A_QID_LO 0 + + +// Enet Egress Packet Unit +`define EEPU_REQ_BUS 55 +`define EEPU_REQ_SZ 55 +`define EEPU_R_TLEN_HI 54 +`define EEPU_R_TLEN_LO 48 +`define EEPU_R_SOF 47 +`define EEPU_R_EOF 46 +`define EEPU_R_PORT_HI 45 +`define EEPU_R_PORT_LO 44 +`define EEPU_R_QID_HI 43 +`define EEPU_R_QID_LO 40 +`define EEPU_R_ADD_HI 39 +`define EEPU_R_ADD_LO 0 + +// This is cleaved in between Egress Datapath Ack's +`define EEPU_ACK_BUS 6 +`define EEPU_ACK_SZ 6 +`define EEPU_A_EOF 5 +`define EEPU_A_NACK 4 +`define EEPU_A_QID_HI 3 +`define EEPU_A_QID_LO 0 + + +// Enet Egress Datapath +`define EEDP_ACK_BUS 128 +`define EEDP_ACK_SZ 28 +`define EEDP_A_NACK 27 +`define EEDP_A_QID_HI 26 +`define EEDP_A_QID_LO 21 +`define EEDP_A_SOF 20 +`define EEDP_A_EOF 19 +`define EEDP_A_LEN_HI 18 +`define EEDP_A_LEN_LO 12 +`define EEDP_A_TAG_HI 11 +`define EEDP_A_TAG_LO 0 +`define EEDP_A_PORT_HI 5 +`define EEDP_A_PORT_LO 4 +`define EEDP_A_PORT_WIDTH 2 + + +// In-Order / Ordered Queue: EEPU +// Tag is: TLEN, SOF, EOF, QID = 15 +`define EEPU_TAG_ARY (7+1+1+6) +`define EEPU_ENTRIES 16 +`define EEPU_E_IDX 4 +`define EEPU_PORTS 4 +`define EEPU_P_IDX 2 + +// Nack + Tag Info + CTag +`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12) +`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX) + + +// ENET Ingress Queue Management Req +`define EICU_REQ_BUS 64 +`define EICU_REQ_SZ 62 +`define EICU_R_CTAG_HI 61 +`define EICU_R_CTAG_LO 50 +`define EICU_R_ADD_HI 49 +`define EICU_R_ADD_LO 10 +`define EICU_R_LEN_HI 9 +`define EICU_R_LEN_LO 3 +`define EICU_R_COS 1 +`define EICU_R_READ 0 + + +// ENET Ingress Queue Management Ack +`define EICU_ACK_BUS 64 +`define EICU_ACK_SZ 14 +`define EICU_A_NACK 13 +`define EICU_A_READ 12 +`define EICU_A_CTAG_HI 11 +`define EICU_A_CTAG_LO 0 + + +// Enet Ingress Packet Unit +`define EIPU_REQ_BUS 128 +`define EIPU_REQ_SZ 59 +`define EIPU_R_CTAG_HI 58 +`define EIPU_R_CTAG_LO 50 +`define EIPU_R_ADD_HI 49 +`define EIPU_R_ADD_LO 10 +`define EIPU_R_LEN_HI 9 +`define EIPU_R_LEN_LO 3 +`define EIPU_R_COS 1 +`define EIPU_R_READ 0 + + +// ENET Ingress Packet Unit Ack +`define EIPU_ACK_BUS 10 +`define EIPU_ACK_SZ 10 +`define EIPU_A_NACK 9 +`define EIPU_A_CTAG_HI 8 +`define EIPU_A_CTAG_LO 0 + + +// In-Order / Ordered Queue: PCI +// Tag is: CTAG +`define PCI_TAG_ARY 12 +`define PCI_ENTRIES 16 +`define PCI_E_IDX 4 +`define PCI_PORTS 2 + +// PCI-X Request +`define PCI_REQ_BUS 64 +`define PCI_REQ_SZ 62 +`define PCI_R_CTAG_HI 61 +`define PCI_R_CTAG_LO 50 +`define PCI_R_ADD_HI 49 +`define PCI_R_ADD_LO 10 +`define PCI_R_LEN_HI 9 +`define PCI_R_LEN_LO 3 +`define PCI_R_COS 1 +`define PCI_R_READ 0 + +// PCI_X Acknowledge +`define PCI_ACK_BUS 64 +`define PCI_ACK_SZ 14 +`define PCI_A_NACK 13 +`define PCI_A_READ 12 +`define PCI_A_CTAG_HI 11 +`define PCI_A_CTAG_LO 0 + + +`define BSC_MAX_REQ_SZ 62 + + +// +// BSC array sizes +//================ +// +`define BSC_REQ_ARY_INDEX 6 +`define BSC_REQ_ARY_DEPTH 64 +`define BSC_REQ_ARY_WIDTH 62 +`define BSC_REQ_NXT_WIDTH 12 +`define BSC_ACK_ARY_INDEX 6 +`define BSC_ACK_ARY_DEPTH 64 +`define BSC_ACK_ARY_WIDTH 14 +`define BSC_ACK_NXT_WIDTH 12 +`define BSC_PAY_ARY_INDEX 6 +`define BSC_PAY_ARY_DEPTH 64 +`define BSC_PAY_ARY_WIDTH 256 + +// ECC syndrome bits per memory element +`define BSC_PAY_ECC 10 +`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH) + + +// +// BSC Port Definitions +// ==================== +// +// Bits 7 to 4 of curr_port_id +`define BSC_PORT_NULL 4'h0 +`define BSC_PORT_SC 4'h1 +`define BSC_PORT_EICU 4'h2 +`define BSC_PORT_EIPU 4'h3 +`define BSC_PORT_EECU 4'h4 +`define BSC_PORT_EEPU 4'h8 +`define BSC_PORT_PCI 4'h9 + +// Number of ports of each type +`define BSC_PORT_SC_CNT 8 + +// Bits needed to represent above +`define BSC_PORT_SC_IDX 3 + +// How wide the linked list pointers are +// 60b for no payload (2CoS) +// 80b for payload (2CoS) + +//`define BSC_OBJ_PTR 80 +//`define BSC_HD1_HI 69 +//`define BSC_HD1_LO 60 +//`define BSC_TL1_HI 59 +//`define BSC_TL1_LO 50 +//`define BSC_CT1_HI 49 +//`define BSC_CT1_LO 40 +//`define BSC_HD0_HI 29 +//`define BSC_HD0_LO 20 +//`define BSC_TL0_HI 19 +//`define BSC_TL0_LO 10 +//`define BSC_CT0_HI 9 +//`define BSC_CT0_LO 0 + +`define BSC_OBJP_PTR 48 +`define BSC_PYP1_HI 47 +`define BSC_PYP1_LO 42 +`define BSC_HDP1_HI 41 +`define BSC_HDP1_LO 36 +`define BSC_TLP1_HI 35 +`define BSC_TLP1_LO 30 +`define BSC_CTP1_HI 29 +`define BSC_CTP1_LO 24 +`define BSC_PYP0_HI 23 +`define BSC_PYP0_LO 18 +`define BSC_HDP0_HI 17 +`define BSC_HDP0_LO 12 +`define BSC_TLP0_HI 11 +`define BSC_TLP0_LO 6 +`define BSC_CTP0_HI 5 +`define BSC_CTP0_LO 0 + +`define BSC_PTR_WIDTH 192 +`define BSC_PTR_REQ_HI 191 +`define BSC_PTR_REQ_LO 144 +`define BSC_PTR_REQP_HI 143 +`define BSC_PTR_REQP_LO 96 +`define BSC_PTR_ACK_HI 95 +`define BSC_PTR_ACK_LO 48 +`define BSC_PTR_ACKP_HI 47 +`define BSC_PTR_ACKP_LO 0 + +`define BSC_PORT_SC_PTR 96 // R, R+P +`define BSC_PORT_EECU_PTR 48 // A+P +`define BSC_PORT_EICU_PTR 96 // A, A+P +`define BSC_PORT_EIPU_PTR 48 // A + +// I2C STATES in DRAMctl +`define I2C_CMD_NOP 4'b0000 +`define I2C_CMD_START 4'b0001 +`define I2C_CMD_STOP 4'b0010 +`define I2C_CMD_WRITE 4'b0100 +`define I2C_CMD_READ 4'b1000 + + +// +// IOB defines +// =========== +// +`define IOB_ADDR_WIDTH 40 +`define IOB_LOCAL_ADDR_WIDTH 32 + +`define IOB_CPU_INDEX 3 +`define IOB_CPU_WIDTH 8 +`define IOB_THR_INDEX 2 +`define IOB_THR_WIDTH 4 +`define IOB_CPUTHR_INDEX 5 +`define IOB_CPUTHR_WIDTH 32 + +`define IOB_MONDO_DATA_INDEX 5 +`define IOB_MONDO_DATA_DEPTH 32 +`define IOB_MONDO_DATA_WIDTH 64 +`define IOB_MONDO_SRC_WIDTH 5 +`define IOB_MONDO_BUSY 5 + +`define IOB_INT_TAB_INDEX 2 +`define IOB_INT_TAB_DEPTH 4 + +//`define IOB_INT_STAT_WIDTH 32 +//`define IOB_INT_STAT_HI 31 +//`define IOB_INT_STAT_LO 0 + +`define IOB_INT_VEC_WIDTH 6 +`define IOB_INT_VEC_HI 5 +`define IOB_INT_VEC_LO 0 + +`define IOB_INT_CPU_WIDTH 5 +`define IOB_INT_CPU_HI 12 +`define IOB_INT_CPU_LO 8 + +`define IOB_INT_MASK 2 +`define IOB_INT_CLEAR 1 +`define IOB_INT_PEND 0 + +`define IOB_DISP_TYPE_HI 17 +`define IOB_DISP_TYPE_LO 16 +`define IOB_DISP_THR_HI 12 +`define IOB_DISP_THR_LO 8 +`define IOB_DISP_VEC_HI 5 +`define IOB_DISP_VEC_LO 0 + +`define IOB_JBI_RESET 1 +`define IOB_ENET_RESET 0 + +`define IOB_RESET_STAT_WIDTH 3 +`define IOB_RESET_STAT_HI 3 +`define IOB_RESET_STAT_LO 1 + +`define IOB_SERNUM_WIDTH 64 + +`define IOB_FUSE_WIDTH 22 + +`define IOB_TMSTAT_THERM 63 + +`define IOB_POR_TT 6'b01 // power-on-reset trap type + +`define IOB_CPU_BUF_INDEX 4 + +`define IOB_INT_BUF_INDEX 4 +`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width + +`define IOB_IO_BUF_INDEX 4 +`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width + +`define IOB_L2_VIS_BUF_INDEX 5 +`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width + +`define IOB_INT_AVEC_WIDTH 9 // availibility vector width +`define IOB_ACK_AVEC_WIDTH 9 // availibility vector width + +// fixme - double check address mapping +// CREG in `IOB_INT_CSR space +`define IOB_DEV_ADDR_MASK 32'hffffffe7 +`define IOB_CREG_INTSTAT 32'h00000000 +`define IOB_CREG_MDATA0 32'h00000400 +`define IOB_CREG_MDATA1 32'h00000500 +`define IOB_CREG_MBUSY 32'h00000900 +`define IOB_THR_ADDR_MASK 32'hffffff07 +`define IOB_CREG_MDATA0_ALIAS 32'h00000600 +`define IOB_CREG_MDATA1_ALIAS 32'h00000700 +`define IOB_CREG_MBUSY_ALIAS 32'h00000b00 + +// CREG in `IOB_MAN_CSR space +`define IOB_CREG_INTMAN 32'h00000000 +`define IOB_CREG_INTCTL 32'h00000400 +`define IOB_CREG_INTVECDISP 32'h00000800 +`define IOB_CREG_RESETSTAT 32'h00000810 +`define IOB_CREG_SERNUM 32'h00000820 +`define IOB_CREG_TMSTATCTRL 32'h00000828 +`define IOB_CREG_COREAVAIL 32'h00000830 +`define IOB_CREG_SSYSRESET 32'h00000838 +`define IOB_CREG_FUSESTAT 32'h00000840 +`define IOB_CREG_MARGIN 32'h00000850 +`define IOB_CREG_JINTV 32'h00000a00 + +`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800 +`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820 +`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828 +`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830 +`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838 +`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840 +`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000 +`define IOB_CREG_DBG_ENET_CTRL 32'h00002000 +`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008 +`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100 +`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140 +`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160 +`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148 +`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168 +`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150 +`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170 +`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180 +`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0 +`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188 +`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8 +`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190 +`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0 + +`define IOB_CREG_TESTSTUB 32'h80000000 + +// Address map for TAP access of SPARC ASI +`define IOB_ASI_PC 4'b0000 +`define IOB_ASI_BIST 4'b0001 +`define IOB_ASI_MARGIN 4'b0010 +`define IOB_ASI_DEFEATURE 4'b0011 +`define IOB_ASI_L1DD 4'b0100 +`define IOB_ASI_L1ID 4'b0101 +`define IOB_ASI_L1DT 4'b0110 + +`define IOB_INT 2'b00 +`define IOB_RESET 2'b01 +`define IOB_IDLE 2'b10 +`define IOB_RESUME 2'b11 + +// +// CIOP UCB Bus Width +// ================== +// +//`define IOB_EECU_WIDTH 16 // ethernet egress command +//`define EECU_IOB_WIDTH 16 + +//`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously) +//`define NRAM_IOB_WIDTH 4 + +`define IOB_JBI_WIDTH 64 // JBI +`define JBI_IOB_WIDTH 16 + +//`define IOB_ENET_ING_WIDTH 32 // ethernet ingress +//`define ENET_ING_IOB_WIDTH 8 + +//`define IOB_ENET_EGR_WIDTH 4 // ethernet egress +//`define ENET_EGR_IOB_WIDTH 4 + +//`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC +//`define ENET_MAC_IOB_WIDTH 4 + +`define IOB_DRAM_WIDTH 4 // DRAM controller +`define DRAM_IOB_WIDTH 4 + +//`define IOB_BSC_WIDTH 4 // BSC +//`define BSC_IOB_WIDTH 4 + +`define IOB_SPI_WIDTH 4 // SPI (Boot ROM) +`define SPI_IOB_WIDTH 4 + +`define IOB_CLK_WIDTH 4 // clk unit +`define CLK_IOB_WIDTH 4 + +//`define IOB_CLSP_WIDTH 4 // clk spine unit +//`define CLSP_IOB_WIDTH 4 + +`define IOB_TAP_WIDTH 8 // TAP +`define TAP_IOB_WIDTH 8 + + +// +// CIOP UCB Buf ID Type +// ==================== +// +`define UCB_BID_CMP 2'b00 +`define UCB_BID_TAP 2'b01 + +// +// Interrupt Device ID +// =================== +// +// Caution: DUMMY_DEV_ID has to be 9 bit wide +// for fields to line up properly in the IOB. +`define DUMMY_DEV_ID 9'h00 // 0 +`define UNCOR_ECC_DEV_ID 7'd1 // 1 + +// +// Soft Error related definitions +// ============================== +// +`define COR_ECC_CNT_WIDTH 16 + + +// +// CMP clock +// ========= +// + +`define CMP_CLK_PERIOD 1333 + + +// +// NRAM/IO Interface +// ================= +// + +`define DRAM_CLK_PERIOD 6000 + +`define NRAM_IO_DQ_WIDTH 32 +`define IO_NRAM_DQ_WIDTH 32 + +`define NRAM_IO_ADDR_WIDTH 15 +`define NRAM_IO_BA_WIDTH 2 + + +// +// NRAM/ENET Interface +// =================== +// + +`define NRAM_ENET_DATA_WIDTH 64 +`define ENET_NRAM_ADDR_WIDTH 20 + +`define NRAM_DBG_DATA_WIDTH 40 + + +// +// IO/FCRAM Interface +// ================== +// + +`define FCRAM_DATA1_HI 63 +`define FCRAM_DATA1_LO 32 +`define FCRAM_DATA0_HI 31 +`define FCRAM_DATA0_LO 0 + +// +// PCI Interface +// ================== +// Load/store size encodings +// ------------------------- +// Size encoding +// 000 - byte +// 001 - half-word +// 010 - word +// 011 - double-word +// 100 - quad +`define LDST_SZ_BYTE 3'b000 +`define LDST_SZ_HALF_WORD 3'b001 +`define LDST_SZ_WORD 3'b010 +`define LDST_SZ_DOUBLE_WORD 3'b011 +`define LDST_SZ_QUAD 3'b100 + +// +// JBI<->SCTAG Interface +// ======================= +// Outbound Header Format +`define JBI_BTU_OUT_ADDR_LO 0 +`define JBI_BTU_OUT_ADDR_HI 42 +`define JBI_BTU_OUT_RSV0_LO 43 +`define JBI_BTU_OUT_RSV0_HI 43 +`define JBI_BTU_OUT_TYPE_LO 44 +`define JBI_BTU_OUT_TYPE_HI 48 +`define JBI_BTU_OUT_RSV1_LO 49 +`define JBI_BTU_OUT_RSV1_HI 51 +`define JBI_BTU_OUT_REPLACE_LO 52 +`define JBI_BTU_OUT_REPLACE_HI 56 +`define JBI_BTU_OUT_RSV2_LO 57 +`define JBI_BTU_OUT_RSV2_HI 59 +`define JBI_BTU_OUT_BTU_ID_LO 60 +`define JBI_BTU_OUT_BTU_ID_HI 71 +`define JBI_BTU_OUT_DATA_RTN 72 +`define JBI_BTU_OUT_RSV3_LO 73 +`define JBI_BTU_OUT_RSV3_HI 75 +`define JBI_BTU_OUT_CE 76 +`define JBI_BTU_OUT_RSV4_LO 77 +`define JBI_BTU_OUT_RSV4_HI 79 +`define JBI_BTU_OUT_UE 80 +`define JBI_BTU_OUT_RSV5_LO 81 +`define JBI_BTU_OUT_RSV5_HI 83 +`define JBI_BTU_OUT_DRAM 84 +`define JBI_BTU_OUT_RSV6_LO 85 +`define JBI_BTU_OUT_RSV6_HI 127 + +// Inbound Header Format +`define JBI_SCTAG_IN_ADDR_LO 0 +`define JBI_SCTAG_IN_ADDR_HI 39 +`define JBI_SCTAG_IN_SZ_LO 40 +`define JBI_SCTAG_IN_SZ_HI 42 +`define JBI_SCTAG_IN_RSV0 43 +`define JBI_SCTAG_IN_TAG_LO 44 +`define JBI_SCTAG_IN_TAG_HI 55 +`define JBI_SCTAG_IN_REQ_LO 56 +`define JBI_SCTAG_IN_REQ_HI 58 +`define JBI_SCTAG_IN_POISON 59 +`define JBI_SCTAG_IN_RSV1_LO 60 +`define JBI_SCTAG_IN_RSV1_HI 63 + +`define JBI_SCTAG_REQ_WRI 3'b100 +`define JBI_SCTAG_REQ_WR8 3'b010 +`define JBI_SCTAG_REQ_RDD 3'b001 +`define JBI_SCTAG_REQ_WRI_BIT 2 +`define JBI_SCTAG_REQ_WR8_BIT 1 +`define JBI_SCTAG_REQ_RDD_BIT 0 + +// +// JBI->IOB Mondo Header Format +// ============================ +// +`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1 +`define JBI_IOB_MONDO_RSV1_LO 13 +`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target +`define JBI_IOB_MONDO_TRG_LO 8 +`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0 +`define JBI_IOB_MONDO_RSV0_LO 5 +`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source +`define JBI_IOB_MONDO_SRC_LO 0 + +`define JBI_IOB_MONDO_RSV1_WIDTH 3 +`define JBI_IOB_MONDO_TRG_WIDTH 5 +`define JBI_IOB_MONDO_RSV0_WIDTH 3 +`define JBI_IOB_MONDO_SRC_WIDTH 5 + +// JBI->IOB Mondo Bus Width/Cycle +// ============================== +// Cycle 1 Header[15:8] +// Cycle 2 Header[ 7:0] +// Cycle 3 J_AD[127:120] +// Cycle 4 J_AD[119:112] +// ..... +// Cycle 18 J_AD[ 7: 0] +`define JBI_IOB_MONDO_BUS_WIDTH 8 +`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data