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URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /s1_core/trunk/hdl
    from Rev 113 to Rev 114
    Reverse comparison

Rev 113 → Rev 114

/behav/testbench/mem_harness.v
1,8 → 1,7
/*
* Memory Harness with Wishbone Slave interface
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/behav/testbench/s1_defs.h
1,8 → 1,7
/*
* Simply RISC S1 Definitions
* S1 Definitions
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/behav/testbench/testbench.v
1,8 → 1,7
/*
* Simply RISC S1 Testbench
* S1 Testbench
*
* (C) 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
78,7 → 77,7
initial begin
 
// Display start message
$display("INFO: TBENCH: Starting Simply RISC S1 Core simulation...");
$display("INFO: TBENCH: Starting S1 Core simulation...");
 
// Create VCD trace file
$dumpfile("trace.vcd");
90,7 → 89,7
#1000
sys_reset <= 1'b0;
#49000
$display("INFO: TBENCH: Completed Simply RISC S1 Core simulation!");
$display("INFO: TBENCH: Completed S1 Core simulation!");
$finish;
 
end
99,7 → 98,7
* Module instances
*/
 
// Simply RISC S1 Core
// S1 Core
s1_top s1_top_0 (
 
// System inputs
/rtl/s1_top/cachedir.v
1,8 → 1,7
/*
* Simply RISC CacheDir
* CacheDir
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/rtl/s1_top/int_ctrl.v
1,8 → 1,7
/*
* Interrupt Controller
* S1 Interrupt Controller
*
* (C) 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/rtl/s1_top/os2wb.v
2,7 → 2,7
//////////////////////////////////////////////////////////////////////////////////
// Company: (C) Athree, 2009
// Engineer: Dmitry Rozhdestvenskiy
// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
// Email: dmitryr@a3.spb.ru divx4log@narod.ru
//
// Design Name: Bridge from SPARC Core to Wishbone Master
// Module Name: os2wb
/rtl/s1_top/pcx_fifo.v
1,8 → 1,7
/*
* Simply RISC PCX FIFO
* PCX FIFO
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/rtl/s1_top/rst_ctrl.v
1,8 → 1,7
/*
* Reset Controller
* S1 Reset Controller
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/rtl/s1_top/s1_defs.h
1,8 → 1,7
/*
* Simply RISC S1 Definitions
* S1 Definitions
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/rtl/s1_top/s1_top.v
1,8 → 1,7
/*
* Simply RISC S1 Core Top-Level
* S1 Core Top-Level
*
* (C) 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/rtl/s1_top/simple_fifo.v
1,8 → 1,7
/*
* Simply RISC Simple FIFO
* Simple FIFO
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/rtl/s1_top/spc2wbm.v
1,8 → 1,7
/*
* Bridge from SPARC Core to Wishbone Master
*
* (C) 2006-2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) 2006-2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or

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