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    /s1_core/trunk/tools/src
    from Rev 105 to Rev 113
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Rev 105 → Rev 113

/gtkwave.sav File deleted
/TRACAN.txt
0,0 → 1,52
Simply RISC S1 Core - Tracan (Trace Analyzer)
=============================================
 
This small tool has been written to convert the waveforms of the
original OpenSPARC T1 simulation environment into a format similar
to the one used in the "sim.log" file generated by the S1 simulations.
 
To have it working you have to:
- have a working OpenSPARC T1 simulation environment;
- modify the top-level testbench cmpt_top.v to add the
following lines:
 
initial begin
$dumpfile("trace.vcd");
$dumpvars(2);
end
 
- run the T1 simulations you want (give to the sims script
the argument to not delete the results);
- open the resulting trace.vcd file with a text editor and
look for lines similar to these ones:
 
$var wire 124 " spc_pcx_data_pa [123:0] $end
$var wire 145 $ cpx_spc_data_cx2 [144:0] $end
 
- if the chars after the numbers are different from the double
quote and the dollar sign shown above, then you have to change
the string used by the egrep command into the 'tracan' script;
for instance if the two chars are 'A' and 'B' the line will
become:
 
egrep ' A$| B$' $1 | egrep -v x | ./tracan.bin
 
- then you can finally run the program: if the binary file
tracan.bin does not exists it will be compiled with GCC;
- if everything goes right you will be able to use the command:
 
tracan.sh PATH_TO_YOUR_TRACE_VCD_FILE
 
and you will get the logfile on the console; a typical usage
would be:
 
tracan.sh trace.vcd > sim.log
 
- if you want to improve the script to automatically extract the
ASCII symbol used in the VCD file for outgoing and incoming
packets, please modify the tool and we'll be happy to mention
your name into this file!
- Enjoy!
 
The development team at Simply RISC LLP
 
/tracan.cpp
0,0 → 1,122
 
#include "tracan.h"
 
// Useful functions
void reverse_string(char *s) {
char t, *e = s + strlen(s);
while (--e > s) { t = *s;*s++=*e;*e=t; }
}
unsigned long long bitsToInt(char *bit_vector, int bit_pos_max, int bit_pos_min) {
unsigned long long value = 0;
unsigned int len = strlen(bit_vector);
if (bit_pos_min < 0 || bit_pos_min > bit_pos_max || bit_pos_max >= len) {
printf("*** ERROR *** Invalid substring boundaries MIN=%d MAX=%d LEN=%d", bit_pos_min, bit_pos_max, len);
exit(1);
}
for(unsigned long long i = 0; i <= bit_pos_max-bit_pos_min; i++) {
if (bit_vector[bit_pos_min+i]=='1')
value += (1ULL<<i);
}
return value;
}
 
// Print functions
void print_pcx_req(char *buf) {
if (!strcmp(buf, "10000")) printf("PCX_REQ RAM_DDR_0 ");
else if (!strcmp(buf, "01000")) printf("PCX_REQ RAM_DDR_1 ");
else if (!strcmp(buf, "00100")) printf("PCX_REQ RAM_DDR_2 ");
else if (!strcmp(buf, "00010")) printf("PCX_REQ RAM_DDR_3 ");
else if (!strcmp(buf, "00001")) printf("PCX_REQ ROM_IOBridge ");
else printf("PCX_REQ Unknown_%s ", buf);
}
void print_pcx_atom(char *buf) {
if (!strcmp(buf, "1"))
printf("ATOMIC_");
}
void print_pcx_data(char *buf) {
char str_type[20], str_size[20];
if (!bitsToInt(buf, PCX_VLD,PCX_VLD)) return;
switch(bitsToInt(buf, PCX_RQ_HI,PCX_RQ_LO)) {
case LOAD_RQ: strcpy(str_type, "LOAD_RQ"); break;
case IMISS_RQ: strcpy(str_type, "IMISS_RQ"); break;
case STORE_RQ: strcpy(str_type, "STORE_RQ"); break;
case CAS1_RQ: strcpy(str_type, "CAS1_RQ"); break;
case CAS2_RQ: strcpy(str_type, "CAS2_RQ"); break;
case SWAP_RQ: strcpy(str_type, "SWAP_RQ"); break;
case STRLOAD_RQ: strcpy(str_type, "STRLOAD_RQ"); break;
case STRST_RQ: strcpy(str_type, "STRST_RQ"); break;
case STQ_RQ: strcpy(str_type, "STQ_RQ"); break;
case INT_RQ: strcpy(str_type, "INT_RQ"); break;
case FWD_RQ: strcpy(str_type, "FWD_RQ"); break;
case FWD_RPY: strcpy(str_type, "FWD_RPY"); break;
case RSVD_RQ: strcpy(str_type, "RSVD_RQ"); break;
case ATOM_REQ_A: strcpy(str_type, "ATOM_REQ_A"); break; // Added by Simply RISC
case ATOM_REQ_B: strcpy(str_type, "ATOM_REQ_B"); break; // Added by Simply RISC
default: sprintf(str_type, "Unknown_0x%02llX", bitsToInt(buf, PCX_RQ_HI,PCX_RQ_LO));
}
switch(bitsToInt(buf, PCX_SZ_HI,PCX_SZ_LO)) {
case PCX_SZ_1B: strcpy(str_size, "1B"); break;
case PCX_SZ_2B: strcpy(str_size, "2B"); break;
case PCX_SZ_4B: strcpy(str_size, "4B"); break;
case PCX_SZ_8B: strcpy(str_size, "8B"); break;
case PCX_SZ_16B: strcpy(str_size, "16B"); break;
default: sprintf(str_size, "Unknown_0x%02llX", bitsToInt(buf, PCX_SZ_HI,PCX_SZ_LO));
}
printf("PCX_DATA Valid=%llu Type=%s NonCache_RnW=%llu PE=%llu.%llu Buffer=%llu L1Way_Packet=%llu Size=%s Address=0x%010llX Store_Data=0x%016llX\n",
bitsToInt(buf, PCX_VLD,PCX_VLD), str_type, bitsToInt(buf, PCX_R,PCX_R), bitsToInt(buf, PCX_CP_HI,PCX_CP_LO), bitsToInt(buf, PCX_TH_HI,PCX_TH_LO),
bitsToInt(buf, PCX_BF_HI,PCX_BF_LO), bitsToInt(buf, PCX_WY_HI,PCX_WY_LO), str_size,
bitsToInt(buf, PCX_AD_HI,PCX_AD_LO), bitsToInt(buf, PCX_DA_HI,PCX_DA_LO));
}
void print_pcx_grant(char *buf) {
if (!strcmp(buf, "10000")) printf("PCX_GRANT RAM_DDR_0\n");
else if (!strcmp(buf, "01000")) printf("PCX_GRANT RAM_DDR_1\n");
else if (!strcmp(buf, "00100")) printf("PCX_GRANT RAM_DDR_2\n");
else if (!strcmp(buf, "00010")) printf("PCX_GRANT RAM_DDR_3\n");
else if (!strcmp(buf, "00001")) printf("PCX_GRANT ROM_IOBridge\n");
else printf("PCX_GRANT Unknown_%s\n", buf);
}
void print_cpx_ready(char *buf) {
printf("CPX_READY %s\n", buf);
}
void print_cpx_data(char *buf) {
char str_type[20];
if (!bitsToInt(buf, CPX_VLD,CPX_VLD)) return;
switch(bitsToInt(buf, CPX_RQ_HI,CPX_RQ_LO)) {
case LOAD_RET: strcpy(str_type, "LOAD_RET"); break;
case INV_RET: strcpy(str_type, "INV_RET__AT_ACK__EVICT_REQ"); break;
case ST_ACK: strcpy(str_type, "ST_ACK"); break;
case INT_RET: strcpy(str_type, "INT_RET"); break;
case TEST_RET: strcpy(str_type, "TEST_RET"); break;
case FP_RET: strcpy(str_type, "FP_RET"); break;
case IFILL_RET: strcpy(str_type, "IFILL_RET"); break;
case ERR_RET: strcpy(str_type, "ERR_RET"); break;
case STRLOAD_RET: strcpy(str_type, "STRLOAD_RET"); break;
case STRST_ACK: strcpy(str_type, "STRST_ACK"); break;
case FWD_RQ_RET: strcpy(str_type, "FWD_RQ_RET"); break;
case FWD_RPY_RET: strcpy(str_type, "FWD_RPY_RET"); break;
case RSVD_RET: strcpy(str_type, "RSVD_RET"); break;
default: sprintf(str_type, "Unknown_0x%02llX", bitsToInt(buf, CPX_RQ_HI,CPX_RQ_LO));
}
printf("CPX_DATA Valid=%llu Type=%s Error=%llu NonCache_RnW=%llu Thread=%llu IntSrc_etc=0x%04llX Load_Data=0x%016llX%016llX\n",
bitsToInt(buf, CPX_VLD,CPX_VLD), str_type, bitsToInt(buf, CPX_ERR_HI-1,CPX_ERR_LO), bitsToInt(buf, CPX_R,CPX_R), bitsToInt(buf, CPX_TH_HI,CPX_TH_LO),
bitsToInt(buf, CPX_IN_HI,CPX_IN_LO), bitsToInt(buf, CPX_DA_HI,CPX_DA_LO+64), bitsToInt(buf, CPX_DA_LO+63,CPX_DA_LO));
}
 
// Main function
int main() {
char bit_vector[200];
char signal_type;
while(!feof(stdin)) {
fscanf(stdin, "%s %c\n", bit_vector, &signal_type);
reverse_string(bit_vector);
switch (signal_type) {
case VCD_ID_PCX_REQ: print_pcx_req(bit_vector); break;
case VCD_ID_PCX_ATOM: print_pcx_atom(bit_vector); break;
case VCD_ID_PCX_DATA: print_pcx_data(bit_vector); break;
case VCD_ID_PCX_GRANT: print_pcx_grant(bit_vector); break;
case VCD_ID_CPX_READY: print_cpx_ready(bit_vector); break;
case VCD_ID_CPX_DATA: print_cpx_data(bit_vector); break;
}
}
}
 
/tracan.h
0,0 → 1,129
// Header file for trace analyzer
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
const int LEN_REQ = 125;
const int LEN_RET = 146;
 
// Symbols used in trace.vcd generated from official OpenSPARC T1 sims
const char VCD_ID_PCX_REQ = '!';
const char VCD_ID_PCX_ATOM = '^';
const char VCD_ID_PCX_DATA = '"';
const char VCD_ID_PCX_GRANT = 'f';
const char VCD_ID_CPX_READY = '#';
const char VCD_ID_CPX_DATA = '$';
 
// From T1 defs
 
#define PCX_VLD 123 //PCX packet valid
#define PCX_RQ_HI 122 //PCX request type field
#define PCX_RQ_LO 118
#define PCX_NC 117 //PCX non-cacheable bit
#define PCX_R 117 //PCX read/!write bit
#define PCX_CP_HI 116 //PCX cpu_id field
#define PCX_CP_LO 114
#define PCX_TH_HI 113 //PCX Thread field
#define PCX_TH_LO 112
#define PCX_BF_HI 111 //PCX buffer id field
#define PCX_INVALL 111
#define PCX_BF_LO 109
#define PCX_WY_HI 108 //PCX replaced L1 way field
#define PCX_WY_LO 107
#define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
#define PCX_P_LO 107
#define PCX_SZ_HI 106 //PCX load/store size field
#define PCX_SZ_LO 104
#define PCX_ERR_HI 106 //PCX error field
#define PCX_ERR_LO 104
#define PCX_AD_HI 103 //PCX address field
#define PCX_AD_LO 64
#define PCX_DA_HI 63 //PCX Store data
#define PCX_DA_LO 0
 
#define PCX_SZ_1B 0x0
#define PCX_SZ_2B 0x1
#define PCX_SZ_4B 0x2
#define PCX_SZ_8B 0x3
#define PCX_SZ_16B 0x7
 
#define CPX_VLD 144 //CPX payload packet valid
 
#define CPX_RQ_HI 143 //CPX Request type
#define CPX_RQ_LO 140
#define CPX_ERR_HI 139 //CPX error field
#define CPX_ERR_LO 137
#define CPX_NC 136 //CPX non-cacheable
#define CPX_R 136 //CPX read/!write bit
#define CPX_TH_HI 135 //CPX thread ID field
#define CPX_TH_LO 134
 
//bits 133:128 are shared by different fields
//for different packet types.
 
#define CPX_IN_HI 133 //CPX Interrupt source
#define CPX_IN_LO 128
 
#define CPX_WYVLD 133 //CPX replaced way valid
#define CPX_WY_HI 132 //CPX replaced I$/D$ way
#define CPX_WY_LO 131
#define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
#define CPX_BF_LO 128
 
#define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
#define CPX_SI_LO 128 //used for invalidates
 
#define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
#define CPX_P_LO 130
 
#define CPX_ASI 130 //CPX forward request to ASI
#define CPX_IF4B 130
#define CPX_IINV 124
#define CPX_DINV 123
#define CPX_INVPA5 122
#define CPX_INVPA4 121
#define CPX_CPUID_HI 120
#define CPX_CPUID_LO 118
#define CPX_INV_PA_HI 116
#define CPX_INV_PA_LO 112
#define CPX_INV_IDX_HI 117
#define CPX_INV_IDX_LO 112
 
#define CPX_DA_HI 127 //CPX data payload
#define CPX_DA_LO 0
 
#define LOAD_RQ 0x00
#define IMISS_RQ 0x10
#define STORE_RQ 0x01
#define CAS1_RQ 0x02
#define CAS2_RQ 0x03
#define SWAP_RQ 0x06
#define STRLOAD_RQ 0x04
#define STRST_RQ 0x05
#define STQ_RQ 0x07 // Not found in official waves
#define INT_RQ 0x09 // NF
#define FWD_RQ 0x0D // NF
#define FWD_RPY 0x0E // NF
#define RSVD_RQ 0x1F // NF
// Added by Simply RISC
#define ATOM_REQ_A 0x0A
#define ATOM_REQ_B 0x0B
 
#define LOAD_RET 0x0
#define INV_RET 0x3 // Not found in official waves
#define ST_ACK 0x4
#define AT_ACK 0x3 // NF
#define INT_RET 0x7
#define TEST_RET 0x5 // NF
#define FP_RET 0x8
#define IFILL_RET 0x1
#define EVICT_REQ 0x3 // NF
#define ERR_RET 0xC // NF
#define STRLOAD_RET 0x2
#define STRST_ACK 0x6
#define FWD_RQ_RET 0xA // NF
#define FWD_RPY_RET 0xB // NF
#define RSVD_RET 0xF // NF
 
//End cache crossbar defines
/waves_s1.gtkw
0,0 → 1,31
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Nov 30 21:49:20 2015
[*]
[dumpfile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/run/sim/icarus/trace.vcd"
[dumpfile_mtime] "Mon Nov 30 21:48:09 2015"
[dumpfile_size] 9925089
[savefile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/src/waves_s1.gtkw"
[timestart] 0
[size] 1855 1151
[pos] -1 -1
*-21.545673 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] testbench.
[treeopen] testbench.s1_top_0.
[sst_width] 223
[signals_width] 529
[sst_expanded] 1
[sst_vpaned_height] 354
@23
testbench.s1_top_0.spc_pcx_req_pq[4:0]
@28
testbench.s1_top_0.spc_pcx_atom_pq
@22
testbench.s1_top_0.spc_pcx_data_pa[123:0]
testbench.s1_top_0.pcx_spc_grant_px[4:0]
@28
testbench.s1_top_0.cpx_spc_data_rdy_cx2
@22
testbench.s1_top_0.cpx_spc_data_cx2[144:0]
[pattern_trace] 1
[pattern_trace] 0
/waves_t1.gtkw
0,0 → 1,31
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Nov 22 17:04:48 2015
[*]
[dumpfile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/traces/v9_allinst:model_core1:core1_mini:0/trace.vcd"
[dumpfile_mtime] "Mon May 1 14:33:41 2006"
[dumpfile_size] 20236723
[savefile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/opt/tracan/waves.gtkw"
[timestart] 1984200
[size] 1855 1151
[pos] -1 -1
*-14.287723 2025079 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] cmp_top.
[treeopen] cmp_top.iop.
[sst_width] 223
[signals_width] 527
[sst_expanded] 1
[sst_vpaned_height] 354
@23
cmp_top.iop.sparc0.spc_pcx_req_pq[4:0]
@28
cmp_top.iop.sparc0.spc_pcx_atom_pq
@22
cmp_top.iop.sparc0.spc_pcx_data_pa[123:0]
cmp_top.iop.sparc0.pcx_spc_grant_px[4:0]
@28
cmp_top.iop.sparc0.cpx_spc_data_rdy_cx2
@22
cmp_top.iop.sparc0.cpx_spc_data_cx2[144:0]
[pattern_trace] 1
[pattern_trace] 0

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