URL
https://opencores.org/ocsvn/s1_core/s1_core/trunk
Subversion Repositories s1_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/s1_core/trunk/tools/src
- from Rev 113 to Rev 114
- ↔ Reverse comparison
Rev 113 → Rev 114
/TRACAN.txt
1,5 → 1,5
Simply RISC S1 Core - Tracan (Trace Analyzer) |
============================================= |
S1 Core - Tracan (Trace Analyzer) |
================================= |
|
This small tool has been written to convert the waveforms of the |
original OpenSPARC T1 simulation environment into a format similar |
48,5 → 48,3
your name into this file! |
- Enjoy! |
|
The development team at Simply RISC LLP |
|
/bw_r_dcd.v
1,4 → 1,4
// Empty module for cacheless Simply RISC S1 Core |
// Empty module for cacheless S1 Core |
|
module bw_r_dcd ( |
// Outputs |
/bw_r_icd.v
1,4 → 1,4
// Empty module for cacheless Simply RISC S1 Core |
// Empty module for cacheless S1 Core |
|
module bw_r_icd(icd_wsel_fetdata_s1, icd_wsel_topdata_s1, icd_fuse_repair_value, |
icd_fuse_repair_en, so, rclk, se, si, reset_l, sehold, fdp_icd_index_bf, |
/bw_r_idct.v
1,4 → 1,4
// Empty module for cacheless Simply RISC S1 Core |
// Empty module for cacheless S1 Core |
|
module bw_r_idct(rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so, rclk, se, |
si, reset_l, sehold, rst_tri_en, index0_x, index1_x, index_sel_x, |
/sourceme
1,6 → 1,6
|
# General paths settings |
export S1_ROOT=/usr/design/simplyrisc-s1 |
export S1_ROOT=/usr/design/s1_core |
export T1_ROOT=/usr/design/opensparc-t1/current |
export PATH=.:$S1_ROOT/tools/bin:$PATH |
|
/tracan.cpp
50,8 → 50,8
case FWD_RQ: strcpy(str_type, "FWD_RQ"); break; |
case FWD_RPY: strcpy(str_type, "FWD_RPY"); break; |
case RSVD_RQ: strcpy(str_type, "RSVD_RQ"); break; |
case ATOM_REQ_A: strcpy(str_type, "ATOM_REQ_A"); break; // Added by Simply RISC |
case ATOM_REQ_B: strcpy(str_type, "ATOM_REQ_B"); break; // Added by Simply RISC |
case ATOM_REQ_A: strcpy(str_type, "ATOM_REQ_A"); break; // Added for S1 Core |
case ATOM_REQ_B: strcpy(str_type, "ATOM_REQ_B"); break; // Added for S1 Core |
default: sprintf(str_type, "Unknown_0x%02llX", bitsToInt(buf, PCX_RQ_HI,PCX_RQ_LO)); |
} |
switch(bitsToInt(buf, PCX_SZ_HI,PCX_SZ_LO)) { |
/tracan.h
106,7 → 106,7
#define FWD_RQ 0x0D // NF |
#define FWD_RPY 0x0E // NF |
#define RSVD_RQ 0x1F // NF |
// Added by Simply RISC |
// Added for S1 Core |
#define ATOM_REQ_A 0x0A |
#define ATOM_REQ_B 0x0B |
|
/waves_s1.gtkw
2,10 → 2,10
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI |
[*] Mon Nov 30 21:49:20 2015 |
[*] |
[dumpfile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/run/sim/icarus/trace.vcd" |
[dumpfile] "/home/ubuntu/Work/SVN/s1_core/trunk/run/sim/icarus/trace.vcd" |
[dumpfile_mtime] "Mon Nov 30 21:48:09 2015" |
[dumpfile_size] 9925089 |
[savefile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/src/waves_s1.gtkw" |
[savefile] "/home/ubuntu/Work/SVN/s1_core/trunk/tools/src/waves_s1.gtkw" |
[timestart] 0 |
[size] 1855 1151 |
[pos] -1 -1 |
/waves_t1.gtkw
2,10 → 2,10
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI |
[*] Sun Nov 22 17:04:48 2015 |
[*] |
[dumpfile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/traces/v9_allinst:model_core1:core1_mini:0/trace.vcd" |
[dumpfile] "/home/ubuntu/Work/SVN/s1_core/trunk/tools/traces/v9_allinst:model_core1:core1_mini:0/trace.vcd" |
[dumpfile_mtime] "Mon May 1 14:33:41 2006" |
[dumpfile_size] 20236723 |
[savefile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/opt/tracan/waves.gtkw" |
[savefile] "/home/ubuntu/Work/SVN/s1_core/trunk/tools/opt/tracan/waves.gtkw" |
[timestart] 1984200 |
[size] 1855 1151 |
[pos] -1 -1 |