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/tags/Release IPCommunication v1.0/autobaud.vhd
0,0 → 1,294
--=============================================================================
-- TITRE : AUTOBAUD
-- DESCRIPTION :
 
 
 
 
 
 
-- FICHIER : autobaud.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY autobaud IS
PORT (
 
 
 
 
 
 
 
 
-- Interface avec les modules d'analyse Layer 2
 
eof1 : IN STD_LOGIC; -- Fin de trame port 1
 
l2_ok1 : IN STD_LOGIC; -- Flag de trame correcte port 1
 
eof2 : IN STD_LOGIC; -- Fin de trame port 2
 
l2_ok2 : IN STD_LOGIC; -- Flag de trame correcte port 2
 
-- Sorties du module
 
 
);
END autobaud;
 
ARCHITECTURE rtl of autobaud is
 
 
 
 
 
SIGNAL front_des_rx_c1 : STD_LOGIC; -- 1 pulse de clk_sys sur front descendant de rx1
SIGNAL front_mon_rx_c1 : STD_LOGIC; -- 1 pulse de clk_sys sur front montant de rx1
 
SIGNAL divclk1 : STD_LOGIC_VECTOR(nbbit-1 downto 0); -- mesure le nombre de clk_sys sur rx1
 
 
 
SIGNAL front_des_rx_c2 : STD_LOGIC; -- 1 pulse de clk_sys sur front descendant de rx2
SIGNAL front_mon_rx_c2 : STD_LOGIC; -- 1 pulse de clk_sys sur front montant de rx2
 
SIGNAL divclk2 : STD_LOGIC_VECTOR(nbbit-1 downto 0); -- mesure le nombre de clk_sys sur rx2
 
 
 
 
 
 
 
BEGIN
--------------------------------------------
 
--------------------------------------------
front_rx1 : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
rx_r1 <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx_r1 <= rx1;
END IF;
END PROCESS;
front_des_rx_c1 <= NOT(rx1) AND rx_r1;
front_mon_rx_c1 <= rx1 AND NOT(rx_r1);
--------------------------------------------
 
--------------------------------------------
mes_bit_1 : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
divclk1 <= (others => '0');
rx_encours1 <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (baud_locked_buf = '0') THEN
 
IF (front_des_rx_c1 = '1' OR front_mon_rx_c1 = '1') THEN
 
 
divclk1 <= (others => '0');-- On initialise le comptage de cycle
ELSIF (rx_encours1 = '1') THEN
 
IF (divclk1 /= SXT("11", nbbit)) THEN
 
divclk1 <= divclk1 + 1;
ELSE
 
rx_encours1 <= '0';
END IF;
END IF;
ELSE
rx_encours1 <= '0';
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
front_rx2 : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
rx_r2 <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx_r2 <= rx2;
END IF;
END PROCESS;
front_des_rx_c2 <= NOT(rx2) AND rx_r2;
front_mon_rx_c2 <= rx2 AND NOT(rx_r2);
 
--------------------------------------------
 
--------------------------------------------
mes_bit_2 : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
divclk2 <= (others => '0');
rx_encours2 <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (baud_locked_buf = '0') THEN
IF (front_des_rx_c2 = '1' OR front_mon_rx_c2 = '1') THEN
rx_encours2 <= '1';
divclk2 <= (others => '0');
ELSIF (rx_encours2 = '1') THEN
IF (divclk2 /= SXT("11", nbbit)) THEN
divclk2 <= divclk2 + 1;
ELSE
rx_encours2 <= '0';
END IF;
END IF;
ELSE
rx_encours2 <= '0';
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
 
mux_divclk_c <= divclk1 WHEN (front_mon_rx_c1 = '1' OR front_des_rx_c1 = '1') ELSE divclk2;
compare : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
memmin_div <= (others => '1');
cpt_car1 <= (others => '0');
cpt_car2 <= (others => '0');
cpt_fanion1 <= (OTHERS => '0');
cpt_fanion2 <= (OTHERS => '0');
baud_locked_buf <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (baud_locked_buf = '0') THEN
-- Si l'algo n'est pas fini
IF ((((front_des_rx_c1 = '1' OR front_mon_rx_c1 = '1') and rx_encours1 = '1') OR
((front_des_rx_c2 = '1' OR front_mon_rx_c2 = '1') and rx_encours2 = '1')) AND
(('0' & mux_divclk_c) < ('0' & memmin_div))) THEN
-- Si on a un front sur rx1 ou rx2, et que ce n'est pas le premier (i.e. on peut
-- utiliser la valeur du compteur), Et si cette valeur est plus petite que la valeur
 
 
 
cpt_car2 <= (others => '0');
ELSE
 
IF (cpt_car1 = "1111111111") OR (cpt_car2 = "1111111111") THEN
 
-- et que l'algo n'est pas fini
 
ELSE
 
cpt_car1 <= cpt_car1 + 1;
END IF;
IF (val_rx2 = '1') THEN
cpt_car2 <= cpt_car2 + 1;
END IF;
END IF;
END IF;
IF (val_rx1 = '1') THEN
 
IF (dat_rx1 = x"7E" OR dat_rx1 = x"F9") THEN
 
cpt_fanion1 <= cpt_fanion1 + 1;
ELSE
cpt_fanion1 <= (OTHERS => '0');
END IF;
END IF;
IF (val_rx2 = '1') THEN
IF (dat_rx2 = x"7E" OR dat_rx2 = x"F9") THEN
cpt_fanion2 <= cpt_fanion2 + 1;
ELSE
cpt_fanion2 <= (OTHERS => '0');
END IF;
END IF;
IF (eof1 = '1' AND l2_ok1 = '1') OR
(eof2 = '1' AND l2_ok2 = '1') OR
(cpt_fanion1 = "111") OR
(cpt_fanion2 = "111") THEN
 
 
baud_locked_buf <= '1';
cpt_car1 <= (others => '0');
END IF;
ELSE
 
IF ((val_rx1 = '1' AND dat_rx1 /= x"7E" AND dat_rx1 /= x"F9") OR
(val_rx2 = '1' AND dat_rx2 /= x"7E" AND dat_rx2 /= x"F9")) THEN
 
cpt_car1 <= cpt_car1 + 1;
IF (cpt_car1 = "0111111111") THEN
 
 
memmin_div <= (others => '1');
cpt_car1 <= (others => '0');
cpt_car2 <= (others => '0');
cpt_fanion1 <= (OTHERS => '0');
cpt_fanion2 <= (OTHERS => '0');
END IF;
ELSIF (eof1 = '1' AND l2_ok1 = '1') OR
(eof2 = '1' AND l2_ok2 = '1') THEN
 
 
END IF;
END IF;
END IF;
END PROCESS;
baud_locked <= baud_locked_buf;
 
--------------------------------------------
 
 
 
--------------------------------------------
selectbaud : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/50-1, tc_divclk'length);
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (memmin_div(10) = '1') THEN
 
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/50-1, tc_divclk'length);
ELSIF (memmin_div(9) = '1') THEN
 
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/100-1, tc_divclk'length);
ELSIF (memmin_div(8) = '1') THEN
 
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/200-1, tc_divclk'length);
ELSIF (memmin_div(7) = '1') THEN
 
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/500-1, tc_divclk'length);
ELSIF (memmin_div(6) = '1') THEN
 
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/1000-1, tc_divclk'length);
ELSIF (memmin_div(5) = '1') THEN
 
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/2000-1, tc_divclk'length);
ELSIF (memmin_div(4) = '1' OR
memmin_div(3 downto 2) = "11") THEN
 
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/6000-1, tc_divclk'length);
ELSE
 
tc_divclk <= CONV_STD_LOGIC_VECTOR(freq_clk*1000/12000-1, tc_divclk'length);
END IF;
END IF;
END PROCESS;
 
END rtl;
 
/tags/Release IPCommunication v1.0/com_exec.vhd
0,0 → 1,1100
--=============================================================================
-- TITRE : COM_EXEC
-- DESCRIPTION :
 
 
 
 
 
-- FICHIER : com_exec.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY com_exec IS
GENERIC (
 
reg_typemio : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"10"; -- Type du MIO
reg_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"10"; -- Version du MIO
 
 
);
PORT (
 
 
 
 
iid : IN STD_LOGIC_VECTOR(63 downto 0);-- Adresse IID du composant
 
 
 
 
 
 
 
rd_out : OUT STD_LOGIC; -- Signal de lecture sur l'interface externe
-- Interfaces vers les modules layer2_rx
 
 
-- Interfaces vers le module frame_store1
 
socin1 : IN STD_LOGIC; -- Indique que l'octet sur datin1 est le 1er d'une commande
rd_datin1 : OUT STD_LOGIC; -- Signal de lecture d'un nouvel octet applicatif
new_frame1 : IN STD_LOGIC; -- 1 Pulse indique qu'une nouvelle trame est disponible
l7_ok1 : IN STD_LOGIC; -- 1 Pulse indique que la nouvelle trame est conforme du point de vue layer 7
 
 
 
-- Interfaces vers le module frame_store2
 
socin2 : IN STD_LOGIC; -- Indique que l'octet sur datin2 est le 1er d'une commande
rd_datin2 : OUT STD_LOGIC; -- Signal de lecture d'un nouvel octet applicatif
new_frame2 : IN STD_LOGIC; -- 1 Pulse indique qu'une nouvelle trame est disponible
l7_ok2 : IN STD_LOGIC; -- 1 Pulse indique que la nouvelle trame est conforme du point de vue layer 7
 
 
 
-- Interfaces ver le module layer2_tx
 
 
valsent : OUT STD_LOGIC; -- validant du bus datsent
 
 
datsent_free: IN STD_LOGIC; -- Indique que le module layer2_tx a pris en compte l'octet datsent
clr_fifo_tx : OUT STD_LOGIC; -- Signal de purge de la FIFO Tx
 
-- Interface vers les modules switch
copy_ena1 : OUT STD_LOGIC; -- Autorise la copie de Rx1 sur Tx2
copy_ena2 : OUT STD_LOGIC; -- Autorise la copie de Rx2 sur Tx1
-- Interface de pilotage du module SPI
reload_fpgan: OUT STD_LOGIC; -- Ordre de reconfiguration du FPGA
 
spitx_val : OUT STD_LOGIC; -- Validant de spitx_dat
 
 
spirx_next : OUT STD_LOGIC; -- Lit un octet de plus dans spirx_val
 
 
 
 
spi_rstn : OUT STD_LOGIC -- Reset du module SPI
);
END com_exec;
 
ARCHITECTURE rtl OF com_exec IS
CONSTANT typ_sync : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"00"; -- Type pour trame de synchronisation
 
 
CONSTANT typ_atttid : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"3C"; -- Type pour trame d'attribution de TID
 
 
 
 
 
CONSTANT adreg_mac : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 7);
CONSTANT adreg_iid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(8, 7);
CONSTANT adreg_typ : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(16, 7);
CONSTANT adreg_ver : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(17, 7);
CONSTANT adreg_verpic: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(18, 7);
CONSTANT adreg_tid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(19, 7);
CONSTANT adreg_sid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(20, 7);
-- CONSTANT adreg_outrep: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(23, 7);
CONSTANT adreg_tcyc : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(24, 7);
CONSTANT adreg_status: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(25, 7);
--CONSTANT adreg_cnfrep: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(26, 7);
--CONSTANT adreg_cnfcyc: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(27, 7);
CONSTANT adreg_adref : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(28, 7);
CONSTANT adreg_szref : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(29, 7);
CONSTANT adreg_toco1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(30, 7);
CONSTANT adreg_toco2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(31, 7);
--CONSTANT adreg_seq : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(32, 7);
CONSTANT adreg_toac1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(33, 7);
CONSTANT adreg_toac2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(34, 7);
CONSTANT adreg_sync : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(35, 7);
CONSTANT adreg_for : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(36, 7);
CONSTANT adreg_conf : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(37, 7);
CONSTANT adreg_loadfpga: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(124, 7);
CONSTANT adreg_spinbr: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(125, 7);
CONSTANT adreg_spictl: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(126, 7);
CONSTANT adreg_spidat: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(127, 7);
 
SIGNAL reg_tid : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_config : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_status : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_adref : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_szref : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_cpttoco1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_cpttoco2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_cpttoac1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_cpttoac2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_cptsync : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_cptfor : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_tcyc : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_spinbr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_spictl : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_loadfpga : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
-- Signaux de gestion du cycle
 
 
SIGNAL tc_tcyc : STD_LOGIC_VECTOR(15 DOWNTO 0); -- Pour calculer reg_tcyc * 100
 
 
 
 
 
 
 
 
-- Signaux de gestion des monitoring
 
 
 
SIGNAL voie_toco : STD_LOGIC; -- 0 pour err_toco sur le port 1, 1 pour err_toco sur le port 2
 
 
 
 
SIGNAL com_dispo : STD_LOGIC; -- Multiplexage de com_dispo 1 ou 2 selon la voie
SIGNAL rd_combuf : STD_LOGIC; -- Buffer provisoire pour multiplexer rd_com
SIGNAL sel_voie : STD_LOGIC; -- A 0 si on traite la voie 1, a 1 si on traite la voie 2
 
 
 
 
 
 
 
SIGNAL store_com : STD_LOGIC; -- 1 pulse pour enregistrer la commande en cours dans un oldcomx
SIGNAL delete_com : STD_LOGIC; -- 1 pulse pour effacer la commande en cours des oldcomx
 
SIGNAL synchro_valide: STD_LOGIC; -- A 1 si la commande en cours est une synchrone valide
 
 
 
 
SIGNAL rd_r : STD_LOGIC; -- Pour retarder le signal rd de 1 cycle
 
 
SIGNAL rd_int : STD_LOGIC; -- Signal de lecture si ad_buf pointe sur un registre interne
SIGNAL dataread : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Multiplexeur pour la lecture
SIGNAL memadbuf7 : STD_LOGIC; -- Pour latcher le MSB du adbus lors d'une lecture
 
SIGNAL datint_read : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Multiplexeur pour la lecture des registres internes
SIGNAL socin : STD_LOGIC; -- Multiplexage des signaux socinx
 
-- Signaux de gestion des SYNC absents
SIGNAL cpt_syncmiss : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Compteur de trames de synhcro absentes
 
 
TYPE comexec_type IS (idle_st, rectyp_st, getadsrce_st, attribtid_st, purgesidsync_st, getseq_st, purgecrcsync_st, getadbuf_st, getnr_st, getcom_st,
writebyt_st, startframe_st, sendseq_st, sendcom_st, sendsrce_st, sendadr_st, sendnr_st, senddata_st,
sendstatus_st, endframe_st,purgecom_st);
SIGNAL fsm_comexec : comexec_type;
 
 
begin
--------------------------------------------
-- Affectation des sorties de configuration du module
--------------------------------------------
 
 
copy_ena1 <= reg_config(0); -- Autorisation de recopie du port 1 sur le port 2
copy_ena2 <= reg_config(1); -- Autorisationd e recopie du port 2 sur le port 1
clr_fifo_tx <= '0'; -- On n'utilsie pas le clr des FIFO Tx pour l'instant
spi_typecom <= reg_spictl(0); -- Type de commande sur le port SPI PROM
 
spi_rstn <= reg_spictl(4); -- Reset du module SPI PROM
 
--------------------------------------------
-- Gestion du signal de reprogrammation du FPGA
--------------------------------------------
gest_progb : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reload_fpgan <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (reg_spictl(4) = '0') THEN
-- Tant que le reset du module SPI est actif
reload_fpgan <= '1'; -- On fait rien
ELSIF (reg_loadfpga = x"31") THEN
-- Si le module SPI est actif et qu'on trouve la valeur magique dan le registre
reload_fpgan <= '0'; -- On force la reprogrammation
END IF;
END IF;
END PROCESS;
--------------------------------------------
 
-- interne (module SPI inclus)
-- externe
--------------------------------------------
 
 
 
-- On lit un registre interne selon le MSB de l'@
 
 
-- On lit un registre externe selon le MSB de l'@
 
 
 
spitx_val <= wr_int WHEN (ad_buf(6 DOWNTO 0) = adreg_spidat) ELSE '0';
 
 
 
spirx_next<= rd_int WHEN (ad_buf(6 DOWNTO 0) = adreg_spidat) ELSE '0';
 
--------------------------------------------
-- Gestion de la lecture sur le bus interne
--------------------------------------------
gest_readint : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
datint_read <= (others => '0');
memadbuf7 <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_int = '1') THEN
CASE ad_buf(6 DOWNTO 0) IS
 
WHEN adreg_mac | adreg_mac+1 | adreg_mac+2 | adreg_mac+3 |
adreg_mac+4 | adreg_mac+5 | adreg_mac+6 | adreg_mac+7 => datint_read <= x"FF";
WHEN adreg_iid => datint_read <= iid( 7 DOWNTO 0);
WHEN adreg_iid+1 => datint_read <= iid(15 DOWNTO 8);
WHEN adreg_iid+2 => datint_read <= iid(23 DOWNTO 16);
WHEN adreg_iid+3 => datint_read <= iid(31 DOWNTO 24);
WHEN adreg_iid+4 => datint_read <= iid(39 DOWNTO 32);
WHEN adreg_iid+5 => datint_read <= iid(47 DOWNTO 40);
WHEN adreg_iid+6 => datint_read <= iid(55 DOWNTO 48);
WHEN adreg_iid+7 => datint_read <= iid(63 DOWNTO 56);
WHEN adreg_typ => datint_read <= reg_typemio;
WHEN adreg_ver => datint_read <= reg_version;
WHEN adreg_verpic => datint_read <= x"00";
WHEN adreg_tid => datint_read <= reg_tid;
WHEN adreg_sid | adreg_sid+1 | adreg_sid+2 => datint_read <= x"FF";
WHEN adreg_tcyc => datint_read <= reg_tcyc;
WHEN adreg_status => datint_read <= reg_status;
WHEN adreg_adref => datint_read <= reg_adref;
WHEN adreg_szref => datint_read <= reg_szref;
WHEN adreg_toco1 => datint_read <= reg_cpttoco1;
WHEN adreg_toco2 => datint_read <= reg_cpttoco2;
WHEN adreg_toac1 => datint_read <= reg_cpttoac1;
WHEN adreg_toac2 => datint_read <= reg_cpttoac2;
WHEN adreg_sync => datint_read <= reg_cptsync;
WHEN adreg_for => datint_read <= reg_cptfor;
WHEN adreg_conf => datint_read <= reg_config;
WHEN adreg_spinbr => datint_read <= reg_spinbr;
WHEN adreg_spictl => datint_read <= spirx_val & reg_spictl(6 DOWNTO 4) & spi_busy & reg_spictl(2 DOWNTO 0);
WHEN adreg_spidat => datint_read <= spirx_dat;
WHEN OTHERS => datint_read <= reg_status;
END CASE;
END IF;
IF (rd = '1') THEN
-- sur une lecture, que ce soit interne ou externe
 
END IF;
END IF;
END PROCESS;
 
dataread <= datout_read WHEN memadbuf7 = '1' ELSE datint_read;
 
--------------------------------------------
 
 
--------------------------------------------
gest_wrreg : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_config <= x"03";
reg_adref <= ad_ref;
reg_szref <= sz_ref;
reg_tcyc <= x"FF";
reg_spinbr <= x"00";
reg_loadfpga <= x"00";
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (wr_int = '1') THEN
CASE ad_buf(6 DOWNTO 0) IS
 
WHEN adreg_conf =>
reg_config <= datawrite;
WHEN adreg_adref =>
reg_adref <= datawrite;
WHEN adreg_szref =>
reg_szref <= datawrite;
WHEN adreg_tcyc =>
reg_tcyc <= datawrite;
WHEN adreg_loadfpga =>
IF (reg_spictl(4) = '1') THEN
 
reg_loadfpga <= datawrite;
END IF;
WHEN adreg_spinbr =>
reg_spinbr <= datawrite;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF (wr_int = '1' AND ad_buf(6 DOWNTO 0) = adreg_spictl) THEN
reg_spictl <= datawrite;
ELSE
-- On s'assure que le pulse de commande du SPI ne dure qu'un seul cycle
reg_spictl(3) <= '0';
END IF;
END IF;
END PROCESS;
----------------------------------
-- Gestion du registre de status
----------------------------------
gest_stat : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
 
reg_status <= x"80";
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_int = '1' AND ad_buf(6 DOWNTO 0) = adreg_status) OR
(fsm_comexec = sendstatus_st AND datsent_free = '1') THEN
 
reg_status <= x"00";
ELSE
IF (err_toco = '1') THEN
 
reg_status(0) <= '1';
END IF;
 
IF (start_cycle = '1' AND mem_activity1 = '0') THEN
 
reg_status(2) <= '1';
END IF;
IF (start_cycle = '1' AND mem_activity2 = '0') THEN
 
reg_status(3) <= '1';
END IF;
IF (synchro_miss = '1') THEN
-- Gestion du bit NTS (pas de trame de synhcro)
reg_status(4) <= '1';
END IF;
IF (new_frame1 = '1' AND l7_ok1 = '0') OR
(new_frame2 = '1' AND l7_ok2 = '0') THEN
 
reg_status(5) <= '1';
END IF;
reg_status(6) <= sel_voie;
reg_status(7) <= '0';
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
-- Gestion de la synchro
--------------------------------------------
gest_sync : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cpt_syncmiss <= (others => '0');
synchro_lock <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (synchro_outwin = '1' AND synchro_lock = '1') THEN
 
cpt_syncmiss <= (others => '0'); -- On annule le compteur de trame de sync manquante
 
ELSE
IF (synchro = '1') THEN
 
synchro_lock <= '1';
cpt_syncmiss <= (others => '0');
ELSIF (synchro_miss = '1') THEN
-- Sur chaque cycle sans trame de synchro
IF (cpt_syncmiss /= x"FF") THEN
 
cpt_syncmiss <= cpt_syncmiss + 1;
ELSE
 
END IF;
END IF;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
-- Gestion du temps de cycle de communication
--------------------------------------------
gest_cycle : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
mes10us <= (others => '0');
mescycle <= CONV_STD_LOGIC_VECTOR(1, mescycle'LENGTH);
tc_tcyc <= (OTHERS => '0');
start_cycle <= '0';
win_syncbefore <= '0';
win_syncafter <= '0';
synchro_miss <= '0';
cpt_seq <= (others => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
 
tc_tcyc <= EXT(reg_tcyc & "000000", tc_tcyc'LENGTH) + EXT(reg_tcyc & "00000", tc_tcyc'LENGTH) + EXT(reg_tcyc & "00", tc_tcyc'LENGTH);
IF (synchro = '1') THEN
 
 
 
 
 
win_syncafter <= '1'; -- Par contre, onpeut recevoir une synchro en retard
synchro_miss <= '0';
 
ELSE
IF (mes10us = CONV_STD_LOGIC_VECTOR(freq_clksys*10-1, mes10us'length)) THEN
-- Toutes les 10 us
mes10us <= (others => '0');
IF (mescycle = ('0' & tc_tcyc) + ("0000" & tc_tcyc(tc_tcyc'LEFT DOWNTO 3))) THEN
 
 
win_syncafter <= '0';
 
mescycle <= ("0000" & tc_tcyc(tc_tcyc'LEFT DOWNTO 3)) + 1;
 
 
ELSE
-- Si on a pas encore atteind le 1.125xTCYC
mescycle <= mescycle + 1;
IF (mescycle = ('0' & tc_tcyc) - ("0000" & tc_tcyc(tc_tcyc'LEFT DOWNTO 3))) THEN
 
 
win_syncafter <= '0'; -- Par contre la synchro en retard ne serait pas valide
ELSIF (mescycle = ('0' & tc_tcyc)) THEN
 
win_syncbefore <= '0';
 
 
ELSIF (mescycle = ("0000" & tc_tcyc(tc_tcyc'LEFT DOWNTO 3))) THEN
 
 
END IF;
END IF;
ELSE
 
start_cycle <= '0'; -- On assure que les signaux ne durent qu'un clk
synchro_miss <= '0';
mes10us <= mes10us + 1;
END IF;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
-- Gestion des compteurs de monitoring
--------------------------------------------
-- Compteur de trames avec un mauvais format (champs invalides, CRC faux, ...)
gest_for : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_cptfor <= (others => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_int = '1' AND ad_buf(6 DOWNTO 0) = adreg_for) THEN
 
IF (new_frame1 = '1' AND l7_ok1 = '0') OR (new_frame2 = '1' AND l7_ok2 = '0') THEN
reg_cptfor(0) <= '1';
ELSE
reg_cptfor(0) <= '0';
END IF;
reg_cptfor(7 DOWNTO 1) <= "0000000";
ELSIF (reg_cptfor /= x"FF") THEN
IF (new_frame1 = '1' AND l7_ok1 = '0') OR
(new_frame2 = '1' AND l7_ok2 = '0') THEN
 
reg_cptfor <= reg_cptfor + 1;
END IF;
END IF;
END IF;
END PROCESS;
 
-- Compteur d'absence de trame de synchro
gest_abssync : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_cptsync <= (others => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_int = '1' AND ad_buf(6 DOWNTO 0) = adreg_sync) THEN
 
reg_cptsync <= "0000000" & synchro_miss;
ELSIF (reg_cptsync /= x"FF") THEN
IF (synchro_miss = '1') THEN
reg_cptsync <= reg_cptsync + 1;
END IF;
END IF;
END IF;
END PROCESS;
 
 
gest_toac1 : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_cpttoac1 <= (others => '0');
mem_activity1 <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_int = '1' AND ad_buf(6 DOWNTO 0) = adreg_toac1) THEN
 
IF (start_cycle = '1' AND mem_activity1 = '0') THEN
reg_cpttoac1(0) <= '1';
ELSE
reg_cpttoac1(0) <= '0';
END IF;
reg_cpttoac1(7 DOWNTO 1) <= "0000000";
ELSIF (reg_cpttoac1 /= x"FF") THEN
IF (start_cycle = '1' AND mem_activity1 = '0') THEN
 
reg_cpttoac1 <= reg_cpttoac1 + 1;
END IF;
END IF;
IF (activity1 = '1') THEN
 
mem_activity1 <= '1';
ELSIF (start_cycle = '1') THEN
 
mem_activity1 <= '0';
END IF;
END IF;
END PROCESS;
 
 
gest_toac2 : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_cpttoac2 <= (others => '0');
mem_activity2 <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_int = '1' AND ad_buf(6 DOWNTO 0) = adreg_toac2) THEN
 
IF (start_cycle = '1' AND mem_activity2 = '0') THEN
reg_cpttoac2(0) <= '1';
ELSE
reg_cpttoac2(0) <= '0';
END IF;
reg_cpttoac2(7 DOWNTO 1) <= "0000000";
ELSIF (reg_cpttoac2 /= x"FF") THEN
IF (start_cycle = '1' AND mem_activity2 = '0') THEN
reg_cpttoac2 <= reg_cpttoac2 + 1;
END IF;
END IF;
IF (activity2 = '1') THEN
mem_activity2 <= '1';
ELSIF (start_cycle = '1') THEN
mem_activity2 <= '0';
END IF;
END IF;
END PROCESS;
 
 
gest_toco1 : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_cpttoco1 <= (others => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_int = '1' AND ad_buf(6 DOWNTO 0) = adreg_toco1) THEN
 
IF (err_toco = '1' AND voie_toco = '0') THEN
reg_cpttoco1(0) <= '1';
ELSE
reg_cpttoco1(0) <= '0';
END IF;
reg_cpttoco1(7 DOWNTO 1) <= "0000000";
ELSIF (reg_cpttoco1 /= x"FF") THEN
IF (err_toco = '1' AND voie_toco = '0') THEN
-- Si on a une trame absente (err_toco) sur le voie 1 (voie_toco)
reg_cpttoco1 <= reg_cpttoco1 + 1;
END IF;
END IF;
END IF;
END PROCESS;
 
 
gest_toco2 : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_cpttoco2 <= (others => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_int = '1' AND ad_buf(6 DOWNTO 0) = adreg_toco2) THEN
IF (err_toco = '1' AND voie_toco = '1') THEN
reg_cpttoco2(0) <= '1';
ELSE
reg_cpttoco2(0) <= '0';
END IF;
reg_cpttoco2(7 DOWNTO 1) <= "0000000";
ELSIF (reg_cpttoco2 /= x"FF") THEN
IF (err_toco = '1' AND voie_toco = '1') THEN
-- Si on a une trame absente (err_toco) sur le voie 2 (voie_toco)
reg_cpttoco2 <= reg_cpttoco2 + 1;
END IF;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
 
 
rd_datin1 <= rd_combuf WHEN (sel_voie = '0') ELSE '0';-- On lit un octet de plus dans le bon buffer
rd_datin2 <= rd_combuf WHEN (sel_voie = '1') ELSE '0';
 
 
 
rd_combuf <= rd_com AND com_dispo AND NOT(socin) WHEN (fsm_comexec = purgecom_st) ELSE
rd_com AND com_dispo;
--------------------------------------------
 
-- Format des oldcom
 
 
-- 8 LSB : champs de la commande
 
--------------------------------------------
mem_oldcom : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
oldcom1 <= (others => '0');
oldcom2 <= (others => '0');
oldcom3 <= (others => '0');
err_toco <= '0';
voie_toco <= '0';
mem_sync <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (synchro = '1') THEN
 
mem_sync <= '1';
ELSIF (start_cycle = '1') THEN
 
mem_sync <= '0';
END IF;
IF (start_cycle = '1') THEN
 
IF (mem_sync = '1') THEN
 
 
 
 
oldcom3(8) <= '0'; -- On purge les FIFO oldcom
END IF;
IF (oldcom1(8) = '1') THEN
 
 
 
ELSE
err_toco <= '0';
END IF;
ELSIF (store_com = '1') THEN
 
IF (oldcom1(8) = '0') THEN
oldcom1 <= sel_voie & '1' & typ_field;
ELSIF (oldcom2(8) = '0') THEN
oldcom2 <= sel_voie & '1' & typ_field;
ELSIF (oldcom3(8) = '0') THEN
oldcom3 <= sel_voie & '1' & typ_field;
ELSE
 
oldcom1 <= oldcom2;
oldcom2 <= oldcom3;
oldcom3 <= sel_voie & '1' & typ_field;
END IF;
err_toco <= '0';
ELSIF (delete_com = '1') THEN
 
IF (oldcom1 = NOT(sel_voie) & '1' & typ_field) THEN
 
 
oldcom2 <= oldcom3;
 
err_toco <= '0';
ELSIF (oldcom2 = NOT(sel_voie) & '1' & typ_field) THEN
 
 
 
oldcom2(8) <= '0';
oldcom3(8) <= '0';
err_toco <= '1'; -- On indique l'erreur
voie_toco <= NOT(oldcom1(9)); -- et sur quelle voie il y'a eu l'erreur
ELSIF (oldcom3 = NOT(sel_voie) & '1' & typ_field) THEN
 
 
 
 
 
oldcom2(8) <= '0';
oldcom3(8) <= '0';
err_toco <= '1'; -- On indique l'erreur
voie_toco <= NOT(oldcom1(9)); -- et sur quelle voie il y'a eu l'erreur
END IF;
ELSE
err_toco <= '0'; -- Pour assurer qu'il ne dure qu'un seul cycle
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
 
com_recue <= '1' WHEN ((oldcom1 = NOT(sel_voie) & '1' & datin) OR
(oldcom2 = NOT(sel_voie) & '1' & datin) OR
(oldcom3 = NOT(sel_voie) & '1' & datin)) ELSE '0';
 
 
 
synchro_valide <= '1' WHEN (typ_field = typ_sync AND
(synchro_lock = '0' OR
(win_syncbefore = '1' AND datin = cpt_seq + 1) OR
(win_syncafter = '1' AND datin = cpt_seq))) ELSE '0';
 
man_fsm : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_comexec <= idle_st;
sel_voie <= '1';
cpt_byt <= (others => '0');
reg_tid <= x"8F";
wr <= '0';
rd <= '0';
rd_r <= '0';
ad_buf <= (others => '0');
 
store_com <= '0';
delete_com <= '0';
synchro_outwin <= '0';
rd_com <= '0';
sof <= '0';
eof <= '0';
datsent <= (others => '0');
valsent <= '0';
datawrite <= (others => '0');
synchro <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_comexec IS
WHEN idle_st =>
 
wr <= '0';
rd <= '0';
synchro <= '0';
store_com <= '0';
delete_com <= '0';
synchro_outwin <= '0';
sof <= '0';
eof <= '0';
valsent <= '0';
IF (com_dispo1 = '1' AND (com_dispo2 = '0' OR sel_voie = '1')) THEN
-- On s'assure qu'on traite par alternance une voie et puis l'autre. On traite la voie 1 que si y'a
 
 
rd_com <= '1'; -- On demande un octet de plus par anticipation
fsm_comexec <= rectyp_st;
ELSIF (com_dispo2 = '1') THEN
 
 
rd_com <= '1';
fsm_comexec <= rectyp_st;
ELSE
rd_com <= '0';
END IF;
WHEN rectyp_st =>
-- Etat d'enregistrement du type de commande
 
IF (com_recue = '0') THEN
 
fsm_comexec <= getadsrce_st; --
IF (datin /= typ_sync) THEN
 
store_com <= '1';
END IF;
ELSE
 
 
 
END IF;
WHEN getadsrce_st =>
 
--ad_source <= datin;
store_com <= '0';
delete_com <= '0';
-- On va traiter la commande en fonction de son type
IF (typ_field = typ_sync) THEN
-- Si c'est une trame de synchro
cpt_byt <= x"01";
fsm_comexec <= purgesidsync_st; -- On va purger le SID de la trame de synhcro
ELSIF (typ_field = typ_atttid) THEN
-- Si c'est une commande type attribution de TID
 
fsm_comexec <= attribtid_st;
ELSIF (typ_field = typ_reqnoseq) THEN
 
fsm_comexec <= getcom_st;
ELSE
-- Si c'est une trame qu'on ne sait pas traiter, on va la purger
rd_com <= '0';
fsm_comexec <= purgecom_st;
END IF;
 
WHEN purgesidsync_st =>
 
cpt_byt <= cpt_byt - 1;
IF (cpt_byt = "00") THEN
fsm_comexec <= getseq_st;
END IF;
 
WHEN getseq_st =>
 
seq_field <= datin;
IF (synchro_valide = '1') THEN
-- Si le champ SEQ est valable
rd_com <= '1'; -- On continu de lire pour supprimer le CRC
synchro <= '1'; -- On signale une synchro valide
IF (reg_config(3) = '1') THEN
 
-- On va d'abord purger les 2 CRC de la commande
fsm_comexec <= purgecrcsync_st;
cpt_byt <= x"01";
ELSE
 
fsm_comexec <= purgecom_st; -- On va purger la commande
END IF;
ELSE
IF (win_syncbefore = '0' AND win_syncafter = '0') THEN
 
synchro_outwin <= '1';
END IF;
fsm_comexec <= purgecom_st;
rd_com <= '0';
END IF;
 
WHEN purgecrcsync_st =>
-- Etat de purge des 2 octets de CRC de la trmae de synchro
synchro <= '0';
cpt_byt <= cpt_byt - 1;
IF (cpt_byt = "00") THEN
-- Si on a fini de purger le CRC de la trame de synchro
 
sof <= '1';
 
valsent <= '1'; -- On valide l'octet sorti
 
 
rd_com <= '0';
END IF;
 
WHEN attribtid_st =>
 
 
cpt_byt <= cpt_byt - 1;
IF (cpt_byt = x"00") THEN
 
IF (iid_temp = iid) THEN
 
 
END IF;
fsm_comexec <= idle_st;
rd_com <= '0';
END IF;
 
WHEN getcom_st =>
 
com_field <= datin;
rd_com <= '1';
fsm_comexec <= getnr_st;
 
WHEN getnr_st =>
 
cpt_byt <= datin;
rd_com <= '1';
fsm_comexec <= getadbuf_st;
 
WHEN getadbuf_st =>
 
ad_buf <= datin;
IF (com_field = com_write) THEN
 
fsm_comexec <= writebyt_st;
rd_com <= '1';
ELSIF (com_field = com_read) THEN
-- Si c'est une commande de lecture
 
 
 
valsent <= '1'; -- On valide l'octet sorti
rd_com <= '0'; -- On ne lit plus rien de la commande pour l'instant
 
fsm_comexec <= purgecom_st;
rd_com <= '0';
END IF;
WHEN writebyt_st =>
 
datawrite <= datin;
wr <= '1';
cpt_byt <= cpt_byt - 1 ;
IF (wr = '1' AND (ad_buf /= ('0' & adreg_spidat)) AND ad_buf /= x"FF") THEN
 
 
ad_buf <= ad_buf + 1;
END IF;
IF (cpt_byt = x"01") THEN
 
 
 
END IF;
WHEN startframe_st =>
 
synchro <= '0'; -- Le signal de synhcro ne doit durer qu'1 pulse
IF (datsent_free = '1') THEN
-- Si le 1er octet est en cours de traitement, l'octet suivant est le TYPE
 
 
valsent <= '1';
fsm_comexec <= sendsrce_st;
END IF;
WHEN sendsrce_st =>
 
IF (datsent_free = '1') THEN
datsent <= reg_tid;
valsent <= '1';
fsm_comexec <= sendcom_st;
END IF;
 
WHEN sendcom_st =>
 
IF (datsent_free = '1') THEN
IF (typ_field = typ_sync) THEN
 
datsent <= x"01";
ELSE
 
datsent <= x"02";
END IF;
valsent <= '1';
fsm_comexec <= sendnr_st;
END IF;
 
WHEN sendnr_st =>
-- Envoie du nombre d 'octets lus
IF (datsent_free = '1') THEN
datsent <= cpt_byt;
valsent <= '1';
fsm_comexec <= sendadr_st;
END IF;
 
WHEN sendadr_st =>
-- Envoie de l'adresse ou on a lu les octets
IF (datsent_free = '1') THEN
datsent <= ad_buf;
rd <= '1';
rd_r <= '0';
valsent <= '1';
fsm_comexec <= senddata_st;
END IF;
 
WHEN senddata_st =>
 
 
IF (rd = '1' AND datsent_free = '1') THEN
rd_r <= '1';
IF ((ad_buf /= ('0' & adreg_spidat)) AND ad_buf /= x"FF") THEN
 
ad_buf <= ad_buf + 1;
END IF;
cpt_byt <= cpt_byt - 1;
END IF;
IF (datsent_free = '1') THEN
 
IF (cpt_byt = x"01") THEN
 
END IF;
IF (rd_r = '1') THEN
 
datsent <= dataread; -- On l'envoie
valsent <= '1';
IF (cpt_byt = x"00") THEN
 
IF (typ_field = typ_sync) THEN
 
fsm_comexec <= sendstatus_st; -- Il faut envoyer l'octet de status
ELSE
 
fsm_comexec <= endframe_st; -- On a fini
eof <= '1';
END IF;
END IF;
ELSE
 
 
END IF;
END IF;
 
WHEN sendstatus_st =>
-- Envoie du registre de status
IF (datsent_free = '1') THEN
datsent <= reg_status;
valsent <= '1';
eof <= '1';
fsm_comexec <= endframe_st;
END IF;
 
WHEN endframe_st =>
-- Gestion de la fin d'envoie d'une trame
IF (datsent_free = '1') THEN
eof <= '0';
valsent <= '0';
fsm_comexec <= idle_st;
END IF;
 
WHEN purgecom_st =>
 
 
store_com <= '0';
delete_com <= '0';
synchro_outwin <= '0';
IF (sel_voie = '0') THEN
IF (com_dispo1 = '1' AND socin1 = '0') THEN
 
rd_com <= '1';
ELSE
rd_com <= '0';
fsm_comexec <= idle_st;
END IF;
ELSE
IF (com_dispo2 = '1' AND socin2 = '0') THEN
rd_com <= '1';
ELSE
rd_com <= '0';
fsm_comexec <= idle_st;
END IF;
END IF;
WHEN OTHERS =>
fsm_comexec <= idle_st;
END CASE;
END IF;
END PROCESS;
 
end rtl;
 
/tags/Release IPCommunication v1.0/communication.vhd
0,0 → 1,626
--=============================================================================
-- TITRE : COMMUNICATION
-- DESCRIPTION :
 
-- Le module read_mac maintien les autres modules en reset
 
-- FICHIER : communication.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
ENTITY communication IS
GENERIC (
reg_typemio : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"10"; -- Type du MIO
reg_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"10"; -- Version du MIO
 
 
);
PORT (
 
 
 
iid : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- IID du MIO
sync_lock : OUT STD_LOGIC;
 
 
 
 
 
 
 
 
 
 
 
rd_out : OUT STD_LOGIC; -- Signal de lecture sur l'interface externe
-- Signaux de pilotage du SPI de la PROM de config du FPGA
reload_fpgan: OUT STD_LOGIC; -- Ordre de reconfig du FPGA
spi_csn : OUT STD_LOGIC; -- CS de la PROM
spi_wpn : OUT STD_LOGIC; -- Write protect de la PROM
spi_sdo : OUT STD_LOGIC; -- Serial Data vers la PROM
spi_sdi : IN STD_LOGIC; -- Serial Data venant de la PROM
 
spare : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END communication;
 
ARCHITECTURE rtl of communication is
 
 
CONSTANT nbbit_div : INTEGER := 11;
 
 
 
 
SIGNAL tc_divclk : STD_LOGIC_VECTOR(nbbit_div - 1 DOWNTO 0); -- Diviseur d'horloge pour le baud rate
 
SIGNAL tid : STD_LOGIC_VECTOR(7 DOWNTO 0); -- TID du MIO
 
-- Interfaces du SWITCH1
 
SIGNAL layer1_val1 : STD_LOGIC; -- Indique un octet valide sur layer1_rx1
 
 
 
SIGNAL layer1_empty1 : STD_LOGIC; -- Indique qu'aucun octet n'est en attente de serialsiation
SIGNAL copy_ena1 : STD_LOGIC;
-- Interfaces du SWITCH2
SIGNAL layer1_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL layer1_val2 : STD_LOGIC;
SIGNAL sw_ena2 : STD_LOGIC;
SIGNAL layer1_tx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL layer1_rd2 : STD_LOGIC;
SIGNAL layer1_empty2 : STD_LOGIC;
SIGNAL copy_ena2 : STD_LOGIC;
-- Interfaces du module LAYER2_RX1
 
SIGNAL layer2_rxval1 : STD_LOGIC; -- Indique un octet valide sur layer2_rx1
 
SIGNAL layer2_eof1 : STD_LOGIC; -- Indqiue une fin de trame
 
 
-- Interfaces du module LAYER2_RX2
SIGNAL layer2_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL layer2_rxval2 : STD_LOGIC;
SIGNAL layer2_sof2 : STD_LOGIC;
SIGNAL layer2_eof2 : STD_LOGIC;
SIGNAL layer2_l2ok2 : STD_LOGIC;
 
-- Interfaces du module FRAME_STORE1 (couche applicative)
 
 
SIGNAL layer7_rd1 : STD_LOGIC; -- Signal de lecture d'un octet de plus
 
 
 
 
-- Interfaces du module FRAME_STORE2
SIGNAL layer7_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL layer7_soc2 : STD_LOGIC;
SIGNAL layer7_rd2 : STD_LOGIC;
SIGNAL layer7_newframe2 : STD_LOGIC;
SIGNAL layer7_comdispo2 : STD_LOGIC;
SIGNAL layer7_l7ok2 : STD_LOGIC;
SIGNAL layer7_overflow2 : STD_LOGIC;
 
 
 
SIGNAL val_txdat : STD_LOGIC; -- Indique un octet dispo sur tx_dat
 
SIGNAL tx_eof : STD_LOGIC; -- Indique une fin de trame
SIGNAL txdat_free : STD_LOGIC; -- Indique que le module couche transport Tx est dispo
SIGNAL clr_fifo_tx : STD_LOGIC; -- Clear de la FIFO transport Tx
 
-- Interfaces du module LAYER2_TX
 
SIGNAL layer2_txval : STD_LOGIC; -- Indique un octet valide sur layer2_txdat
 
 
 
 
-- Interface de pilotage du module SPI de programmation de la PROM FPGA
 
SIGNAL spitx_val : STD_LOGIC; -- Validant de spitx_dat
 
 
SIGNAL spirx_next : STD_LOGIC; -- Lit un octet de plus dans spirx_val
 
 
 
 
SIGNAL spi_rstn : STD_LOGIC; -- Reset du module SPI
SIGNAL etat1, etat2 : STD_LOGIC;
 
COMPONENT autobaud
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
rx1 : IN STD_LOGIC;
val_rx1 : IN STD_LOGIC;
eof1 : IN STD_LOGIC;
dat_rx1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
l2_ok1 : IN STD_LOGIC;
rx2 : IN STD_LOGIC;
val_rx2 : IN STD_LOGIC;
eof2 : IN STD_LOGIC;
dat_rx2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
l2_ok2 : IN STD_LOGIC;
tc_divclk : OUT STD_LOGIC_VECTOR(10 downto 0);
baud_locked : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT switch
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
baud_lock : IN STD_LOGIC;
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
rx : IN STD_LOGIC;
rx_dat : OUT STD_LOGIC_VECTOR(7 downto 0);
rx_val : OUT STD_LOGIC;
tx : OUT STD_LOGIC;
tx_dat : IN STD_LOGIC_VECTOR(7 downto 0);
tx_rd : OUT STD_LOGIC;
tx_empty : IN STD_LOGIC;
sw_ena : IN STD_LOGIC;
copy_ena : IN STD_LOGIC;
etat : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT layer2_rx
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
ad_mio : IN STD_LOGIC_VECTOR(7 downto 0);
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
val_out : OUT STD_LOGIC;
sw_ena : OUT STD_LOGIC;
sof : OUT STD_LOGIC;
eof : OUT STD_LOGIC;
l2_ok : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT frame_store
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
sof : IN STD_LOGIC;
eof : IN STD_LOGIC;
l2_ok : IN STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
soc_out : OUT STD_LOGIC;
rd_datout : IN STD_LOGIC;
new_frame : OUT STD_LOGIC;
com_dispo : OUT STD_LOGIC;
l7_ok : OUT STD_LOGIC;
overflow : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT com_exec
GENERIC (
freq_clksys : INTEGER := 48;
reg_typemio : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"10"; -- Type du MIO
reg_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"10"; -- Version du MIO
ad_ref : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"80";
sz_ref : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"04"
);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
tid : OUT STD_LOGIC_VECTOR(7 downto 0);
iid : IN STD_LOGIC_VECTOR(63 downto 0);
sync_lock : OUT STD_LOGIC;
datout_read : IN STD_LOGIC_VECTOR(7 downto 0);
datout_write: OUT STD_LOGIC_VECTOR(7 downto 0);
ad_out : OUT STD_LOGIC_VECTOR(6 downto 0);
wr_out : OUT STD_LOGIC;
rd_out : OUT STD_LOGIC;
activity1 : IN STD_LOGIC;
activity2 : IN STD_LOGIC;
datin1 : IN STD_LOGIC_VECTOR(7 downto 0);
socin1 : IN STD_LOGIC;
new_frame1 : IN STD_LOGIC;
com_dispo1 : IN STD_LOGIC;
l7_ok1 : IN STD_LOGIC;
l7_overflow1: IN STD_LOGIC;
datin2 : IN STD_LOGIC_VECTOR(7 downto 0);
socin2 : IN STD_LOGIC;
new_frame2 : IN STD_LOGIC;
com_dispo2 : IN STD_LOGIC;
l7_ok2 : IN STD_LOGIC;
l7_overflow2: IN STD_LOGIC;
datsent_free: IN STD_LOGIC;
rd_datin1 : OUT STD_LOGIC;
rd_datin2 : OUT STD_LOGIC;
datsent : OUT STD_LOGIC_VECTOR(7 downto 0);
valsent : OUT STD_LOGIC;
sof : OUT STD_LOGIC;
eof : OUT STD_LOGIC;
clr_fifo_tx : OUT STD_LOGIC;
copy_ena1 : OUT STD_LOGIC;
copy_ena2 : OUT STD_LOGIC;
reload_fpgan: OUT STD_LOGIC;
spitx_dat : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
spitx_val : OUT STD_LOGIC;
spirx_dat : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
spirx_val : IN STD_LOGIC;
spirx_next : OUT STD_LOGIC;
spi_typecom : OUT STD_LOGIC;
spi_execcom : OUT STD_LOGIC;
spi_busy : IN STD_LOGIC;
spi_nbread : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
spi_rstn : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT layer2_tx
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
sof : IN STD_LOGIC;
eof : IN STD_LOGIC;
datin_free : OUT STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
val_out : OUT STD_LOGIC;
clr_fifo : IN STD_LOGIC;
progfull1 : IN STD_LOGIC;
progfull2 : IN STD_LOGIC;
full1 : IN STD_LOGIC;
empty1 : IN STD_LOGIC;
full2 : IN STD_LOGIC;
empty2 : IN STD_LOGIC
);
END COMPONENT;
 
 
-- stockage avant overflow (voir le module layer2_tx)
COMPONENT fifo_tx
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full: OUT STD_LOGIC
);
END COMPONENT;
COMPONENT if_promspi
GENERIC (
 
spiclk_freq : INTEGER := 12
);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
spi_csn : OUT std_logic;
spi_wpn : OUT std_logic;
spi_sdo : OUT std_logic;
spi_sdi : IN std_logic;
spi_clk : OUT std_logic;
tx_dat : IN std_logic_vector(7 downto 0);
tx_val : IN std_logic;
rx_dat : OUT std_logic_vector(7 downto 0);
rx_val : OUT std_logic;
rx_next : IN std_logic;
type_com : IN std_logic;
exec_com : IN std_logic;
spi_busy : OUT std_logic;
nb_read : IN std_logic_vector(7 downto 0)
);
END COMPONENT;
BEGIN
spare <= etat2 & etat1 & sw_ena2 & sw_ena1 & copy_ena2 & copy_ena1;
--------------------------------------------
 
--------------------------------------------
meta : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
rx1_r1 <= '1';
rx1_r2 <= '1';
rx2_r1 <= '1';
rx2_r2 <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx1_r1 <= rx1;
rx1_r2 <= rx1_r1;
rx2_r1 <= rx2;
rx2_r2 <= rx2_r1;
END IF;
END PROCESS;
 
inst_autobaud: autobaud
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
rx1 => rx1_r2,
rx2 => rx2_r2,
val_rx1 => layer1_val1,
dat_rx1 => layer1_rx1,
eof1 => layer2_eof1,
l2_ok1 => layer2_l2ok1,
val_rx2 => layer1_val2,
dat_rx2 => layer1_rx2,
eof2 => layer2_eof2,
l2_ok2 => layer2_l2ok2,
tc_divclk => tc_divclk,
baud_locked => baud_locked
);
 
inst_switch1: switch
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_locked,
tc_divclk => tc_divclk,
rx => rx1_r2,
rx_dat => layer1_rx1,
rx_val => layer1_val1,
tx => tx2,
tx_dat => layer1_tx2,
tx_rd => layer1_rd2,
tx_empty => layer1_empty2,
sw_ena => sw_ena1,
copy_ena => copy_ena1,
etat => etat1
);
inst_switch2: switch
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_locked,
tc_divclk => tc_divclk,
rx => rx2_r2,
rx_dat => layer1_rx2,
rx_val => layer1_val2,
tx => tx1,
tx_dat => layer1_tx1,
tx_rd => layer1_rd1,
tx_empty => layer1_empty1,
sw_ena => sw_ena2,
copy_ena => copy_ena2,
etat => etat2
);
 
inst_layer2_rx1: layer2_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
ad_mio => tid,
dat_in => layer1_rx1,
val_in => layer1_val1,
dat_out => layer2_rx1,
val_out => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
sw_ena => sw_ena1
);
 
inst_layer2_rx2: layer2_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
ad_mio => tid,
dat_in => layer1_rx2,
val_in => layer1_val2,
dat_out => layer2_rx2,
val_out => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
sw_ena => sw_ena2
);
 
inst_frame_store1: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx1,
val_in => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
dat_out => layer7_rx1,
soc_out => layer7_soc1,
rd_datout => layer7_rd1,
new_frame => layer7_newframe1,
com_dispo => layer7_comdispo1,
l7_ok => layer7_l7ok1,
overflow => layer7_overflow1
);
inst_frame_store2: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx2,
val_in => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
dat_out => layer7_rx2,
soc_out => layer7_soc2,
rd_datout => layer7_rd2,
new_frame => layer7_newframe2,
com_dispo => layer7_comdispo2,
l7_ok => layer7_l7ok2,
overflow => layer7_overflow2
);
inst_comexec: com_exec
GENERIC MAP(
freq_clksys => 96,
reg_typemio => reg_typemio,
reg_version => reg_version,
ad_ref => ad_ref,
sz_ref => sz_ref
)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tid => tid,
iid => iid,
sync_lock => sync_lock,
datout_write=> datout_write,
datout_read => datout_read,
ad_out => ad_out,
wr_out => wr_out,
rd_out => rd_out,
activity1 => layer2_eof1,
activity2 => layer2_eof2,
datin1 => layer7_rx1,
socin1 => layer7_soc1,
rd_datin1 => layer7_rd1,
new_frame1 => layer7_newframe1,
com_dispo1 => layer7_comdispo1,
l7_ok1 => layer7_l7ok1,
l7_overflow1=> layer7_overflow1,
datin2 => layer7_rx2,
socin2 => layer7_soc2,
rd_datin2 => layer7_rd2,
new_frame2 => layer7_newframe2,
com_dispo2 => layer7_comdispo2,
l7_ok2 => layer7_l7ok2,
l7_overflow2=> layer7_overflow2,
datsent => tx_dat,
valsent => val_txdat,
sof => tx_sof,
eof => tx_eof,
datsent_free=> txdat_free,
clr_fifo_tx => clr_fifo_tx,
copy_ena1 => copy_ena1,
copy_ena2 => copy_ena2,
reload_fpgan=> reload_fpgan,
spitx_dat => spitx_dat,
spitx_val => spitx_val,
spirx_dat => spirx_dat,
spirx_val => spirx_val,
spirx_next => spirx_next,
spi_typecom => spi_typecom,
spi_execcom => spi_execcom,
spi_busy => spi_busy,
spi_nbread => spi_nbread,
spi_rstn => spi_rstn
);
 
inst_layer2_tx: layer2_tx
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => tx_dat,
val_in => val_txdat,
sof => tx_sof,
eof => tx_eof,
datin_free => txdat_free,
dat_out => layer2_txdat,
val_out => layer2_txval,
clr_fifo => clr_fifo_tx,
progfull1 => layer2_progfull1,
progfull2 => layer2_progfull2,
full1 => layer2_full1,
empty1 => layer1_empty1,
full2 => layer2_full2,
empty2 => layer1_empty2
);
inst_fifo_tx1 : fifo_tx
PORT MAP (
clk => clk_sys,
srst => clr_fifo_tx,
din => layer2_txdat,
wr_en => layer2_txval,
rd_en => layer1_rd1,
dout => layer1_tx1,
full => layer2_full1,
empty => layer1_empty1,
prog_full => layer2_progfull1
);
 
inst_fifo_tx2 : fifo_tx
PORT MAP (
clk => clk_sys,
srst => clr_fifo_tx,
din => layer2_txdat,
wr_en => layer2_txval,
rd_en => layer1_rd2,
dout => layer1_tx2,
full => layer2_full2,
empty => layer1_empty2,
prog_full => layer2_progfull2
);
inst_flash : if_promspi
GENERIC MAP (
div_rate => 3,
spiclk_freq => 12)
PORT MAP (
clk_sys => clk_sys,
rst_n => spi_rstn,
spi_csn => spi_csn,
spi_wpn => spi_wpn,
spi_sdo => spi_sdo,
spi_sdi => spi_sdi,
spi_clk => spi_clk,
tx_dat => spitx_dat,
tx_val => spitx_val,
rx_dat => spirx_dat,
rx_val => spirx_val,
rx_next => spirx_next,
type_com => spi_typecom,
exec_com => spi_execcom,
spi_busy => spi_busy,
nb_read => spi_nbread
);
 
END rtl;
 
/tags/Release IPCommunication v1.0/communication_sil.vhd
0,0 → 1,432
--=============================================================================
-- TITRE : COMMUNICATION_SIL
-- DESCRIPTION :
 
-- FICHIER : communication_sil.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
-- 18/09/14 DRA SATURN 1.1
-- Evolution du module switch (prise en compte du signal SW_ENA)
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY communication_sil IS
PORT (
 
 
 
ad_mio : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- TID du MIO
 
 
 
 
 
 
 
copy_ena1 : IN STD_LOGIC; -- Autorise la copy du port 1 sur le port 2
copy_ena2 : IN STD_LOGIC; -- Autorise la copy du port 2 sur le port 1
-- Interfaces de lecture des trames port 1
 
 
layer7_rd1 : IN STD_LOGIC; -- Signal de lecture d'un octet de plus
 
 
 
 
activity1 : OUT STD_LOGIC; -- Indique du trafic sur le port 1
-- Interfaces de lecture des trames port 2
layer7_rx2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1
layer7_soc2 : OUT STD_LOGIC;
layer7_rd2 : IN STD_LOGIC;
layer7_newframe2 : OUT STD_LOGIC;
layer7_comdispo2 : OUT STD_LOGIC;
layer7_l2ok2 : OUT STD_LOGIC;
layer7_overflow2 : OUT STD_LOGIC;
activity2 : OUT STD_LOGIC; -- Indique du trafic sur le port 2
 
 
 
val_txdat : IN STD_LOGIC; -- Indique un octet dispo sur tx_dat
 
tx_eof : IN STD_LOGIC; -- Indique une fin de trame
txdat_free : OUT STD_LOGIC; -- Indique que le module couche transport Tx est dispo
clr_fifo_tx : IN STD_LOGIC -- Clear de la FIFO transport Tx
);
END communication_sil;
 
ARCHITECTURE rtl of communication_sil is
 
 
CONSTANT nbbit_div : INTEGER := 11;
 
 
SIGNAL rx1_r1, rx1_r2 : STD_LOGIC;
SIGNAL rx2_r1, rx2_r2 : STD_LOGIC;
-- Diviseur d'horloge pour le baud rate
SIGNAL tc_divclk : STD_LOGIC_VECTOR(nbbit_div - 1 DOWNTO 0); -- Termianl count du diviseur
 
 
-- Interfaces du SWITCH1
 
SIGNAL layer1_val1 : STD_LOGIC; -- Indique un octet valide sur layer1_rx1
 
 
 
SIGNAL layer1_empty1 : STD_LOGIC; -- Indique qu'aucun octet n'est en attente de serialsiation
-- Interfaces du SWITCH2
SIGNAL layer1_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1
SIGNAL layer1_val2 : STD_LOGIC;
SIGNAL sw_ena2 : STD_LOGIC;
SIGNAL layer1_tx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL layer1_rd2 : STD_LOGIC;
SIGNAL layer1_empty2 : STD_LOGIC;
-- Interfaces du module LAYER2_RX1
 
SIGNAL layer2_rxval1 : STD_LOGIC; -- Indique un octet valide sur layer2_rx1
 
SIGNAL layer2_eof1 : STD_LOGIC; -- Indqiue une fin de trame
 
 
-- Interfaces du module LAYER2_RX2
SIGNAL layer2_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem que port 1
SIGNAL layer2_rxval2 : STD_LOGIC;
SIGNAL layer2_sof2 : STD_LOGIC;
SIGNAL layer2_eof2 : STD_LOGIC;
SIGNAL layer2_l2ok2 : STD_LOGIC;
 
-- Interfaces du module LAYER2_TX
 
SIGNAL layer2_txval : STD_LOGIC; -- Indique un octet valide sur layer2_txdat
 
 
 
 
COMPONENT autobaud
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
rx1 : IN STD_LOGIC;
val_rx1 : IN STD_LOGIC;
eof1 : IN STD_LOGIC;
dat_rx1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
l2_ok1 : IN STD_LOGIC;
rx2 : IN STD_LOGIC;
val_rx2 : IN STD_LOGIC;
eof2 : IN STD_LOGIC;
dat_rx2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
l2_ok2 : IN STD_LOGIC;
tc_divclk : OUT STD_LOGIC_VECTOR(10 downto 0);
baud_locked : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT switch
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
baud_lock : IN STD_LOGIC;
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
rx : IN STD_LOGIC;
rx_dat : OUT STD_LOGIC_VECTOR(7 downto 0);
rx_val : OUT STD_LOGIC;
tx : OUT STD_LOGIC;
tx_dat : IN STD_LOGIC_VECTOR(7 downto 0);
tx_rd : OUT STD_LOGIC;
tx_empty : IN STD_LOGIC;
sw_ena : IN STD_LOGIC;
copy_ena : IN STD_LOGIC;
etat : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT layer2_rx
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
ad_mio : IN STD_LOGIC_VECTOR(7 downto 0);
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
val_out : OUT STD_LOGIC;
sw_ena : OUT STD_LOGIC;
sof : OUT STD_LOGIC;
eof : OUT STD_LOGIC;
l2_ok : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT frame_store
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
sof : IN STD_LOGIC;
eof : IN STD_LOGIC;
l2_ok : IN STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
soc_out : OUT STD_LOGIC;
rd_datout : IN STD_LOGIC;
new_frame : OUT STD_LOGIC;
com_dispo : OUT STD_LOGIC;
l7_ok : OUT STD_LOGIC;
overflow : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT layer2_tx
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
sof : IN STD_LOGIC;
eof : IN STD_LOGIC;
datin_free : OUT STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
val_out : OUT STD_LOGIC;
clr_fifo : IN STD_LOGIC;
progfull1 : IN STD_LOGIC;
progfull2 : IN STD_LOGIC;
full1 : IN STD_LOGIC;
empty1 : IN STD_LOGIC;
full2 : IN STD_LOGIC;
empty2 : IN STD_LOGIC
);
END COMPONENT;
 
 
-- stockage avant overflow (voir le module layer2_tx)
COMPONENT fifo_tx
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full: OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--------------------------------------------
 
--------------------------------------------
meta : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
rx1_r1 <= '1';
rx1_r2 <= '1';
rx2_r1 <= '1';
rx2_r2 <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx1_r1 <= rx1;
rx1_r2 <= rx1_r1;
rx2_r1 <= rx2;
rx2_r2 <= rx2_r1;
END IF;
END PROCESS;
 
inst_autobaud: autobaud
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
rx1 => rx1_r2,
rx2 => rx2_r2,
val_rx1 => layer1_val1,
dat_rx1 => layer1_rx1,
eof1 => layer2_eof1,
l2_ok1 => layer2_l2ok1,
val_rx2 => layer1_val2,
dat_rx2 => layer1_rx2,
eof2 => layer2_eof2,
l2_ok2 => layer2_l2ok2,
tc_divclk => tc_divclk,
baud_locked => baud_locked
);
 
inst_switch1: switch
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_locked,
tc_divclk => tc_divclk,
rx => rx1_r2,
rx_dat => layer1_rx1,
rx_val => layer1_val1,
tx => tx2,
tx_dat => layer1_tx2,
tx_rd => layer1_rd2,
tx_empty => layer1_empty2,
sw_ena => sw_ena1,
copy_ena => copy_ena1,
etat => OPEN
);
inst_switch2: switch
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_locked,
tc_divclk => tc_divclk,
rx => rx2_r2,
rx_dat => layer1_rx2,
rx_val => layer1_val2,
tx => tx1,
tx_dat => layer1_tx1,
tx_rd => layer1_rd1,
tx_empty => layer1_empty1,
sw_ena => sw_ena2,
copy_ena => copy_ena2,
etat => OPEN
);
 
inst_layer2_rx1: layer2_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
ad_mio => ad_mio,
dat_in => layer1_rx1,
val_in => layer1_val1,
dat_out => layer2_rx1,
val_out => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
sw_ena => sw_ena1
);
activity1 <= layer2_eof1;
 
inst_layer2_rx2: layer2_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
ad_mio => ad_mio,
dat_in => layer1_rx2,
val_in => layer1_val2,
dat_out => layer2_rx2,
val_out => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
sw_ena => sw_ena2
);
activity2 <= layer2_eof2;
 
inst_frame_store1: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx1,
val_in => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
dat_out => layer7_rx1,
soc_out => layer7_soc1,
rd_datout => layer7_rd1,
new_frame => layer7_newframe1,
com_dispo => layer7_comdispo1,
l7_ok => layer7_l2ok1,
overflow => layer7_overflow1
);
inst_frame_store2: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx2,
val_in => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
dat_out => layer7_rx2,
soc_out => layer7_soc2,
rd_datout => layer7_rd2,
new_frame => layer7_newframe2,
com_dispo => layer7_comdispo2,
l7_ok => layer7_l2ok2,
overflow => layer7_overflow2
);
inst_layer2_tx: layer2_tx
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => tx_dat,
val_in => val_txdat,
sof => tx_sof,
eof => tx_eof,
datin_free => txdat_free,
dat_out => layer2_txdat,
val_out => layer2_txval,
clr_fifo => clr_fifo_tx,
progfull1 => layer2_progfull1,
progfull2 => layer2_progfull2,
full1 => layer2_full1,
empty1 => layer1_empty1,
full2 => layer2_full2,
empty2 => layer1_empty2
);
inst_fifo_tx1 : fifo_tx
PORT MAP (
clk => clk_sys,
srst => clr_fifo_tx,
din => layer2_txdat,
wr_en => layer2_txval,
rd_en => layer1_rd1,
dout => layer1_tx1,
full => layer2_full1,
empty => layer1_empty1,
prog_full => layer2_progfull1
);
 
inst_fifo_tx2 : fifo_tx
PORT MAP (
clk => clk_sys,
srst => clr_fifo_tx,
din => layer2_txdat,
wr_en => layer2_txval,
rd_en => layer1_rd2,
dout => layer1_tx2,
full => layer2_full2,
empty => layer1_empty2,
prog_full => layer2_progfull2
);
END rtl;
 
/tags/Release IPCommunication v1.0/communication_sil4.vhd
0,0 → 1,497
--=============================================================================
-- TITRE : COMMUNICATION_SIL4
-- DESCRIPTION :
 
-- FICHIER : communication_sil4.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY communication_sil4 IS
PORT (
 
 
 
ad_mio : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- TID du MIO
 
 
 
 
 
 
 
copy_ena1 : IN STD_LOGIC; -- Autorise la copy du port 1 sur le port 2
copy_ena2 : IN STD_LOGIC; -- Autorise la copy du port 2 sur le port 1
 
 
 
layer7_rd1_uc1 : IN STD_LOGIC; -- Signal de lecture d'un octet de plus
 
 
 
 
activity1 : OUT STD_LOGIC; -- Indique du trafic sur le port 1
 
layer7_rx2_uc1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1
layer7_soc2_uc1 : OUT STD_LOGIC;
layer7_rd2_uc1 : IN STD_LOGIC;
layer7_newframe2_uc1 : OUT STD_LOGIC;
layer7_comdispo2_uc1 : OUT STD_LOGIC;
layer7_l2ok2_uc1 : OUT STD_LOGIC;
layer7_overflow2_uc1 : OUT STD_LOGIC;
activity2 : OUT STD_LOGIC; -- Indique du trafic sur le port 2
 
 
 
layer7_rd1_uc2 : IN STD_LOGIC; -- Signal de lecture d'un octet de plus
 
 
 
 
 
layer7_rx2_uc2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1
layer7_soc2_uc2 : OUT STD_LOGIC;
layer7_rd2_uc2 : IN STD_LOGIC;
layer7_newframe2_uc2 : OUT STD_LOGIC;
layer7_comdispo2_uc2 : OUT STD_LOGIC;
layer7_l2ok2_uc2 : OUT STD_LOGIC;
layer7_overflow2_uc2 : OUT STD_LOGIC;
 
txdat_free : OUT STD_LOGIC; -- Indique que le module couche transport Tx est dispo
 
val_txdat_uc1 : IN STD_LOGIC; -- Indique un octet dispo sur tx_dat
 
tx_eof_uc1 : IN STD_LOGIC; -- Indique une fin de trame
clr_fifo_tx_uc1 : IN STD_LOGIC; -- Clear de la FIFO transport Tx
 
 
val_txdat_uc2 : IN STD_LOGIC; -- Indique un octet dispo sur tx_dat
 
tx_eof_uc2 : IN STD_LOGIC; -- Indique une fin de trame
clr_fifo_tx_uc2 : IN STD_LOGIC -- Clear de la FIFO transport Tx
);
END communication_sil4;
 
ARCHITECTURE rtl of communication_sil4 is
 
 
CONSTANT nbbit_div : INTEGER := 11;
 
 
SIGNAL rx1_r1, rx1_r2 : STD_LOGIC;
SIGNAL rx2_r1, rx2_r2 : STD_LOGIC;
-- Diviseur d'horloge pour le baud rate
SIGNAL tc_divclk : STD_LOGIC_VECTOR(nbbit_div - 1 DOWNTO 0); -- Termianl count du diviseur
 
 
-- Interfaces du SWITCH1
 
SIGNAL layer1_val1 : STD_LOGIC; -- Indique un octet valide sur layer1_rx1
 
 
 
SIGNAL layer1_empty1 : STD_LOGIC; -- Indique qu'aucun octet n'est en attente de serialsiation
-- Interfaces du SWITCH2
SIGNAL layer1_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1
SIGNAL layer1_val2 : STD_LOGIC;
SIGNAL sw_ena2 : STD_LOGIC;
SIGNAL layer1_tx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL layer1_rd2 : STD_LOGIC;
SIGNAL layer1_empty2 : STD_LOGIC;
-- Interfaces du module LAYER2_RX1
 
SIGNAL layer2_rxval1 : STD_LOGIC; -- Indique un octet valide sur layer2_rx1
 
SIGNAL layer2_eof1 : STD_LOGIC; -- Indqiue une fin de trame
 
 
-- Interfaces du module LAYER2_RX2
SIGNAL layer2_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem que port 1
SIGNAL layer2_rxval2 : STD_LOGIC;
SIGNAL layer2_sof2 : STD_LOGIC;
SIGNAL layer2_eof2 : STD_LOGIC;
SIGNAL layer2_l2ok2 : STD_LOGIC;
 
-- Interfaces du module LAYER2_TX
 
SIGNAL layer2_txval : STD_LOGIC; -- Indique un octet valide sur layer2_txdat
 
 
 
 
 
 
 
SIGNAL val_txdat : STD_LOGIC; -- Indique un octet dispo sur tx_dat
 
SIGNAL tx_eof : STD_LOGIC; -- Indique une fin de trame
SIGNAL clr_fifo_tx : STD_LOGIC; -- Clear de la FIFO transport Tx
 
COMPONENT autobaud
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
rx1 : IN STD_LOGIC;
val_rx1 : IN STD_LOGIC;
eof1 : IN STD_LOGIC;
dat_rx1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
l2_ok1 : IN STD_LOGIC;
rx2 : IN STD_LOGIC;
val_rx2 : IN STD_LOGIC;
eof2 : IN STD_LOGIC;
dat_rx2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
l2_ok2 : IN STD_LOGIC;
tc_divclk : OUT STD_LOGIC_VECTOR(10 downto 0);
baud_locked : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT switch
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
baud_lock : IN STD_LOGIC;
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
rx : IN STD_LOGIC;
rx_dat : OUT STD_LOGIC_VECTOR(7 downto 0);
rx_val : OUT STD_LOGIC;
tx : OUT STD_LOGIC;
tx_dat : IN STD_LOGIC_VECTOR(7 downto 0);
tx_rd : OUT STD_LOGIC;
tx_empty : IN STD_LOGIC;
sw_ena : IN STD_LOGIC;
copy_ena : IN STD_LOGIC;
etat : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT layer2_rx
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
ad_mio : IN STD_LOGIC_VECTOR(7 downto 0);
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
val_out : OUT STD_LOGIC;
sw_ena : OUT STD_LOGIC;
sof : OUT STD_LOGIC;
eof : OUT STD_LOGIC;
l2_ok : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT frame_store
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
sof : IN STD_LOGIC;
eof : IN STD_LOGIC;
l2_ok : IN STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
soc_out : OUT STD_LOGIC;
rd_datout : IN STD_LOGIC;
new_frame : OUT STD_LOGIC;
com_dispo : OUT STD_LOGIC;
l7_ok : OUT STD_LOGIC;
overflow : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT layer2_tx
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
sof : IN STD_LOGIC;
eof : IN STD_LOGIC;
datin_free : OUT STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
val_out : OUT STD_LOGIC;
clr_fifo : IN STD_LOGIC;
progfull1 : IN STD_LOGIC;
progfull2 : IN STD_LOGIC;
full1 : IN STD_LOGIC;
empty1 : IN STD_LOGIC;
full2 : IN STD_LOGIC;
empty2 : IN STD_LOGIC
);
END COMPONENT;
 
 
-- stockage avant overflow (voir le module layer2_tx)
COMPONENT fifo_tx
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full: OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--------------------------------------------
 
--------------------------------------------
meta : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
rx1_r1 <= '1';
rx1_r2 <= '1';
rx2_r1 <= '1';
rx2_r2 <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx1_r1 <= rx1;
rx1_r2 <= rx1_r1;
rx2_r1 <= rx2;
rx2_r2 <= rx2_r1;
END IF;
END PROCESS;
 
inst_autobaud: autobaud
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
rx1 => rx1_r2,
rx2 => rx2_r2,
val_rx1 => layer1_val1,
dat_rx1 => layer1_rx1,
eof1 => layer2_eof1,
l2_ok1 => layer2_l2ok1,
val_rx2 => layer1_val2,
dat_rx2 => layer1_rx2,
eof2 => layer2_eof2,
l2_ok2 => layer2_l2ok2,
tc_divclk => tc_divclk,
baud_locked => baud_locked
);
 
inst_switch1: switch
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_locked,
tc_divclk => tc_divclk,
rx => rx1_r2,
rx_dat => layer1_rx1,
rx_val => layer1_val1,
tx => tx2,
tx_dat => layer1_tx2,
tx_rd => layer1_rd2,
tx_empty => layer1_empty2,
sw_ena => sw_ena1,
copy_ena => copy_ena1,
etat => OPEN
);
inst_switch2: switch
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_locked,
tc_divclk => tc_divclk,
rx => rx2_r2,
rx_dat => layer1_rx2,
rx_val => layer1_val2,
tx => tx1,
tx_dat => layer1_tx1,
tx_rd => layer1_rd1,
tx_empty => layer1_empty1,
sw_ena => sw_ena2,
copy_ena => copy_ena2,
etat => OPEN
);
 
inst_layer2_rx1: layer2_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
ad_mio => ad_mio,
dat_in => layer1_rx1,
val_in => layer1_val1,
dat_out => layer2_rx1,
val_out => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
sw_ena => sw_ena1
);
activity1 <= layer2_eof1;
 
inst_layer2_rx2: layer2_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
ad_mio => ad_mio,
dat_in => layer1_rx2,
val_in => layer1_val2,
dat_out => layer2_rx2,
val_out => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
sw_ena => sw_ena2
);
activity2 <= layer2_eof2;
 
inst_frame_store1_uc1: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx1,
val_in => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
dat_out => layer7_rx1_uc1,
soc_out => layer7_soc1_uc1,
rd_datout => layer7_rd1_uc1,
new_frame => layer7_newframe1_uc1,
com_dispo => layer7_comdispo1_uc1,
l7_ok => layer7_l2ok1_uc1,
overflow => layer7_overflow1_uc1
);
inst_frame_store1_uc2: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx1,
val_in => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
dat_out => layer7_rx1_uc2,
soc_out => layer7_soc1_uc2,
rd_datout => layer7_rd1_uc2,
new_frame => layer7_newframe1_uc2,
com_dispo => layer7_comdispo1_uc2,
l7_ok => layer7_l2ok1_uc2,
overflow => layer7_overflow1_uc2
);
 
inst_frame_store2_uc1: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx2,
val_in => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
dat_out => layer7_rx2_uc1,
soc_out => layer7_soc2_uc1,
rd_datout => layer7_rd2_uc1,
new_frame => layer7_newframe2_uc1,
com_dispo => layer7_comdispo2_uc1,
l7_ok => layer7_l2ok2_uc1,
overflow => layer7_overflow2_uc1
);
inst_frame_store2_uc2: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx2,
val_in => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
dat_out => layer7_rx2_uc2,
soc_out => layer7_soc2_uc2,
rd_datout => layer7_rd2_uc2,
new_frame => layer7_newframe2_uc2,
com_dispo => layer7_comdispo2_uc2,
l7_ok => layer7_l2ok2_uc2,
overflow => layer7_overflow2_uc2
);
 
tx_dat <= tx_dat_uc1 WHEN (val_txdat_uc1 = '1') ELSE tx_dat_uc2;
val_txdat <= val_txdat_uc1 OR val_txdat_uc2;
tx_sof <= tx_sof_uc1 OR tx_sof_uc2;
tx_eof <= tx_eof_uc1 OR tx_eof_uc2;
clr_fifo_tx <= clr_fifo_tx_uc1 OR clr_fifo_tx_uc2;
 
inst_layer2_tx: layer2_tx
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => tx_dat,
val_in => val_txdat,
sof => tx_sof,
eof => tx_eof,
datin_free => txdat_free,
dat_out => layer2_txdat,
val_out => layer2_txval,
clr_fifo => clr_fifo_tx,
progfull1 => layer2_progfull1,
progfull2 => layer2_progfull2,
full1 => layer2_full1,
empty1 => layer1_empty1,
full2 => layer2_full2,
empty2 => layer1_empty2
);
inst_fifo_tx1 : fifo_tx
PORT MAP (
clk => clk_sys,
srst => clr_fifo_tx,
din => layer2_txdat,
wr_en => layer2_txval,
rd_en => layer1_rd1,
dout => layer1_tx1,
full => layer2_full1,
empty => layer1_empty1,
prog_full => layer2_progfull1
);
 
inst_fifo_tx2 : fifo_tx
PORT MAP (
clk => clk_sys,
srst => clr_fifo_tx,
din => layer2_txdat,
wr_en => layer2_txval,
rd_en => layer1_rd2,
dout => layer1_tx2,
full => layer2_full2,
empty => layer1_empty2,
prog_full => layer2_progfull2
);
END rtl;
 
/tags/Release IPCommunication v1.0/communication_sil4_filtre.vhd
0,0 → 1,543
--=============================================================================
-- TITRE : COMMUNICATION_SIL4
-- DESCRIPTION :
 
-- FICHIER : communication_sil4.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY communication_sil4 IS
PORT (
 
 
 
ad_mio : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- TID du MIO
 
ena_filt_dble : IN STD_LOGIC; -- Autorise le filtrage des trames en double
 
 
 
 
 
 
copy_ena1 : IN STD_LOGIC; -- Autorise la copy du port 1 sur le port 2
copy_ena2 : IN STD_LOGIC; -- Autorise la copy du port 2 sur le port 1
 
 
 
filt_rd1_uc1 : IN STD_LOGIC; -- Signal de lecture d'un octet de plus
 
 
 
 
activity1 : OUT STD_LOGIC; -- Indique du trafic sur le port 1
 
filt_rx2_uc1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1
filt_soc2_uc1 : OUT STD_LOGIC;
filt_rd2_uc1 : IN STD_LOGIC;
filt_comdispo2_uc1 : OUT STD_LOGIC;
layer7_newframe2 : OUT STD_LOGIC;
layer7_l2ok2 : OUT STD_LOGIC;
layer7_overflow2 : OUT STD_LOGIC;
activity2 : OUT STD_LOGIC; -- Indique du trafic sur le port 2
 
 
 
filt_rd1_uc2 : IN STD_LOGIC; -- Signal de lecture d'un octet de plus
 
 
filt_rx2_uc2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1
filt_soc2_uc2 : OUT STD_LOGIC;
filt_rd2_uc2 : IN STD_LOGIC;
filt_comdispo2_uc2 : OUT STD_LOGIC;
 
txdat_free : OUT STD_LOGIC; -- Indique que le module couche transport Tx est dispo
 
val_txdat_uc1 : IN STD_LOGIC; -- Indique un octet dispo sur tx_dat
 
tx_eof_uc1 : IN STD_LOGIC; -- Indique une fin de trame
clr_fifo_tx_uc1 : IN STD_LOGIC; -- Clear de la FIFO transport Tx
 
 
val_txdat_uc2 : IN STD_LOGIC; -- Indique un octet dispo sur tx_dat
 
tx_eof_uc2 : IN STD_LOGIC; -- Indique une fin de trame
clr_fifo_tx_uc2 : IN STD_LOGIC -- Clear de la FIFO transport Tx
);
END communication_sil4;
 
ARCHITECTURE rtl of communication_sil4 is
 
 
CONSTANT nbbit_div : INTEGER := 11;
 
 
SIGNAL rx1_r1, rx1_r2 : STD_LOGIC;
SIGNAL rx2_r1, rx2_r2 : STD_LOGIC;
-- Diviseur d'horloge pour le baud rate
SIGNAL tc_divclk : STD_LOGIC_VECTOR(nbbit_div - 1 DOWNTO 0); -- Termianl count du diviseur
 
 
-- Interfaces du SWITCH1
 
SIGNAL layer1_val1 : STD_LOGIC; -- Indique un octet valide sur layer1_rx1
 
 
 
SIGNAL layer1_empty1 : STD_LOGIC; -- Indique qu'aucun octet n'est en attente de serialsiation
-- Interfaces du SWITCH2
SIGNAL layer1_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1
SIGNAL layer1_val2 : STD_LOGIC;
SIGNAL sw_ena2 : STD_LOGIC;
SIGNAL layer1_tx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL layer1_rd2 : STD_LOGIC;
SIGNAL layer1_empty2 : STD_LOGIC;
-- Interfaces du module LAYER2_RX1
 
SIGNAL layer2_rxval1 : STD_LOGIC; -- Indique un octet valide sur layer2_rx1
 
SIGNAL layer2_eof1 : STD_LOGIC; -- Indqiue une fin de trame
 
 
-- Interfaces du module LAYER2_RX2
SIGNAL layer2_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem que port 1
SIGNAL layer2_rxval2 : STD_LOGIC;
SIGNAL layer2_sof2 : STD_LOGIC;
SIGNAL layer2_eof2 : STD_LOGIC;
SIGNAL layer2_l2ok2 : STD_LOGIC;
 
-- Interfaces du module FRAME_STORE1
 
 
SIGNAL layer7_rd1 : STD_LOGIC; -- Signal de elcture d'un octet de plus
SIGNAL layer7_comdispo1 : STD_LOGIC; -- Indique qu'au moins une trame est dispo
 
 
 
-- Interfaces du module FRAME_STORE2
 
 
SIGNAL layer7_rd2 : STD_LOGIC; -- Signal de elcture d'un octet de plus
SIGNAL layer7_comdispo2 : STD_LOGIC; -- Indique qu'au moins une trame est dispo
 
 
 
-- Interfaces du module LAYER2_TX
 
SIGNAL layer2_txval : STD_LOGIC; -- Indique un octet valide sur layer2_txdat
 
 
 
 
 
 
 
SIGNAL val_txdat : STD_LOGIC; -- Indique un octet dispo sur tx_dat
 
SIGNAL tx_eof : STD_LOGIC; -- Indique une fin de trame
SIGNAL clr_fifo_tx : STD_LOGIC; -- Clear de la FIFO transport Tx
 
COMPONENT autobaud
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
rx1 : IN STD_LOGIC;
val_rx1 : IN STD_LOGIC;
eof1 : IN STD_LOGIC;
dat_rx1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
l2_ok1 : IN STD_LOGIC;
rx2 : IN STD_LOGIC;
val_rx2 : IN STD_LOGIC;
eof2 : IN STD_LOGIC;
dat_rx2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
l2_ok2 : IN STD_LOGIC;
tc_divclk : OUT STD_LOGIC_VECTOR(10 downto 0);
baud_locked : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT switch
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
baud_lock : IN STD_LOGIC;
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
rx : IN STD_LOGIC;
rx_dat : OUT STD_LOGIC_VECTOR(7 downto 0);
rx_val : OUT STD_LOGIC;
tx : OUT STD_LOGIC;
tx_dat : IN STD_LOGIC_VECTOR(7 downto 0);
tx_rd : OUT STD_LOGIC;
tx_empty : IN STD_LOGIC;
sw_ena : IN STD_LOGIC;
copy_ena : IN STD_LOGIC;
etat : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT layer2_rx
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
ad_mio : IN STD_LOGIC_VECTOR(7 downto 0);
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
val_out : OUT STD_LOGIC;
sw_ena : OUT STD_LOGIC;
sof : OUT STD_LOGIC;
eof : OUT STD_LOGIC;
l2_ok : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT frame_store
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
sof : IN STD_LOGIC;
eof : IN STD_LOGIC;
l2_ok : IN STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
soc_out : OUT STD_LOGIC;
rd_datout : IN STD_LOGIC;
new_frame : OUT STD_LOGIC;
com_dispo : OUT STD_LOGIC;
l7_ok : OUT STD_LOGIC;
overflow : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT filter_dbl_frame_sil4 IS
PORT (
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
top_cycle : IN STD_LOGIC;
ena_filt_dble : IN STD_LOGIC;
data_port1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
soc_port1 : IN STD_LOGIC;
com_dispo1 : IN STD_LOGIC;
rd_port1 : OUT STD_LOGIC;
data_port2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
soc_port2 : IN STD_LOGIC;
com_dispo2 : IN STD_LOGIC;
rd_port2 : OUT STD_LOGIC;
data_filt1_uc1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
soc_filt1_uc1 : OUT STD_LOGIC;
frm_dispo_filt1_uc1 : OUT STD_LOGIC;
rd_filt1_uc1 : IN STD_LOGIC;
data_filt2_uc1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
soc_filt2_uc1 : OUT STD_LOGIC;
frm_dispo_filt2_uc1 : OUT STD_LOGIC;
rd_filt2_uc1 : IN STD_LOGIC;
data_filt1_uc2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
soc_filt1_uc2 : OUT STD_LOGIC;
frm_dispo_filt1_uc2 : OUT STD_LOGIC;
rd_filt1_uc2 : IN STD_LOGIC;
data_filt2_uc2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
soc_filt2_uc2 : OUT STD_LOGIC;
frm_dispo_filt2_uc2 : OUT STD_LOGIC;
rd_filt2_uc2 : IN STD_LOGIC;
dpram_overflow1 : OUT STD_LOGIC;
dpram_overflow2 : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT layer2_tx
PORT(
clk_sys : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
dat_in : IN STD_LOGIC_VECTOR(7 downto 0);
val_in : IN STD_LOGIC;
sof : IN STD_LOGIC;
eof : IN STD_LOGIC;
datin_free : OUT STD_LOGIC;
dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);
val_out : OUT STD_LOGIC;
clr_fifo : IN STD_LOGIC;
progfull1 : IN STD_LOGIC;
progfull2 : IN STD_LOGIC;
full1 : IN STD_LOGIC;
empty1 : IN STD_LOGIC;
full2 : IN STD_LOGIC;
empty2 : IN STD_LOGIC
);
END COMPONENT;
 
 
-- stockage avant overflow (voir le module layer2_tx)
COMPONENT fifo_tx
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full: OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--------------------------------------------
 
--------------------------------------------
meta : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
rx1_r1 <= '1';
rx1_r2 <= '1';
rx2_r1 <= '1';
rx2_r2 <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx1_r1 <= rx1;
rx1_r2 <= rx1_r1;
rx2_r1 <= rx2;
rx2_r2 <= rx2_r1;
END IF;
END PROCESS;
 
inst_autobaud: autobaud
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
rx1 => rx1_r2,
rx2 => rx2_r2,
val_rx1 => layer1_val1,
dat_rx1 => layer1_rx1,
eof1 => layer2_eof1,
l2_ok1 => layer2_l2ok1,
val_rx2 => layer1_val2,
dat_rx2 => layer1_rx2,
eof2 => layer2_eof2,
l2_ok2 => layer2_l2ok2,
tc_divclk => tc_divclk,
baud_locked => baud_locked
);
 
inst_switch1: switch
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_locked,
tc_divclk => tc_divclk,
rx => rx1_r2,
rx_dat => layer1_rx1,
rx_val => layer1_val1,
tx => tx2,
tx_dat => layer1_tx2,
tx_rd => layer1_rd2,
tx_empty => layer1_empty2,
sw_ena => sw_ena1,
copy_ena => copy_ena1,
etat => OPEN
);
inst_switch2: switch
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_locked,
tc_divclk => tc_divclk,
rx => rx2_r2,
rx_dat => layer1_rx2,
rx_val => layer1_val2,
tx => tx1,
tx_dat => layer1_tx1,
tx_rd => layer1_rd1,
tx_empty => layer1_empty1,
sw_ena => sw_ena2,
copy_ena => copy_ena2,
etat => OPEN
);
 
inst_layer2_rx1: layer2_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
ad_mio => ad_mio,
dat_in => layer1_rx1,
val_in => layer1_val1,
dat_out => layer2_rx1,
val_out => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
sw_ena => sw_ena1
);
activity1 <= layer2_eof1;
 
inst_layer2_rx2: layer2_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
ad_mio => ad_mio,
dat_in => layer1_rx2,
val_in => layer1_val2,
dat_out => layer2_rx2,
val_out => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
sw_ena => sw_ena2
);
activity2 <= layer2_eof2;
 
inst_frame_store1: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx1,
val_in => layer2_rxval1,
sof => layer2_sof1,
eof => layer2_eof1,
l2_ok => layer2_l2ok1,
dat_out => layer7_rx1,
soc_out => layer7_soc1,
rd_datout => layer7_rd1,
new_frame => layer7_newframe1,
com_dispo => layer7_comdispo1,
l7_ok => layer7_l2ok1,
overflow => layer7_overflow1
);
inst_frame_store2_uc1: frame_store
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => layer2_rx2,
val_in => layer2_rxval2,
sof => layer2_sof2,
eof => layer2_eof2,
l2_ok => layer2_l2ok2,
dat_out => layer7_rx2,
soc_out => layer7_soc2,
rd_datout => layer7_rd2,
new_frame => layer7_newframe2,
com_dispo => layer7_comdispo2,
l7_ok => layer7_l2ok2,
overflow => layer7_overflow2
);
inst_dble_filt : filter_dbl_frame_sil4
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
top_cycle => top_cycle,
ena_filt_dble => ena_filt_dble,
data_port1 => layer7_rx1,
soc_port1 => layer7_soc1,
com_dispo1 => layer7_comdispo1,
rd_port1 => layer7_rd1,
data_port2 => layer7_rx2,
soc_port2 => layer7_soc2,
com_dispo2 => layer7_comdispo2,
rd_port2 => layer7_rd2,
data_filt1_uc1 => filt_rx1_uc1,
soc_filt1_uc1 => filt_soc1_uc1,
frm_dispo_filt1_uc1=> filt_comdispo1_uc1,
rd_filt1_uc1 => filt_rd1_uc1,
data_filt2_uc1 => filt_rx2_uc1,
soc_filt2_uc1 => filt_soc2_uc1,
frm_dispo_filt2_uc1=> filt_comdispo2_uc1,
rd_filt2_uc1 => filt_rd2_uc1,
data_filt1_uc2 => filt_rx1_uc2,
soc_filt1_uc2 => filt_soc1_uc2,
frm_dispo_filt1_uc2=> filt_comdispo1_uc2,
rd_filt1_uc2 => filt_rd1_uc2,
data_filt2_uc2 => filt_rx2_uc2,
soc_filt2_uc2 => filt_soc2_uc2,
frm_dispo_filt2_uc2=> filt_comdispo2_uc2,
rd_filt2_uc2 => filt_rd2_uc2,
dpram_overflow1=> overflow_filter1,
dpram_overflow2=> overflow_filter2
);
 
 
tx_dat <= tx_dat_uc1 WHEN (val_txdat_uc1 = '1') ELSE tx_dat_uc2;
val_txdat <= val_txdat_uc1 OR val_txdat_uc2;
tx_sof <= tx_sof_uc1 OR tx_sof_uc2;
tx_eof <= tx_eof_uc1 OR tx_eof_uc2;
clr_fifo_tx <= clr_fifo_tx_uc1 OR clr_fifo_tx_uc2;
 
inst_layer2_tx: layer2_tx
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
dat_in => tx_dat,
val_in => val_txdat,
sof => tx_sof,
eof => tx_eof,
datin_free => txdat_free,
dat_out => layer2_txdat,
val_out => layer2_txval,
clr_fifo => clr_fifo_tx,
progfull1 => layer2_progfull1,
progfull2 => layer2_progfull2,
full1 => layer2_full1,
empty1 => layer1_empty1,
full2 => layer2_full2,
empty2 => layer1_empty2
);
inst_fifo_tx1 : fifo_tx
PORT MAP (
clk => clk_sys,
srst => clr_fifo_tx,
din => layer2_txdat,
wr_en => layer2_txval,
rd_en => layer1_rd1,
dout => layer1_tx1,
full => layer2_full1,
empty => layer1_empty1,
prog_full => layer2_progfull1
);
 
inst_fifo_tx2 : fifo_tx
PORT MAP (
clk => clk_sys,
srst => clr_fifo_tx,
din => layer2_txdat,
wr_en => layer2_txval,
rd_en => layer1_rd2,
dout => layer1_tx2,
full => layer2_full2,
empty => layer1_empty2,
prog_full => layer2_progfull2
);
END rtl;
 
/tags/Release IPCommunication v1.0/crc16.vhd
0,0 → 1,80
--=============================================================================
-- TITRE : CRC16
-- DESCRIPTION :
 
 
 
 
-- FICHIER : crc16.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY crc16 IS
GENERIC (
 
);
PORT (
 
 
 
 
 
 
val : IN STD_LOGIC; -- validant du bus data
init : IN STD_LOGIC; -- Initialise le caclul du CRC
 
 
);
END crc16;
 
ARCHITECTURE rtl of crc16 is
SIGNAL shifter : STD_LOGIC_VECTOR(15 downto 0); -- DFF pour le calcul du CRC
BEGIN
--------------------------------------------
 
--------------------------------------------
inst_crc : PROCESS(clk_sys, rst_n)
VARIABLE shift_temp : STD_LOGIC_VECTOR(15 downto 0); -- shifter temporaire pour traiter les 8 bits
VARIABLE mask : STD_LOGIC; -- Pour le XOR d'un bit de data avec CRC(15)
BEGIN
IF (rst_n = '0') THEN
shifter <= (others => '1');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (init = '1') THEN
 
ELSIF (val = '1') THEN
 
 
blc_bit : FOR i IN 0 to 7 LOOP -- On traite tous les bits un par un LSB first
mask := shift_temp(15) XOR data(i); -- Calcul de la valeur de feedback
 
shift_temp := (shift_temp(14 downto 0) & '0') XOR
(poly AND SXT(mask & mask, 16));
END LOOP;
 
END IF;
END IF;
END PROCESS;
blc_form : FOR i IN 0 to 7 GENERATE
BEGIN
-- remise en forme du CRC pour assurer que x^15 est transmis en premier
 
crc(7-i) <= NOT(shifter(i));
END GENERATE;
 
END rtl;
 
/tags/Release IPCommunication v1.0/dpram.vhd
0,0 → 1,149
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file dpram.vhd when simulating
-- the core, dpram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY dpram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END dpram;
 
ARCHITECTURE dpram_a OF dpram IS
-- synthesis translate_off
COMPONENT wrapped_dpram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
 
-- Configuration specification
FOR ALL : wrapped_dpram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 10,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 1024,
c_read_depth_b => 1024,
c_read_width_a => 9,
c_read_width_b => 9,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 1024,
c_write_depth_b => 1024,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "READ_FIRST",
c_write_width_a => 9,
c_write_width_b => 9,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_dpram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
 
END dpram_a;
/tags/Release IPCommunication v1.0/dpram.xco
0,0 → 1,108
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Fri Nov 14 11:18:09 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx25t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=dpram
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=READ_FIRST
CSET operating_mode_b=READ_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=9
CSET read_width_b=9
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=1024
CSET write_width_a=9
CSET write_width_b=9
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: a8454b98
/tags/Release IPCommunication v1.0/dpram_dbleframe.xco
0,0 → 1,108
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Oct 20 15:51:12 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx25t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=dpram_dbleframe
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=81
CSET read_width_b=81
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=256
CSET write_width_a=81
CSET write_width_b=81
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: 2596c2d7
/tags/Release IPCommunication v1.0/dpram_filt.xco
0,0 → 1,108
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed May 06 15:30:26 2015
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx25t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=dpram_filt
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=READ_FIRST
CSET operating_mode_b=READ_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=9
CSET read_width_b=9
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=4096
CSET write_width_a=9
CSET write_width_b=9
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: e21c7bca
/tags/Release IPCommunication v1.0/fifo_ckgclk.vhd
0,0 → 1,282
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_ckgclk.vhd when simulating
-- the core, fifo_ckgclk. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_ckgclk IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_ckgclk;
 
ARCHITECTURE fifo_ckgclk_a OF fifo_ckgclk IS
-- synthesis translate_off
COMPONENT wrapped_fifo_ckgclk
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
 
-- Configuration specification
FOR ALL : wrapped_fifo_ckgclk USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 5,
c_default_value => "BlankString",
c_din_width => 11,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 11,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 31,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 30,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 5,
c_rd_depth => 32,
c_rd_freq => 1,
c_rd_pntr_width => 5,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 5,
c_wr_depth => 32,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 5,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_ckgclk
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
 
END fifo_ckgclk_a;
/tags/Release IPCommunication v1.0/fifo_ckgclk.xco
0,0 → 1,217
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Mon Mar 31 14:45:41 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:8.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx25t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.2
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=fifo_ckgclk
CSET data_count=false
CSET data_count_width=5
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_handshake_flag_options_axis=false
CSET enable_handshake_flag_options_rach=false
CSET enable_handshake_flag_options_rdch=false
CSET enable_handshake_flag_options_wach=false
CSET enable_handshake_flag_options_wdch=false
CSET enable_handshake_flag_options_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=31
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=30
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=11
CSET input_depth=32
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=11
CSET output_depth=32
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=Empty
CSET programmable_empty_type_rach=Empty
CSET programmable_empty_type_rdch=Empty
CSET programmable_empty_type_wach=Empty
CSET programmable_empty_type_wdch=Empty
CSET programmable_empty_type_wrch=Empty
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=Full
CSET programmable_full_type_rach=Full
CSET programmable_full_type_rdch=Full
CSET programmable_full_type_wach=Full
CSET programmable_full_type_wdch=Full
CSET programmable_full_type_wrch=Full
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=5
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=5
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-14T07:12:32.000Z
# END Extra information
GENERATE
# CRC: 66369e4b
/tags/Release IPCommunication v1.0/fifo_copy.vhd
0,0 → 1,283
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_copy.vhd when simulating
-- the core, fifo_copy. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_copy IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_copy;
 
ARCHITECTURE fifo_copy_a OF fifo_copy IS
-- synthesis translate_off
COMPONENT wrapped_fifo_copy
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
 
-- Configuration specification
FOR ALL : wrapped_fifo_copy USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 1,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 0,
c_has_slave_ce => 0,
c_has_srst => 1,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 511,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 510,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_copy
PORT MAP (
clk => clk,
srst => srst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
overflow => overflow,
empty => empty
);
-- synthesis translate_on
 
END fifo_copy_a;
/tags/Release IPCommunication v1.0/fifo_copy.xco
0,0 → 1,213
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Nov 17 14:47:50 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx4
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=fifo_copy
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=511
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=510
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=8
CSET input_depth=512
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=8
CSET output_depth=512
CSET overflow_flag=true
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Synchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 2ff79dcc
/tags/Release IPCommunication v1.0/fifo_spi.vhd
0,0 → 1,280
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_spi.vhd when simulating
-- the core, fifo_spi. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_spi IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_spi;
 
ARCHITECTURE fifo_spi_a OF fifo_spi IS
-- synthesis translate_off
COMPONENT wrapped_fifo_spi
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
 
-- Configuration specification
FOR ALL : wrapped_fifo_spi USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 9,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 255,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 254,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 9,
c_rd_depth => 256,
c_rd_freq => 1,
c_rd_pntr_width => 8,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 9,
c_wr_depth => 256,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 8,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_spi
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
 
END fifo_spi_a;
/tags/Release IPCommunication v1.0/fifo_spi.xco
0,0 → 1,213
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Nov 17 14:59:06 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx4
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=fifo_spi
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=255
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=254
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=8
CSET input_depth=256
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=8
CSET output_depth=256
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 41b536fd
/tags/Release IPCommunication v1.0/fifo_tx.vhd
0,0 → 1,283
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_tx.vhd when simulating
-- the core, fifo_tx. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_tx IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END fifo_tx;
 
ARCHITECTURE fifo_tx_a OF fifo_tx IS
-- synthesis translate_off
COMPONENT wrapped_fifo_tx
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
 
-- Configuration specification
FOR ALL : wrapped_fifo_tx USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 0,
c_has_slave_ce => 0,
c_has_srst => 1,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 495,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 494,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_tx
PORT MAP (
clk => clk,
srst => srst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full
);
-- synthesis translate_on
 
END fifo_tx_a;
/tags/Release IPCommunication v1.0/fifo_tx.xco
0,0 → 1,213
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Nov 17 14:50:41 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx4
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=fifo_tx
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=495
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=494
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=8
CSET input_depth=512
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=8
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Synchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: df7c33c8
/tags/Release IPCommunication v1.0/fiforx_spi.vhd
0,0 → 1,283
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fiforx_spi.vhd when simulating
-- the core, fiforx_spi. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fiforx_spi IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END fiforx_spi;
 
ARCHITECTURE fiforx_spi_a OF fiforx_spi IS
-- synthesis translate_off
COMPONENT wrapped_fiforx_spi
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
 
-- Configuration specification
FOR ALL : wrapped_fiforx_spi USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 1,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx18",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 11,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fiforx_spi
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
data_count => data_count
);
-- synthesis translate_on
 
END fiforx_spi_a;
/tags/Release IPCommunication v1.0/fiforx_spi.xco
0,0 → 1,213
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Nov 17 14:55:57 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx4
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=fiforx_spi
CSET data_count=true
CSET data_count_width=11
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1023
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=1022
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=8
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=8
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=11
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=11
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 280656af
/tags/Release IPCommunication v1.0/fifotx_spi.vhd
0,0 → 1,283
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifotx_spi.vhd when simulating
-- the core, fifotx_spi. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifotx_spi IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END fifotx_spi;
 
ARCHITECTURE fifotx_spi_a OF fifotx_spi IS
-- synthesis translate_off
COMPONENT wrapped_fifotx_spi
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
 
-- Configuration specification
FOR ALL : wrapped_fifotx_spi USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 1,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx18",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 11,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifotx_spi
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
data_count => data_count
);
-- synthesis translate_on
 
END fifotx_spi_a;
/tags/Release IPCommunication v1.0/fifotx_spi.xco
0,0 → 1,213
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Tue Oct 06 06:54:22 2015
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx4
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=fifotx_spi
CSET data_count=true
CSET data_count_width=11
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1023
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=1022
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=8
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=8
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=11
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=11
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: ee3472c4
/tags/Release IPCommunication v1.0/flux_chgclk.vhd
0,0 → 1,90
--=============================================================================
-- TITRE : flux_chgclk
-- DESCRIPTION :
 
 
-- FICHIER : flux_chgclk.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
 
ENTITY flux_chgclk IS
PORT (
 
clks : IN STD_LOGIC; -- Clock du flux entrant
clkd : IN STD_LOGIC; -- Clock du flux sortant
 
datas : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux source
vals : IN STD_LOGIC; -- Validant du flux source
 
eofs : IN STD_LOGIC; -- Fin de trame du flux source
crcoks : IN STD_LOGIC; -- Signal de trame bonne pour flux source
 
datad : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem pour le flux destination
vald : OUT STD_LOGIC;
sofd : OUT STD_LOGIC;
eofd : OUT STD_LOGIC;
crcokd : OUT STD_LOGIC
);
END flux_chgclk;
 
ARCHITECTURE rtl of flux_chgclk is
 
SIGNAL vectout : STD_LOGIC_VECTOR(10 DOWNTO 0); -- Pour lire la FIFO
SIGNAL empty : STD_LOGIC; -- FIFO vide
 
 
COMPONENT fifo_ckgclk
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
 
vectin <= crcoks & eofs & sofs & datas;
wren <= vals OR eofs; -- Le VAL n'est pas actif pendant le EOF, on force wren pour le EOF soit dans la FIFO
 
inst_chgclk : fifo_ckgclk
PORT MAP(
rst => NOT(rst_n),
wr_clk => clks,
rd_clk => clkd,
din => vectin,
wr_en => wren,
rd_en => '1',
dout => vectout,
full => open,
empty => empty
);
 
 
crcokd <= vectout(10);
eofd <= vectout(9);
sofd <= vectout(8);
datad <= vectout(7 DOWNTO 0);
 
 
END rtl;
 
/tags/Release IPCommunication v1.0/frame_ana.vhd
0,0 → 1,468
--=============================================================================
-- TITRE : FRAME_ANA
-- DESCRIPTION :
 
 
 
 
 
-- FICHIER : frame_ana.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 29/02/2012 DRA CONCERTO V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity frame_ana is
PORT (
 
 
 
ad_mio : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Adress logique du MIO
-- Interfaces vers le le module LAYER2_RX
 
 
 
 
 
val_in : IN STD_LOGIC; -- Validant du bus dat_in
 
-- Interfaces vers le module COM_EXEC
 
soc_out : OUT STD_LOGIC; -- Indique que l'octet sur dat_out est le 1e d'une commande
rd_datout: IN STD_LOGIC; -- Signal de lecture d'un nouvel octet applicatif
new_frame: OUT STD_LOGIC; -- Indique qu'une nouvelle trame est disponible
 
l7_ok : OUT STD_LOGIC; -- Indique que la nouvelle trame est conforme du point de vue layer 7
overflow : OUT STD_LOGIC -- Indique un overflow du buffer de stockage des commandes
);
end frame_ana;
 
architecture rtl of frame_ana is
 
CONSTANT typ_nosec: STD_LOGIC_VECTOR(1 downto 0) := "01";
CONSTANT typ_sync : STD_LOGIC_VECTOR(1 downto 0) := "10";
CONSTANT typ_sup : STD_LOGIC_VECTOR(1 downto 0) := "11";
 
CONSTANT com_write: STD_LOGIC_VECTOR(1 downto 0) := "01";
CONSTANT com_read : STD_LOGIC_VECTOR(1 downto 0) := "10";
CONSTANT com_rdwr : STD_LOGIC_VECTOR(1 downto 0) := "11";
SIGNAL adread : STD_LOGIC_VECTOR(9 DOWNTO 0); -- Signal d'adresse pour la lecture
SIGNAL cpt_adread: STD_LOGIC_VECTOR(9 DOWNTO 0); -- Compteur d'adresse pour la lecture
 
 
 
 
 
SIGNAL dpram_dr : STD_LOGIC_VECTOR(8 DOWNTO 0); -- Pour fabriquer le vecteur de lecutre dans la DPRAM
 
SIGNAL soc_wr : STD_LOGIC; -- Indique le 1er octet d'une commande
 
 
SIGNAL crc : STD_LOGIC_VECTOR(15 downto 0);-- Valeur dynamique du crc
SIGNAL init_crc : STD_LOGIC; -- Initialise le calcul du CRC
 
 
 
TYPE layer7_type IS (idle_st, rectyp_st, destination_st, source_st, adrw_st, nrw_st,
dataw_st, crc1_st, crc2_st, crccheck_st, endok_st, endnok_st, abort_st);
SIGNAL fsm_layer7 : layer7_type;
 
-- Module de calcul du CRC16
COMPONENT crc16
GENERIC (
 
);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
data : IN std_logic_vector(7 downto 0);
val : IN std_logic;
init : IN std_logic;
crc : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT dpram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
begin
--------------------------------------------
-- Gestion du comtpeur d'adresse en lecture
--------------------------------------------
cptr : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cpt_adread <= (others => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_datout = '1') THEN
cpt_adread <= cpt_adread + 1;
END IF;
END IF;
END PROCESS;
 
adread <= cpt_adread WHEN (rd_datout = '0') ELSE cpt_adread+1;
 
 
com_dispo <= '0' WHEN (adread = old_adw) ELSE '1';
 
 
overflow_buf <= '1' WHEN (adwrite = cpt_adread-2) AND (wea(0) = '1') ELSE '0';
overflow <= overflow_buf;
--------------------------------------------
 
--------------------------------------------
man_fsm : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
old_adw <= (others => '0');
adwrite <= (others => '0');
fsm_layer7 <= idle_st;
soc_wr <= '0';
l7_ok <= '0';
new_frame <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_layer7 IS
WHEN idle_st =>
-- Etat transitoire d'initialisation de l'algo de traitement
 
 
l7_ok <= '0';
new_frame <= '0';
fsm_layer7 <= rectyp_st;
soc_wr <= '1'; -- Si on est ici, le prochain octet sera le premier de la commande
WHEN rectyp_st =>
-- Etat d'attente du 1er octet de la couche applicative
init_crc <= '0';
 
 
 
 
 
-- cas de plantage du FPGA
-- IF (eof = '1') THEN
 
-- fsm_layer7 <= abort_st;
-- ELS
IF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSIF (val_in = '1') THEN
 
IF (sof = '1') THEN
-- Si c'est bien le 1er octet de la trame
 
 
CASE dat_in(7 downto 6) IS
WHEN typ_sup =>
-- Si c'est une trame de supervision
IF (dat_in(5 downto 4) = "00") THEN
 
fsm_layer7 <= source_st; -- Le prochain octet sera l'@ source
ELSE
-- Si le champ COM n'est pas "00", c'est qu'il y'a une erreur
fsm_layer7 <= endnok_st;
END IF;
WHEN typ_sec =>
 
IF (dat_in(5 downto 4) /= rep_read) THEN
 
fsm_layer7 <= destination_st; -- Le prochain octet sera l'@ destination
ELSE
-- Si le champ COM est rep_read, c'est qu'il y'a une erreur
fsm_layer7 <= endnok_st;
END IF;
 
WHEN typ_nosec =>
 
IF (dat_in(5 downto 4) /= rep_read) THEN
 
fsm_layer7 <= source_st; -- Le prochain octet sera l'@ source
ELSE
-- Si le champ COM est rep_read, c'est qu'il y'a une erreur
fsm_layer7 <= endnok_st;
END IF;
 
WHEN typ_sync =>
-- Si c'est une trame de synchronisation
IF (dat_in(5 downto 4) = "10") THEN
 
fsm_layer7 <= source_st; -- Le prochain octet sera l'@ source
ELSE
-- Si le champ COM n'est pas "10", c'est qu'il y'a une erreur
fsm_layer7 <= endnok_st;
END IF;
 
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
 
WHEN destination_st =>
 
 
IF (eof = '1') THEN
 
fsm_layer7 <= abort_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSE
IF (val_in = '1') THEN
IF (dat_in = ad_mio) OR (dat_in = x"80") OR (dat_in = x"FF") THEN
 
fsm_layer7 <= source_st; -- Le prochain octet sera l'@ source
ELSE
 
 
fsm_layer7 <= endnok_st;
END IF;
END IF;
END IF;
 
WHEN source_st =>
-- Etat d'attente de l'octet @ source.
 
cpt_byte <= CONV_STD_LOGIC_VECTOR(9, cpt_byte'length);
IF (eof = '1') THEN
 
fsm_layer7 <= abort_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSE
IF (val_in = '1') THEN
 
IF (dat_in = x"81" OR dat_in = x"82") THEN
-- Si la source est bien un des 2 concentrateurs
CASE type_field IS
-- Selon le type de la trame
WHEN typ_sec | typ_nosec =>
 
 
WHEN typ_sync =>
-- Si c'est une trame de synchronisation
 
WHEN typ_sup =>
-- Si c'est une trame de supervision
fsm_layer7 <= dataw_st; -- On va recevoir les 9 octets correspondant
WHEN OTHERS =>
NULL;
END CASE;
ELSE
-- Si la source n'est pas un des 2 concentrateurs
 
END IF;
END IF;
END IF;
WHEN adrw_st =>
 
IF (eof = '1') THEN
 
fsm_layer7 <= abort_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSE
IF (val_in = '1') THEN
 
fsm_layer7 <= nrw_st; -- Le prochain octet sera un champ longeur
END IF;
END IF;
 
WHEN nrw_st =>
 
IF (eof = '1') THEN
 
fsm_layer7 <= abort_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSE
IF (val_in = '1') THEN
 
 
cpt_byte <= dat_in;
-- IF (com_field = com_write AND dat_in = x"00") THEN
IF (dat_in = x"00") THEN
 
fsm_layer7 <= endnok_st; -- La trame a un mauvais format
ELSE
IF (type_field = typ_sec AND com_field = com_read) THEN
 
fsm_layer7 <= crc1_st; -- Les champs suivants seront le CRC
ELSIF (type_field = typ_nosec AND com_field = com_read) THEN
 
fsm_layer7 <= endok_st; -- La trame est finie
ELSIF (com_field = com_rdwr) THEN
 
 
 
ELSE
 
 
END IF;
END IF;
END IF;
END IF;
 
WHEN dataw_st =>
 
-- de configuration de l'adresse MAC
IF (eof = '1') THEN
 
fsm_layer7 <= abort_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSE
IF (val_in = '1') THEN
 
 
IF (cpt_byte = CONV_STD_LOGIC_VECTOR(1, cpt_byte'length)) THEN
 
IF (type_field = typ_sec OR type_field = typ_sup) THEN
 
fsm_layer7 <= crc1_st; -- Il y'a un CRC
ELSE
 
 
fsm_layer7 <= endok_st; -- la trame est finie
END IF;
END IF;
END IF;
END IF;
WHEN crc1_st =>
-- Etat d'attente du 1er octet de CRC
IF (eof = '1') THEN
 
fsm_layer7 <= abort_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSE
IF (val_in = '1') THEN
fsm_layer7 <= crc2_st;
END IF;
END IF;
 
WHEN crc2_st =>
 
IF (eof = '1') THEN
 
fsm_layer7 <= abort_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSE
IF (val_in = '1') THEN
fsm_layer7 <= crccheck_st;
END IF;
END IF;
WHEN crccheck_st =>
 
IF (eof = '1') THEN
 
fsm_layer7 <= abort_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= endnok_st;
ELSE
IF (crc(15 downto 0) = x"E88B") THEN
fsm_layer7 <= endok_st;
ELSE
fsm_layer7 <= endnok_st;
END IF;
END IF;
 
WHEN endok_st =>
-- Le format de la couche applicative est correct
IF (eof = '1') THEN
-- On attend le sigal de fin de trame
new_frame <= '1'; -- On signale une nouvelle trame
 
IF (l2_ok = '0') THEN
adwrite <= old_adw; -- On ignore tout ce qu'on vient de copier dans la DPRAM en reprenant l'ancien pointeur
END IF;
fsm_layer7 <= idle_st;
END IF;
 
WHEN endnok_st =>
-- Le format de la couche applicative n'est pas correct
IF (eof = '1') THEN
-- On attend le signal de fin de trame
new_frame <= '1'; -- On signale une nouvelle trame
l7_ok <= '0'; -- dont le format n'est pas correct
adwrite <= old_adw; -- On ignore tout ce qu'on vient de copier dans la DPRAM en reprenant l'ancien pointeur
fsm_layer7 <= idle_st;
END IF;
 
WHEN abort_st =>
 
new_frame <= '1'; -- On signale une nouvelle trame
l7_ok <= '0'; -- dont le format n'est pas correct
adwrite <= old_adw; -- On ignore tout ce qu'on vient de copier dans la DPRAM en reprenant l'ancien pointeur
fsm_layer7 <= idle_st;
 
WHEN OTHERS =>
fsm_layer7 <= idle_st;
END CASE;
END IF;
END PROCESS;
 
--------------------------------------------
-- Calcul du crc16
--------------------------------------------
inst_crc16: crc16
GENERIC MAP (
 
)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
data => dat_in,
val => val_in,
init => init_crc,
crc => crc
);
 
 
 
 
 
inst_dpram : dpram
PORT MAP (
clka => clk_sys,
wea => wea,
addra => adwrite,
dina => dpram_dw,
clkb => clk_sys,
addrb => adread,
doutb => dpram_dr
);
end rtl;
 
/tags/Release IPCommunication v1.0/frame_store.vhd
0,0 → 1,179
--=============================================================================
-- TITRE : FRAME_STORE
-- DESCRIPTION :
 
 
 
 
 
-- FICHIER : frame_store.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
 
entity frame_store is
PORT (
 
 
 
 
-- Interfaces vers le le module LAYER2_RX
 
 
 
 
val_in : IN STD_LOGIC; -- Validant du bus dat_in
 
-- Interfaces vers le module interface PIC
 
soc_out : OUT STD_LOGIC; -- Indique que l'octet sur dat_out est le 1e d'une commande
rd_datout: IN STD_LOGIC; -- Signal de lecture d'un nouvel octet applicatif
new_frame: OUT STD_LOGIC; -- Indique qu'une nouvelle trame est disponible
 
l7_ok : OUT STD_LOGIC; -- Indique que la nouvelle trame est conforme du point de vue layer 7
overflow : OUT STD_LOGIC -- Indique un overflow du buffer de stockage des commandes
);
end frame_store;
 
architecture rtl of frame_store is
SIGNAL adread : STD_LOGIC_VECTOR(9 DOWNTO 0); -- Signal d'adresse pour la lecture en DPRAM
SIGNAL cpt_adread: STD_LOGIC_VECTOR(9 DOWNTO 0); -- Compteur d'adresse pour la lecture en DPRAM
 
 
 
 
SIGNAL dpram_dr : STD_LOGIC_VECTOR(8 DOWNTO 0); -- Vecteur de lecture dans la DPRAM
 
 
 
 
TYPE layer7_type IS (idle_st, recdat_st, overflow_st);
SIGNAL fsm_layer7 : layer7_type;
 
COMPONENT dpram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
begin
--------------------------------------------
-- Gestion du comtpeur d'adresse en lecture
--------------------------------------------
cptr : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cpt_adread <= (others => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rd_datout = '1') THEN
-- Sur chaue ordre de lecture
 
END IF;
END IF;
END PROCESS;
-- Le pointeur de lecture en DPRAM est soit le compteur, soit la location suiante
 
adread <= cpt_adread WHEN (rd_datout = '0') ELSE cpt_adread+1;
 
 
com_dispo <= '0' WHEN (cpt_adread = old_adw) ELSE '1';
 
 
overflow_buf <= '1' WHEN (adwrite = cpt_adread-4) AND (wea(0) = '1') ELSE '0';
overflow <= overflow_buf;
--------------------------------------------
 
--------------------------------------------
man_fsm : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
old_adw <= (others => '0');
adwrite <= (others => '0');
fsm_layer7 <= idle_st;
l7_ok <= '0';
new_frame <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_layer7 IS
WHEN idle_st =>
l7_ok <= '0';
new_frame <= '0';
 
IF (val_in = '1' AND sof = '1') THEN
 
 
fsm_layer7 <= recdat_st;
END IF;
WHEN recdat_st =>
 
IF (eof = '1') THEN
 
new_frame <= '1'; -- On signale une nouvelle trame au module suivant
l7_ok <= l2_ok; -- Si le format de la couche 2 est correct, la trame est bonne
IF (l2_ok = '1') THEN
-- Si la trame est bonne
adwrite <= adwrite-2;-- On supprime les 2 derniers octets qui sont le CRC du layer 2
ELSE
-- Si la trame es tmauvaise (l2_ok = '0')
 
END IF;
fsm_layer7 <= idle_st;
ELSIF (overflow_buf = '1') THEN
fsm_layer7 <= overflow_st;
ELSIF (val_in = '1') THEN
 
 
END IF;
 
WHEN overflow_st =>
-- On a eu un overflow
IF (eof = '1') THEN
-- On attend le signal de fin de trame
 
 
 
fsm_layer7 <= idle_st;
END IF;
WHEN OTHERS =>
fsm_layer7 <= idle_st;
END CASE;
END IF;
END PROCESS;
 
 
 
 
 
inst_dpram : dpram
PORT MAP (
clka => clk_sys,
wea => wea,
addra => adwrite,
dina => dpram_dw,
clkb => clk_sys,
addrb => adread,
doutb => dpram_dr
);
end rtl;
 
/tags/Release IPCommunication v1.0/if_picspi.backup.vhd
0,0 → 1,655
--=============================================================================
-- TITRE : IF_PICSPI
-- DESCRIPTION :
 
 
 
-- FICHIER : if_picspi.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 29/02/2012 DRA CONCERTO V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
ENTITY if_picspi IS
GENERIC (
version : STD_LOGIC_VECTOR(7 DOWNTO 0));
PORT (
 
 
 
 
-- Interface SPI
sclk : IN STD_LOGIC; -- Clock SPI
sdi : IN STD_LOGIC; -- Bit IN SPI
sdo : OUT STD_LOGIC; -- Bit OUT SPI
ssn : IN STD_LOGIC; -- CSn SPI
 
-- Interface avec les autres modules du FPGA
-- Tous ces signaux sont synchrones de clk_sys
-- Signaux de configurations
iid : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- Identifiant IID du FPGA
tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Identifiant TID du FPGA
cpy1 : OUT STD_LOGIC; -- Autorise la recopie du port 1 sur port 2
cpy2 : OUT STD_LOGIC; -- Autorise la recopie du port 2 sur port 1
repli : OUT STD_LOGIC; -- Indique que le module est en repli (gestion des LED)
-- Interfaces de lecture des trames port 1
 
 
 
l7_comdispo1 : IN STD_LOGIC; -- Indique qu'il y'a au moins une trame de dispo
 
l7_l2ok1 : IN STD_LOGIC; -- Indique si la couche transport est bonne ou non
 
-- Interfaces de lecture des trames port 2
 
 
 
l7_comdispo2 : IN STD_LOGIC; -- Indique qu'il y'a au moins une trame de dispo
 
l7_l2ok2 : IN STD_LOGIC; -- Indique si la couche transport est bonne ou non
 
 
 
 
val_txdat : OUT STD_LOGIC; -- Validant de chaque octet
 
tx_eof : OUT STD_LOGIC; -- Indique la fin d'une trame
txdat_free : IN STD_LOGIC; -- Indique que la couche transport en tx est libre
clr_fifo_tx : OUT STD_LOGIC; -- Permet de purger les FIFO Tx
-- Gestion de l'interface SPI PROM
txprom_dat : OUT STD_LOGIC_VECTOR(7 downto 0);
txprom_val : OUT STD_LOGIC;
rxprom_dat : IN STD_LOGIC_VECTOR(7 downto 0);
rxprom_val : IN STD_LOGIC;
rxprom_next : OUT STD_LOGIC;
prom_type_com: OUT STD_LOGIC;
prom_exec_com: OUT STD_LOGIC;
prom_busy : IN STD_LOGIC;
prom_nbread : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
prom_rstn : OUT STD_LOGIC
);
END if_picspi;
 
ARCHITECTURE rtl of if_picspi is
TYPE fsmtx_state IS (idle_st, senddat_st);
SIGNAL fsm_tx : fsmtx_state;
 
TYPE fsmrx_state IS (idle_st, pump_st, recdat_st, waitnotempty_st);
SIGNAL fsm_rx : fsmrx_state;
 
 
CONSTANT adreg_iid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 7);
CONSTANT adreg_tid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(8, 7);
CONSTANT adreg_ctl : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(9, 7);
CONSTANT adreg_stat : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(10, 7);
CONSTANT adreg_rxsize1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(11, 7);
CONSTANT adreg_rxsize2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(12, 7);
CONSTANT adreg_txfree : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(13, 7);
CONSTANT adreg_fiforx1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(14, 7);
CONSTANT adreg_fiforx2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(15, 7);
CONSTANT adreg_fifotx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(16, 7);
CONSTANT adreg_version : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(17, 7);
CONSTANT adreg_promtx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(18, 7);
CONSTANT adreg_promrx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(19, 7);
CONSTANT adreg_promctl : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(20, 7);
CONSTANT adreg_promnbrd : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(21, 7);
 
SIGNAL reg_tid_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_ctl_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_stat_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_rx1size_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_rx2size_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_txfree_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_fiforx1_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_fiforx2_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
-- Signaux de gestion de l'interface SPI
SIGNAL cpt_bitspi : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Compte le nombre de bits sur un cycle SPI
 
 
 
SIGNAL dat_adn : STD_LOGIC; -- Indique si l'octet en cours sur SPI est une data ou l'adresse
 
 
SIGNAL spi_encours : STD_LOGIC;
 
SIGNAL wr_reg : STD_LOGIC; -- 1 Pulse pour lire le registre adwr_spi
 
 
-- Signaux de gestion interne et changement d'horloge
SIGNAL bfo1 : STD_LOGIC;
SIGNAL bfo2 : STD_LOGIC;
SIGNAL ovf1_spi: STD_LOGIC;
SIGNAL ovf2_spi: STD_LOGIC;
SIGNAL bfo1_spi: STD_LOGIC;
SIGNAL bfo2_spi: STD_LOGIC;
SIGNAL cpy1_reg : STD_LOGIC;
SIGNAL cpy2_reg : STD_LOGIC;
SIGNAL tid_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL repli_reg: STD_LOGIC;
 
SIGNAL difftx_free : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL fifotx_datacnt: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL wr_datatx_spi : STD_LOGIC;
SIGNAL rd_datatx_sys : STD_LOGIC;
SIGNAL datatx_rd_sys : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL fifotx_empty : STD_LOGIC;
SIGNAL rst_fifotx : STD_LOGIC;
SIGNAL cpt_tx : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL fiforx_datacnt1: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL rd_datarx_spi1 : STD_LOGIC;
SIGNAL fiforx_empty1 : STD_LOGIC;
SIGNAL firx_e1_r1 : STD_LOGIC;
SIGNAL firx_e1_r2 : STD_LOGIC;
 
SIGNAL fiforx_datacnt2: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL rd_datarx_spi2 : STD_LOGIC;
SIGNAL fiforx_empty2 : STD_LOGIC;
SIGNAL firx_e2_r1 : STD_LOGIC;
SIGNAL firx_e2_r2 : STD_LOGIC;
 
SIGNAL l7_rd : STD_LOGIC;
SIGNAL l7_rd1buf : STD_LOGIC;
SIGNAL l7_rd2buf : STD_LOGIC;
SIGNAL sel_voie : STD_LOGIC;
SIGNAL frm2 : STD_LOGIC;
SIGNAL frm2_r1 : STD_LOGIC;
SIGNAL frm2_r2 : STD_LOGIC;
SIGNAL frm1 : STD_LOGIC;
SIGNAL frm1_r1 : STD_LOGIC;
SIGNAL frm1_r2 : STD_LOGIC;
SIGNAL comdispo : STD_LOGIC;
SIGNAL soc : STD_LOGIC;
 
SIGNAL reg_promctl : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_promnbrd : STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT jk_chgclk
PORT (
 
clk1 : IN STD_LOGIC; -- Horloge principale 1
clk2 : IN STD_LOGIC; -- Horloge principale 2
 
pulseout : OUT STD_LOGIC -- Pulse sur clk2 sur front montant de pulse1
);
END COMPONENT;
 
COMPONENT fifotx_spi
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
COMPONENT fiforx_spi
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
--------------------------------------------
-- Process de gestion du SPI
--------------------------------------------
sdo <= shifter_spitx(7);
rd_reg <= (dat_adn AND rwn_spi AND NOT(ssn)) WHEN (cpt_bitspi = "111" AND spi_encours = '1') ELSE
NOT(ssn) WHEN spi_encours = '0' ELSE
'0';
wr_reg <= (spi_encours AND dat_adn AND NOT(rwn_spi)) WHEN (cpt_bitspi = "111") ELSE '0';
 
serrx_spi : PROCESS(sclk, rst_n)
BEGIN
IF (rst_n = '0') THEN
cpt_bitspi <= (OTHERS => '0');
adrd_spi <= (OTHERS => '0');
adwr_spi <= (OTHERS => '0');
rwn_spi <= '0';
dat_adn <= '0';
shifter_spirx <= (OTHERS => '0');
spi_encours <= '0';
ELSIF (sclk'EVENT and sclk = '1') THEN
IF (spi_encours = '1' AND ssn = '0') THEN
-- Si une transaction SPI est en cours et temps qu'elle est en cours (ssn = '0')
 
 
IF (cpt_bitspi = "110") THEN
 
IF (dat_adn = '0') THEN
-- Si c'est le 1er octet de la trame SPI
IF (sdi = '1') THEN
 
END IF;
 
 
ELSE
adwr_spi <= adrd_spi;
IF (adrd_spi /= adreg_fiforx1 AND
adrd_spi /= adreg_fiforx2 AND
adrd_spi /= adreg_fifotx AND
adrd_spi /= adreg_promtx AND
adrd_spi /= adreg_promrx) THEN
 
adrd_spi <= adrd_spi + 1;
END IF;
END IF;
ELSIF (cpt_bitspi = "111") THEN
 
dat_adn <= '1';
END IF;
ELSE
-- Si une transaction n'est pas en cours
IF (ssn = '0') THEN
 
 
dat_adn <= '0'; -- Le prochain octet sera celui de l'adresse
 
 
ELSE
 
adrd_spi <= adreg_stat;
END IF;
END IF;
END IF;
END PROCESS;
 
sertx_spi : PROCESS(sclk, rst_n)
BEGIN
IF (rst_n = '0') THEN
shifter_spitx <= (OTHERS => '0');
ELSIF (sclk'EVENT and sclk = '0') THEN
IF (spi_encours = '1' AND ssn = '0') THEN
-- Si une transaction SPI est en cours et temps qu'elle est en cours (ssn = '0')
IF (cpt_bitspi = "111") THEN
 
 
ELSE
 
shifter_spitx <= shifter_spitx(6 DOWNTO 0) & '0';
END IF;
ELSE
-- Si une transaction n'est pas en cours
IF (ssn = '0') THEN
 
END IF;
END IF;
END IF;
END PROCESS;
--------------------------------------------
-- Process Combinatoire de gestion du Read (MUX)
--------------------------------------------
mux_read: PROCESS(adrd_spi, iid, reg_tid_spi, reg_ctl_spi, reg_stat_spi, reg_rx1size_spi, reg_rx2size_spi,
reg_txfree_spi, reg_fiforx1_spi, reg_fiforx2_spi, rxprom_val, reg_promnbrd, rxprom_dat, reg_promctl)
BEGIN
CASE adrd_spi IS
WHEN adreg_iid => data_rdspi <= iid(63 DOWNTO 56);
WHEN adreg_iid+1 => data_rdspi <= iid(55 DOWNTO 48);
WHEN adreg_iid+2 => data_rdspi <= iid(47 DOWNTO 40);
WHEN adreg_iid+3 => data_rdspi <= iid(39 DOWNTO 32);
WHEN adreg_iid+4 => data_rdspi <= iid(31 DOWNTO 24);
WHEN adreg_iid+5 => data_rdspi <= iid(23 DOWNTO 16);
WHEN adreg_iid+6 => data_rdspi <= iid(15 DOWNTO 8);
WHEN adreg_iid+7 => data_rdspi <= iid(7 DOWNTO 0);
WHEN adreg_tid => data_rdspi <= reg_tid_spi;
WHEN adreg_ctl => data_rdspi <= reg_ctl_spi;
WHEN adreg_stat => data_rdspi <= reg_stat_spi;
WHEN adreg_rxsize1=> data_rdspi <= reg_rx1size_spi;
WHEN adreg_rxsize2=> data_rdspi <= reg_rx2size_spi;
WHEN adreg_txfree => data_rdspi <= reg_txfree_spi;
WHEN adreg_fiforx1=> data_rdspi <= reg_fiforx1_spi;
WHEN adreg_fiforx2=> data_rdspi <= reg_fiforx2_spi;
-- WHEN adreg_fifotx => data_rdspi <= dummy -- Ce registre est Write Only
WHEN adreg_version=> data_rdspi <= version;
WHEN adreg_promctl=> data_rdspi <= rxprom_val & reg_promctl(6 DOWNTO 4) & prom_busy & reg_promctl(2 DOWNTO 0);
WHEN adreg_promnbrd=>data_rdspi <= reg_promnbrd;
-- WHEN adreg_promtx => data_rdspi <= dummy -- Ce registre est Write Only
WHEN adreg_promrx=> data_rdspi <= rxprom_dat;
WHEN OTHERS => data_rdspi <= reg_stat_spi;
END CASE;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
write_reg : PROCESS(sclk, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_tid_spi <= x"8F";
reg_ctl_spi <= x"87";
ELSIF (sclk'EVENT and sclk = '1') THEN
IF (wr_reg = '1') THEN
CASE adwr_spi IS
WHEN adreg_tid => reg_tid_spi <= shifter_spirx;
WHEN adreg_ctl => reg_ctl_spi <= shifter_spirx;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
rst_fifotx <= reg_ctl_spi(2);
 
--------------------------------------------
-- Process de gestion du registre de status
--------------------------------------------
gest_stat : PROCESS(sclk, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_stat_spi(7 DOWNTO 2) <= (OTHERS => '0');
frm1_r1 <= '0';
frm1_r2 <= '0';
frm2_r1 <= '0';
frm2_r2 <= '0';
ELSIF (sclk'EVENT and sclk = '1') THEN
 
frm1_r2 <= frm1_r1;
frm2_r1 <= frm2;
frm2_r2 <= frm2_r1;
IF (bfo1_spi = '1') THEN
reg_stat_spi(2) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(2) <= reg_stat_spi(2) AND NOT(shifter_spirx(2));
END IF;
IF (bfo2_spi = '1') THEN
reg_stat_spi(3) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(3) <= reg_stat_spi(3) AND NOT(shifter_spirx(3));
END IF;
IF (ovf1_spi = '1') THEN
reg_stat_spi(4) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(4) <= reg_stat_spi(4) AND NOT(shifter_spirx(4));
END IF;
IF (ovf2_spi = '1') THEN
reg_stat_spi(5) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(5) <= reg_stat_spi(5) AND NOT(shifter_spirx(5));
END IF;
END IF;
END PROCESS;
reg_stat_spi(1 DOWNTO 0) <= frm2_r2 & frm1_r2;
--------------------------------------------
-- Process de gestion des changement d'horloge
--------------------------------------------
 
 
clkovf1 : jk_chgclk PORT MAP(rst_n, clk_sys, sclk, l7_overflow1, ovf1_spi);
clkovf2 : jk_chgclk PORT MAP(rst_n, clk_sys, sclk, l7_overflow2, ovf2_spi);
clkobfo1: jk_chgclk PORT MAP(rst_n, clk_sys, sclk, bfo1, bfo1_spi);
clkobfo2: jk_chgclk PORT MAP(rst_n, clk_sys, sclk, bfo2, bfo2_spi);
 
to_clk_sys : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cpy1_reg <= '1';
cpy2_reg <= '1';
repli_reg <= '1';
cpy1 <= '1';
cpy2 <= '1';
repli <= '1';
ELSIF (clk_sys'event AND clk_sys ='1') THEN
cpy1_reg <= reg_ctl_spi(0);
cpy2_reg <= reg_ctl_spi(1);
tid_reg <= reg_tid_spi;
repli_reg<= reg_ctl_spi(7);
cpy1 <= cpy1_reg;
cpy2 <= cpy2_reg;
tid <= tid_reg;
repli<= repli_reg;
END IF;
END PROCESS;
--------------------------------------------
-- Process de gestion de la FIFO Tx
--------------------------------------------
difftx_free <= "10000000001" - fifotx_datacnt; -- Calcul du nombre d'octets dispo dans la FIFO 257-cnt
 
 
 
 
wr_datatx_spi <= '1' WHEN (wr_reg = '1' AND adwr_spi = adreg_fifotx) ELSE '0';
clr_fifo_tx <= '0'; -- Spare pour l'instant on ne fait pas de clear de la fifo tx aval
 
 
-- ou bien en cours de transfert lorsque le module suivant est dispo
rd_datatx_sys <= '1' WHEN ((fsm_tx = idle_st AND fifotx_empty = '0') OR
(fsm_tx = senddat_st AND txdat_free = '1' AND fifotx_empty = '0')) ELSE
'0';
 
val_txdat <= NOT(fifotx_empty);
tx_dat <= datatx_rd_sys;
tx_eof <= txdat_free AND NOT(fifotx_empty) WHEN (fsm_tx = senddat_st AND cpt_tx = "00000001") ELSE '0';
 
gest_fsm_tx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_tx <= idle_st;
tx_sof <= '0';
cpt_tx <= (OTHERS => '0');
 
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_tx IS
WHEN idle_st =>
 
IF (fifotx_empty = '0') THEN
 
cpt_tx <= datatx_rd_sys; -- On initialise le compteur avec la longueur de la trame
 
 
END IF;
 
WHEN senddat_st =>
 
IF (txdat_free = '1' AND fifotx_empty = '0') THEN
 
 
cpt_tx <= cpt_tx - 1; -- Dans ce cas on enregistre une donnee de moins
tx_sof <= '0'; -- On peut annuler le sof car on est sur que le module suivant l'a pris en comtpe
 
fsm_tx <= idle_st; -- On a fini
END IF;
END IF;
WHEN OTHERS =>
fsm_tx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fiftx : fifotx_spi
PORT MAP (
rst => rst_fifotx,
wr_clk => sclk,
rd_clk => clk_sys,
din => shifter_spirx,
wr_en => wr_datatx_spi,
rd_en => rd_datatx_sys,
dout => datatx_rd_sys,
full => OPEN,
empty => fifotx_empty,
wr_data_count => fifotx_datacnt
);
--------------------------------------------
-- Process de gestion des FIFO Rx
--------------------------------------------
rd_datarx_spi1 <= '1' WHEN (rd_reg = '1' AND adrd_spi = adreg_fiforx1) ELSE '0';
rd_datarx_spi2 <= '1' WHEN (rd_reg = '1' AND adrd_spi = adreg_fiforx2) ELSE '0';
 
l7_rd1buf <= (l7_rd AND NOT(sel_voie) AND comdispo AND NOT(soc)) WHEN (fsm_rx = recdat_st) ELSE
(l7_rd AND NOT(sel_voie));
l7_rd1 <= l7_rd1buf;
l7_rd2buf <= (l7_rd AND sel_voie AND comdispo AND NOT(soc)) WHEN (fsm_rx = recdat_st) ELSE
(l7_rd AND sel_voie);
l7_rd2 <= l7_rd2buf;
comdispo <= l7_comdispo1 WHEN (sel_voie = '0') ELSE l7_comdispo2;
soc <= l7_soc1 WHEN (sel_voie = '0') ELSE l7_soc2;
 
gest_fsm_rx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
l7_rd <= '0';
sel_voie <= '0';
fsm_rx <= idle_st;
frm2 <= '0';
frm1 <= '0';
firx_e1_r1 <= '0';
firx_e1_r2 <= '0';
firx_e2_r1 <= '0';
firx_e2_r2 <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
firx_e1_r1 <= fiforx_empty1; -- Passe les FIFO empty sur la clok_sys
firx_e1_r2 <= firx_e1_r1;
firx_e2_r1 <= fiforx_empty2;
firx_e2_r2 <= firx_e2_r1;
CASE fsm_rx IS
WHEN idle_st =>
frm1 <= NOT(firx_e1_r2);
frm2 <= NOT(firx_e2_r2);
IF ((l7_comdispo1 = '1' AND firx_e1_r2 = '1') AND
(l7_comdispo2 = '0' OR firx_e2_r2 = '0' OR sel_voie = '1')) THEN
sel_voie <= '0';
l7_rd <= '1';
fsm_rx <= pump_st;
ELSIF (l7_comdispo2 = '1' AND firx_e2_r2 = '1') THEN
sel_voie <= '1';
l7_rd <= '1';
fsm_rx <= pump_st;
ELSE
l7_rd <= '0';
END IF;
WHEN pump_st =>
fsm_rx <= recdat_st;
 
WHEN recdat_st =>
IF (soc = '1' OR comdispo = '0') THEN
l7_rd <= '0';
fsm_rx <= waitnotempty_st;
END IF;
WHEN waitnotempty_st =>
 
-- Necessaire du fait de la latence entre sclk et clk_sys
IF ((firx_e1_r2 = '0' AND sel_voie = '0') OR
(firx_e2_r2 = '0' AND sel_voie = '1')) THEN
frm1 <= NOT(sel_voie);
frm2 <= sel_voie;
fsm_rx <= idle_st;
END IF;
 
WHEN OTHERS =>
fsm_rx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fifrx1 : fiforx_spi
PORT MAP (
rst => NOT(rst_n),
wr_clk => clk_sys,
rd_clk => sclk,
din => l7_rx1,
wr_en => l7_rd1buf,
rd_en => rd_datarx_spi1,
dout => reg_fiforx1_spi,
full => OPEN,
empty => fiforx_empty1,
rd_data_count => fiforx_datacnt1
);
-- Taille de la trame dans la FIFO : 255 si >= 256, sinon Nb octets dans la FIFO
reg_rx1size_spi <= x"FF" WHEN fiforx_datacnt1(10 DOWNTO 8) /= "000" ELSE
fiforx_datacnt1(7 DOWNTO 0);
 
inst_fifrx2 : fiforx_spi
PORT MAP (
rst => NOT(rst_n),
wr_clk => clk_sys,
rd_clk => sclk,
din => l7_rx2,
wr_en => l7_rd2buf,
rd_en => rd_datarx_spi2,
dout => reg_fiforx2_spi,
full => OPEN,
empty => fiforx_empty2,
rd_data_count => fiforx_datacnt2
);
-- Taille de la trame dans la FIFO : 255 si >= 256, sinon Nb octets dans la FIFO
reg_rx2size_spi <= x"FF" WHEN fiforx_datacnt2(10 DOWNTO 8) /= "000" ELSE
fiforx_datacnt2(7 DOWNTO 0);
 
-------------------------------------------------
-- Signaux de gestion de l'I/F SPI vers la PROM
-------------------------------------------------
--------------------------------------------
 
--------------------------------------------
write_regpromctl : PROCESS(sclk, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_promctl <= x"00";
reg_promnbrd <= x"00";
ELSIF (sclk'EVENT and sclk = '1') THEN
IF (wr_reg = '1' AND adwr_spi = adreg_promctl) THEN
reg_promctl <= shifter_spirx;
ELSE
reg_promctl(3) <= '0';
END IF;
IF (wr_reg = '1' AND adwr_spi = adreg_promnbrd) THEN
reg_promnbrd <= shifter_spirx;
END IF;
END IF;
END PROCESS;
 
txprom_dat <= shifter_spirx;
txprom_val <= wr_reg WHEN (adwr_spi = adreg_promtx) ELSE '0';
rxprom_next <= rd_reg WHEN (adrd_spi = adreg_promrx) ELSE '0';
prom_type_com <= reg_promctl(0);
prom_exec_com <= reg_promctl(3);
prom_rstn <= reg_promctl(4);
prom_nbread <= reg_promnbrd;
 
END rtl;
 
/tags/Release IPCommunication v1.0/if_picspi.vhd
0,0 → 1,752
--=============================================================================
-- TITRE : IF_PICSPI
-- DESCRIPTION :
 
 
 
-- FICHIER : if_picspi.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
-- 24/11/2014 DRA SATURN 1.01
 
 
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
 
ENTITY if_picspi IS
GENERIC (
version : STD_LOGIC_VECTOR(7 DOWNTO 0);
pic_num : INTEGER := 1);
PORT (
 
 
 
 
-- Interface SPI
sclk : IN STD_LOGIC; -- Clock SPI
sdi : IN STD_LOGIC; -- Bit IN SPI
sdo : OUT STD_LOGIC; -- Bit OUT SPI
ssn : IN STD_LOGIC; -- CSn SPI
 
-- Interface avec les autres modules du FPGA
 
-- Signaux de configurations
iid : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- Identifiant IID du FPGA
tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Identifiant TID du FPGA
cpy1 : OUT STD_LOGIC; -- Autorise la recopie du port 1 sur port 2
cpy2 : OUT STD_LOGIC; -- Autorise la recopie du port 2 sur port 1
repli : OUT STD_LOGIC; -- Indique que le module est en repli (gestion des LED)
-- Interfaces de lecture des trames port 1
 
 
 
l7_comdispo1 : IN STD_LOGIC; -- Indique qu'il y'a au moins une trame de dispo
 
l7_l2ok1 : IN STD_LOGIC; -- Indique si la couche transport est bonne ou non
 
activity1 : IN STD_LOGIC; -- Indique une trame sur le port 1 (couche 2)
-- Interfaces de lecture des trames port 2
 
 
 
l7_comdispo2 : IN STD_LOGIC; -- Indique qu'il y'a au moins une trame de dispo
 
l7_l2ok2 : IN STD_LOGIC; -- Indique si la couche transport est bonne ou non
 
activity2 : IN STD_LOGIC; -- Indique une trame sur le port 2 (couche 2)
 
 
 
val_txdat : OUT STD_LOGIC; -- Validant de chaque octet
 
tx_eof : OUT STD_LOGIC; -- Indique la fin d'une trame
txdat_free : IN STD_LOGIC; -- Indique que la couche transport en tx est libre
clr_fifo_tx : OUT STD_LOGIC; -- Permet de purger les FIFO Tx
-- Gestion de l'interface SPI PROM
 
txprom_val : OUT STD_LOGIC; -- Validant de txprom_data
 
 
 
 
prom_exec_com: OUT STD_LOGIC; -- Lance une commande dans le module de reprog
 
prom_nbread : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-- Nombre d'octet qu'il faut lire avec une commande de lecture
prom_rstn : OUT STD_LOGIC -- Reset du module de reprog
);
END if_picspi;
 
ARCHITECTURE rtl of if_picspi is
 
SIGNAL fsm_tx : fsmtx_state;
 
 
SIGNAL fsm_rx : fsmrx_state;
 
 
CONSTANT adreg_iid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 7);
CONSTANT adreg_tid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(8, 7);
CONSTANT adreg_ctl : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(9, 7);
CONSTANT adreg_stat : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(10, 7);
CONSTANT adreg_rxsize1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(11, 7);
CONSTANT adreg_rxsize2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(12, 7);
CONSTANT adreg_txfree : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(13, 7);
CONSTANT adreg_fiforx1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(14, 7);
CONSTANT adreg_fiforx2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(15, 7);
CONSTANT adreg_fifotx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(16, 7);
CONSTANT adreg_version : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(17, 7);
CONSTANT adreg_promtx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(18, 7);
CONSTANT adreg_promrx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(19, 7);
CONSTANT adreg_promctl : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(20, 7);
CONSTANT adreg_promnbrd : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(21, 7);
CONSTANT adreg_trafic : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(22, 7);
 
SIGNAL reg_tid_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_ctl_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_stat_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_rx1size_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_rx2size_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_txfree_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_fiforx1_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_fiforx2_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_promctl : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_promnbrd : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_trafic : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
-- Signaux de gestion de l'interface SPI
SIGNAL cpt_bitspi : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Compte le nombre de bits sur un cycle SPI
SIGNAL cptbit_tx : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Compte le nombre de bits en Tx sur le SPI
 
 
 
SIGNAL dat_adn : STD_LOGIC; -- Indique si l'octet en cours sur SPI est une data ou l'adresse
 
 
SIGNAL spi_encours : STD_LOGIC; -- Indique un cycle SPI en cours
 
 
SIGNAL rd_reg : STD_LOGIC; -- 1 pulse pour lire le registre adrd_spi
 
 
 
 
 
 
 
 
 
-- Signaux de gestion interne et changement d'horloge
SIGNAL difftx_free : STD_LOGIC_VECTOR(10 DOWNTO 0); -- Pour calculer la taille dispo en FIFO Tx sur 8 bits
 
 
SIGNAL rd_datatx_sys : STD_LOGIC; -- Ordre de lecture dans la FIFO Tx
 
SIGNAL fifotx_empty : STD_LOGIC; -- Indique une FFIO Tx vide
SIGNAL rst_fifotx : STD_LOGIC; -- Effacement FIFO Tx
SIGNAL cpt_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Compteur d'octet pour relire la FIFO Tx
 
 
 
SIGNAL rd_datarx_spi1 : STD_LOGIC; -- Ordre de lecture dans la FIFO Rx1
SIGNAL fiforx_empty1 : STD_LOGIC; -- FIFO Rx1 vide
 
 
SIGNAL rd_datarx_spi2 : STD_LOGIC; -- Ordre de lecture dans la FIFO Rx2
SIGNAL fiforx_empty2 : STD_LOGIC; -- FIFO Rx2 vide
 
SIGNAL l7_rd : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx1 ou l7_rx2
SIGNAL l7_rd1buf : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx1
SIGNAL l7_rd2buf : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx2
 
 
 
 
 
 
 
 
COMPONENT fifotx_spi
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
COMPONENT fiforx_spi
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
--------------------------------------------
-- Module de Delay du SDI
--------------------------------------------
IODELAY2_inst : IODELAY2
generic map (
COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
IDELAY_TYPE => "FIXED", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
-- or "DIFF_PHASE_DETECTOR"
 
ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
SERDES_MODE => "NONE", -- "NONE", "MASTER" or "SLAVE"
SIM_TAPDELAY_VALUE => 71 -- Per tap delay used for simulation in ps
)
port map (
BUSY => OPEN, -- 1-bit output: Busy output after CAL
DATAOUT => sdi_delayed,-- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => OPEN, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => OPEN, -- 1-bit output: Delayed data output
TOUT => OPEN, -- 1-bit output: Delayed 3-state output
CAL => '0', -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => '0', -- 1-bit input: Clock input
IDATAIN => sdi, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
INC => '0', -- 1-bit input: Increment / decrement input
IOCLK0 => '0', -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
RST => '0', -- 1-bit input: Reset to zero or 1/2 of total delay period
T => '0' -- 1-bit input: 3-state input signal
);
 
--------------------------------------------
 
--------------------------------------------
select_frontmont : IF (pic_num = 1) GENERATE
BEGIN
serrx_spi : PROCESS(sclk)
BEGIN
IF (sclk'EVENT AND sclk = '1') THEN
 
END IF;
END PROCESS;
END GENERATE;
select_frontdec : IF (pic_num = 2) GENERATE
BEGIN
serrx_spi : PROCESS(sclk)
BEGIN
IF (sclk'EVENT AND sclk = '0') THEN
 
END IF;
END PROCESS;
END GENERATE;
 
--------------------------------------------
 
--------------------------------------------
sertx_spi : PROCESS(sclk, ssn)
BEGIN
IF (ssn = '1') THEN
-- Tant que le ssn n'est pas actif, on reste inactif
shifter_spitx <= (OTHERS => '0');
cptbit_tx <= "000";
front_ssn <= '1';
ELSIF (sclk'EVENT and sclk = '0') THEN
-- Sur front descendant de sclk
 
cptbit_tx <= cptbit_tx + 1; -- a chaque sclk on compte 1 bit
IF (cptbit_tx = "000")THEN
-- Pour le 1er sclk de chaque octet
IF (front_ssn = '1') THEN
 
 
ELSE
 
shifter_spitx <= data_rdspi;
END IF;
ELSE
-- Pour tous les autres bist, on fait un shift
shifter_spitx <= shifter_spitx(6 DOWNTO 0) & '0';
END IF;
END IF;
END PROCESS;
sdo <= shifter_spitx(7);
 
--------------------------------------------
-- Process de gestion d'un cycle SPI
 
 
 
-- mais rendue effective que si le PIC la veut vraiment (i.e. le cycle SPI n'est pas
-- interrompu avant)
--------------------------------------------
managespi : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
ssnr <= "111";
sclkr <= "111";
spi_encours <= '0';
cpt_bitspi <= "000";
dat_adn <= '0';
rwn_spi <= '0';
adrd_spi <= (OTHERS => '0');
rd_reg <= '0';
latch_rdspi <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
 
 
IF (ssn_fall = '1') THEN
-- Initialisations sur activation de ssn
spi_encours <= '1'; -- On est en cours de traitement
 
 
ELSIF (ssn_rise = '1') THEN
-- A la fin du scycle spi
spi_encours <= '0';
ELSE
 
IF (spi_encours = '1') THEN
-- Si on est dans un cycle spi
IF (sclk_rise = '1') THEN
-- Sur chaque front montant de sclk
cpt_bitspi <= cpt_bitspi + 1; -- On comtpe un bit de plus
IF (cpt_bitspi = "110") THEN
 
IF (dat_adn = '0') THEN
-- Si c'est le 1er octet de la trame SPI
 
ELSE
 
 
IF (adrd_spi /= adreg_fiforx1 AND
adrd_spi /= adreg_fiforx2 AND
adrd_spi /= adreg_fifotx AND
adrd_spi /= adreg_promtx AND
adrd_spi /= adreg_promrx) THEN
 
adrd_spi <= adrd_spi + 1;
END IF;
END IF;
 
ELSIF (cpt_bitspi = "111") THEN
 
 
IF (dat_adn = '0') THEN
-- Si c'est le 1er octet de la trame SPI
 
END IF;
ELSIF (cpt_bitspi = "000") THEN
 
 
END IF;
ELSE
-- En dehors des front de sclk, on assure que les signaux de lecture ne durent qu'un cycle
rd_reg <= '0';
latch_rdspi <= '0';
END IF;
ELSE
-- En dehors d'un cycle SPI, on assure qu'on fait pas de lecture non voulue
rd_reg <= '0';
latch_rdspi <= '0';
END IF;
END IF;
END IF;
END PROCESS;
 
 
 
 
-- - on est en write
wr_reg <= dat_adn AND NOT(rwn_spi) WHEN (sclk_rise = '1' AND cpt_bitspi = "111") ELSE '0';
 
ssn_fall <= ssnr(2) AND NOT(ssnr(1));
 
ssn_rise <= NOT(ssnr(2)) AND ssnr(1);
 
sclk_rise <= NOT(sclkr(2)) AND sclkr(1);
 
--------------------------------------------
-- Process de latch d'un registre en lecture
--------------------------------------------
mux_read: PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
data_rdspi <= (OTHERS => '0');
ELSIF (clk_sys'event AND clk_sys ='1') THEN
IF (latch_rdspi = '1') THEN
 
CASE adrd_spi IS
WHEN adreg_iid => data_rdspi <= iid(63 DOWNTO 56);
WHEN adreg_iid+1 => data_rdspi <= iid(55 DOWNTO 48);
WHEN adreg_iid+2 => data_rdspi <= iid(47 DOWNTO 40);
WHEN adreg_iid+3 => data_rdspi <= iid(39 DOWNTO 32);
WHEN adreg_iid+4 => data_rdspi <= iid(31 DOWNTO 24);
WHEN adreg_iid+5 => data_rdspi <= iid(23 DOWNTO 16);
WHEN adreg_iid+6 => data_rdspi <= iid(15 DOWNTO 8);
WHEN adreg_iid+7 => data_rdspi <= iid(7 DOWNTO 0);
WHEN adreg_tid => data_rdspi <= reg_tid_spi;
WHEN adreg_ctl => data_rdspi <= reg_ctl_spi;
WHEN adreg_stat => data_rdspi <= reg_stat_spi;
WHEN adreg_rxsize1=> data_rdspi <= reg_rx1size_spi;
WHEN adreg_rxsize2=> data_rdspi <= reg_rx2size_spi;
WHEN adreg_txfree => data_rdspi <= reg_txfree_spi;
WHEN adreg_fiforx1=> data_rdspi <= reg_fiforx1_spi;
WHEN adreg_fiforx2=> data_rdspi <= reg_fiforx2_spi;
-- WHEN adreg_fifotx => data_rdspi <= dummy -- Ce registre est Write Only
WHEN adreg_version=> data_rdspi <= version;
WHEN adreg_promctl=> data_rdspi <= rxprom_val & reg_promctl(6 DOWNTO 4) & prom_busy & reg_promctl(2 DOWNTO 0);
WHEN adreg_promnbrd=>data_rdspi <= reg_promnbrd;
-- WHEN adreg_promtx => data_rdspi <= dummy -- Ce registre est Write Only
WHEN adreg_promrx=> data_rdspi <= rxprom_dat;
WHEN adreg_trafic=> data_rdspi <= reg_trafic;
WHEN OTHERS => data_rdspi <= reg_stat_spi;
END CASE;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
write_reg : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_tid_spi <= x"8F";
reg_ctl_spi <= x"84";
reg_promctl <= x"00";
reg_promnbrd <= x"00";
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (wr_reg = '1') THEN
 
CASE adwr_spi IS
WHEN adreg_tid => reg_tid_spi <= shifter_spirx;
WHEN adreg_ctl =>
 
reg_ctl_spi(7 DOWNTO 5) <= shifter_spirx(7 DOWNTO 5);
reg_ctl_spi(2 DOWNTO 0) <= shifter_spirx(2 DOWNTO 0);
WHEN adreg_promnbrd => reg_promnbrd <= shifter_spirx;
WHEN OTHERS =>
END CASE;
END IF;
IF (clr_starttx = '1') THEN
-- Si on a fini de traiter une trame en Tx
 
ELSE
IF (wr_reg = '1') AND (adwr_spi = adreg_ctl) AND (shifter_spirx(3) = '1') THEN
 
reg_ctl_spi(3) <= '1';
END IF;
END IF;
IF (wr_reg = '1' AND adwr_spi = adreg_promctl) THEN
reg_promctl <= shifter_spirx;
ELSE
-- Le bit 3 ne doit durer qu'un seul coup de clk_sys
reg_promctl(3) <= '0';
END IF;
END IF;
END PROCESS;
-- Affectation des sorties en fonction des registres internes
cpy1 <= reg_ctl_spi(0);
cpy2 <= reg_ctl_spi(1);
rst_fifotx <= reg_ctl_spi(2);
start_tx <= reg_ctl_spi(3);
repli<= reg_ctl_spi(7);
tid <= reg_tid_spi;
 
--------------------------------------------
-- Process de gestion du registre de status
 
 
--------------------------------------------
gest_stat : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_stat_spi(7 DOWNTO 2) <= (OTHERS => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (l7_newframe1 = '1' AND l7_l2ok1 = '0') THEN
 
reg_stat_spi(2) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(2) <= reg_stat_spi(2) AND NOT(shifter_spirx(2));
END IF;
IF (l7_newframe2 = '1' AND l7_l2ok2 = '0') THEN
 
reg_stat_spi(3) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(3) <= reg_stat_spi(3) AND NOT(shifter_spirx(3));
END IF;
IF (l7_overflow1 = '1') THEN
 
reg_stat_spi(4) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(4) <= reg_stat_spi(4) AND NOT(shifter_spirx(4));
END IF;
IF (l7_overflow2 = '1') THEN
 
reg_stat_spi(5) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(5) <= reg_stat_spi(5) AND NOT(shifter_spirx(5));
END IF;
reg_stat_spi(6) <= NOT(fifotx_empty); -- Indique que la FIFO Tx n'est pas vide
END IF;
END PROCESS;
reg_stat_spi(1 DOWNTO 0) <= frm2 & frm1; -- Indication que les FIFO Rx sont pas vides
 
--------------------------------------------
-- Process de gestion du registre TRAFIC
--------------------------------------------
gest_trafic : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_trafic <= x"03";
mem_activity1 <= '1';
mem_activity2 <= '1';
ELSIF (clk_sys'EVENT AND clk_sys = '1') THEN
IF (wr_reg = '1' AND adwr_spi = adreg_ctl AND shifter_spirx(4) = '1') THEN
 
 
 
mem_activity2 <= activity2;
ELSE
 
IF (activity1 = '1') THEN
 
mem_activity1 <= '1';
END IF;
IF (activity2 = '1') THEN
mem_activity2 <= '1';
END IF;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
-- Process de gestion de la FIFO Tx
--------------------------------------------
difftx_free <= "10000000010" - fifotx_datacnt; -- Calcul du nombre d'octets dispo dans la FIFO 1026-cnt
 
 
 
 
wr_datatx_spi <= '1' WHEN (wr_reg = '1' AND adwr_spi = adreg_fifotx) ELSE '0';
clr_fifo_tx <= '0'; -- Spare pour l'instant on ne fait pas de clear de la fifo tx aval
 
 
-- ou bien en cours de transfert lorsque le module suivant est dispo
rd_datatx_sys <= '1' WHEN ((fsm_tx = idle_st AND fifotx_empty = '0' AND start_tx = '1') OR
(fsm_tx = senddat_st AND txdat_free = '1' AND fifotx_empty = '0')) ELSE
'0';
 
 
 
val_txdat <= NOT(fifotx_empty) WHEN (fsm_tx = idle_st) ELSE '1';
 
tx_dat <= datatx_rd_sys;
-- La fin de trame est valide si le module suivant est dispo
tx_eof <= txdat_free WHEN (fsm_tx = senddat_st AND cpt_tx = "00000001") ELSE '0';
 
gest_fsm_tx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_tx <= idle_st;
tx_sof <= '0';
cpt_tx <= (OTHERS => '0');
clr_starttx <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_tx IS
WHEN idle_st =>
 
IF (fifotx_empty = '0' AND start_tx = '1') THEN
 
cpt_tx <= datatx_rd_sys; -- On initialise le compteur avec la longueur de la trame (1er octet dans la FIFO)
 
 
clr_starttx <= '1'; -- On indique qu'on a pris en compte l'ordre de Tx
END IF;
 
WHEN senddat_st =>
 
clr_starttx <= '0'; -- Ne dure qu'un seul cycle
IF (txdat_free = '1') THEN
 
 
cpt_tx <= cpt_tx - 1; -- Dans ce cas on enregistre une donnee de moins
tx_sof <= '0'; -- On peut annuler le sof car on est sur que le module suivant l'a pris en comtpe
 
fsm_tx <= idle_st; -- On a fini
END IF;
END IF;
WHEN OTHERS =>
fsm_tx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fiftx : fifotx_spi
PORT MAP (
rst => rst_fifotx,
clk => clk_sys,
din => shifter_spirx,
wr_en => wr_datatx_spi,
rd_en => rd_datatx_sys,
dout => datatx_rd_sys,
full => OPEN,
empty => fifotx_empty,
data_count => fifotx_datacnt
);
--------------------------------------------
-- Process de gestion des FIFO Rx
--------------------------------------------
-- Ordre de lecture dans les FIFO Rx
rd_datarx_spi1 <= '1' WHEN (rd_reg = '1' AND adrd_spi = adreg_fiforx1) ELSE '0';
rd_datarx_spi2 <= '1' WHEN (rd_reg = '1' AND adrd_spi = adreg_fiforx2) ELSE '0';
 
 
l7_rd1buf <= (l7_rd AND NOT(sel_voie) AND comdispo AND NOT(soc)) WHEN (fsm_rx = recdat_st) ELSE
(l7_rd AND NOT(sel_voie));
l7_rd1 <= l7_rd1buf;
l7_rd2buf <= (l7_rd AND sel_voie AND comdispo AND NOT(soc)) WHEN (fsm_rx = recdat_st) ELSE
(l7_rd AND sel_voie);
l7_rd2 <= l7_rd2buf;
comdispo <= l7_comdispo1 WHEN (sel_voie = '0') ELSE l7_comdispo2;
soc <= l7_soc1 WHEN (sel_voie = '0') ELSE l7_soc2;
 
gest_fsm_rx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
l7_rd <= '0';
sel_voie <= '0';
fsm_rx <= idle_st;
frm2 <= '0';
frm1 <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_rx IS
WHEN idle_st =>
-- Etat d'attente qu'une FIFO Rx1 ou Rx2 soit vide et qu'il y'ait une trame disponible
-- sur la voie correspondante
frm1 <= NOT(fiforx_empty1); -- On indique s'il y'a des trames en FIFO Rx
frm2 <= NOT(fiforx_empty2);
IF ((l7_comdispo1 = '1' AND fiforx_empty1 = '1') AND
(l7_comdispo2 = '0' OR fiforx_empty2 = '0' OR sel_voie = '1')) THEN
 
 
 
 
fsm_rx <= pump_st;
ELSIF (l7_comdispo2 = '1' AND fiforx_empty2 = '1') THEN
sel_voie <= '1';
l7_rd <= '1';
fsm_rx <= pump_st;
ELSE
l7_rd <= '0';
END IF;
WHEN pump_st =>
 
fsm_rx <= recdat_st;
 
WHEN recdat_st =>
-- Etat de lecture de chaque octet de la trame
IF (soc = '1' OR comdispo = '0') THEN
 
l7_rd <= '0';
fsm_rx <= waitnotempty_st;
END IF;
WHEN waitnotempty_st =>
 
 
-- en cas de plusieurs petites trames dispo en DPRAM et donc garantir qu'on a
-- une seule trame en FIFO Rx
IF ((fiforx_empty1 = '0' AND sel_voie = '0') OR
(fiforx_empty2 = '0' AND sel_voie = '1')) THEN
fsm_rx <= idle_st;
END IF;
 
WHEN OTHERS =>
fsm_rx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fifrx1 : fiforx_spi
PORT MAP (
rst => NOT(rst_n),
clk => clk_sys,
din => l7_rx1,
wr_en => l7_rd1buf,
rd_en => rd_datarx_spi1,
dout => reg_fiforx1_spi,
full => OPEN,
empty => fiforx_empty1,
data_count => fiforx_datacnt1
);
-- Taille de la trame dans la FIFO : 255 si >= 256, sinon Nb octets dans la FIFO
reg_rx1size_spi <= x"FF" WHEN fiforx_datacnt1(10 DOWNTO 8) /= "000" ELSE
fiforx_datacnt1(7 DOWNTO 0);
 
inst_fifrx2 : fiforx_spi
PORT MAP (
rst => NOT(rst_n),
clk => clk_sys,
din => l7_rx2,
wr_en => l7_rd2buf,
rd_en => rd_datarx_spi2,
dout => reg_fiforx2_spi,
full => OPEN,
empty => fiforx_empty2,
data_count => fiforx_datacnt2
);
-- Taille de la trame dans la FIFO : 255 si >= 256, sinon Nb octets dans la FIFO
reg_rx2size_spi <= x"FF" WHEN fiforx_datacnt2(10 DOWNTO 8) /= "000" ELSE
fiforx_datacnt2(7 DOWNTO 0);
 
-------------------------------------------------
-- Signaux de gestion de l'I/F SPI vers la PROM
-------------------------------------------------
 
 
txprom_val <= wr_reg WHEN (adwr_spi = adreg_promtx) ELSE '0';
 
rxprom_next <= rd_reg WHEN (adrd_spi = adreg_promrx) ELSE '0';
-- Affectation des signaux de controle
prom_type_com <= reg_promctl(0);
prom_exec_com <= reg_promctl(3);
prom_rstn <= reg_promctl(4);
prom_nbread <= reg_promnbrd;
 
END rtl;
 
/tags/Release IPCommunication v1.0/if_picspi2.vhd
0,0 → 1,738
--=============================================================================
-- TITRE : IF_PICSPI
-- DESCRIPTION :
 
 
 
-- FICHIER : if_picspi.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
-- 24/11/2014 DRA SATURN 1.01
 
 
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
 
ENTITY if_picspi2 IS
GENERIC (
version : STD_LOGIC_VECTOR(7 DOWNTO 0));
PORT (
 
 
 
 
-- Interface SPI
sclk : IN STD_LOGIC; -- Clock SPI
sdi : IN STD_LOGIC; -- Bit IN SPI
sdo : OUT STD_LOGIC; -- Bit OUT SPI
ssn : IN STD_LOGIC; -- CSn SPI
 
-- Interface avec les autres modules du FPGA
 
-- Signaux de configurations
iid : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- Identifiant IID du FPGA
tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Identifiant TID du FPGA
cpy1 : OUT STD_LOGIC; -- Autorise la recopie du port 1 sur port 2
cpy2 : OUT STD_LOGIC; -- Autorise la recopie du port 2 sur port 1
repli : OUT STD_LOGIC; -- Indique que le module est en repli (gestion des LED)
-- Interfaces de lecture des trames port 1
 
 
 
l7_comdispo1 : IN STD_LOGIC; -- Indique qu'il y'a au moins une trame de dispo
 
l7_l2ok1 : IN STD_LOGIC; -- Indique si la couche transport est bonne ou non
 
activity1 : IN STD_LOGIC; -- Indique une trame sur le port 1 (couche 2)
-- Interfaces de lecture des trames port 2
 
 
 
l7_comdispo2 : IN STD_LOGIC; -- Indique qu'il y'a au moins une trame de dispo
 
l7_l2ok2 : IN STD_LOGIC; -- Indique si la couche transport est bonne ou non
 
activity2 : IN STD_LOGIC; -- Indique une trame sur le port 2 (couche 2)
 
 
 
val_txdat : OUT STD_LOGIC; -- Validant de chaque octet
 
tx_eof : OUT STD_LOGIC; -- Indique la fin d'une trame
txdat_free : IN STD_LOGIC; -- Indique que la couche transport en tx est libre
clr_fifo_tx : OUT STD_LOGIC; -- Permet de purger les FIFO Tx
-- Gestion de l'interface SPI PROM
 
txprom_val : OUT STD_LOGIC; -- Validant de txprom_data
 
 
 
 
prom_exec_com: OUT STD_LOGIC; -- Lance une commande dans le module de reprog
 
prom_nbread : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-- Nombre d'octet qu'il faut lire avec une commande de lecture
prom_rstn : OUT STD_LOGIC -- Reset du module de reprog
);
END if_picspi2;
 
ARCHITECTURE rtl of if_picspi2 is
 
SIGNAL fsm_tx : fsmtx_state;
 
 
SIGNAL fsm_rx : fsmrx_state;
 
 
CONSTANT adreg_iid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 7);
CONSTANT adreg_tid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(8, 7);
CONSTANT adreg_ctl : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(9, 7);
CONSTANT adreg_stat : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(10, 7);
CONSTANT adreg_rxsize1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(11, 7);
CONSTANT adreg_rxsize2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(12, 7);
CONSTANT adreg_txfree : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(13, 7);
CONSTANT adreg_fiforx1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(14, 7);
CONSTANT adreg_fiforx2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(15, 7);
CONSTANT adreg_fifotx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(16, 7);
CONSTANT adreg_version : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(17, 7);
CONSTANT adreg_promtx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(18, 7);
CONSTANT adreg_promrx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(19, 7);
CONSTANT adreg_promctl : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(20, 7);
CONSTANT adreg_promnbrd : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(21, 7);
CONSTANT adreg_trafic : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(22, 7);
 
SIGNAL reg_tid_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_ctl_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_stat_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_rx1size_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_rx2size_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_txfree_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_fiforx1_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_fiforx2_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_promctl : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_promnbrd : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_trafic : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
-- Signaux de gestion de l'interface SPI
SIGNAL cpt_bitspi : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Compte le nombre de bits sur un cycle SPI
SIGNAL cptbit_tx : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Compte le nombre de bits en Tx sur le SPI
 
 
 
SIGNAL dat_adn : STD_LOGIC; -- Indique si l'octet en cours sur SPI est une data ou l'adresse
 
 
SIGNAL spi_encours : STD_LOGIC; -- Indique un cycle SPI en cours
 
 
SIGNAL rd_reg : STD_LOGIC; -- 1 pulse pour lire le registre adrd_spi
 
 
 
 
 
 
 
 
 
-- Signaux de gestion interne et changement d'horloge
SIGNAL difftx_free : STD_LOGIC_VECTOR(10 DOWNTO 0); -- Pour calculer la taille dispo en FIFO Tx sur 8 bits
 
 
SIGNAL rd_datatx_sys : STD_LOGIC; -- Ordre de lecture dans la FIFO Tx
 
SIGNAL fifotx_empty : STD_LOGIC; -- Indique une FFIO Tx vide
SIGNAL rst_fifotx : STD_LOGIC; -- Effacement FIFO Tx
SIGNAL cpt_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Compteur d'octet pour relire la FIFO Tx
 
 
 
SIGNAL rd_datarx_spi1 : STD_LOGIC; -- Ordre de lecture dans la FIFO Rx1
SIGNAL fiforx_empty1 : STD_LOGIC; -- FIFO Rx1 vide
 
 
SIGNAL rd_datarx_spi2 : STD_LOGIC; -- Ordre de lecture dans la FIFO Rx2
SIGNAL fiforx_empty2 : STD_LOGIC; -- FIFO Rx2 vide
 
SIGNAL l7_rd : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx1 ou l7_rx2
SIGNAL l7_rd1buf : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx1
SIGNAL l7_rd2buf : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx2
 
 
 
 
 
 
 
 
COMPONENT fifotx_spi
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
COMPONENT fiforx_spi
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
--------------------------------------------
-- Module de Delay du SDI
--------------------------------------------
IODELAY2_inst : IODELAY2
generic map (
COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
IDELAY_TYPE => "FIXED", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
-- or "DIFF_PHASE_DETECTOR"
 
ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
SERDES_MODE => "NONE", -- "NONE", "MASTER" or "SLAVE"
SIM_TAPDELAY_VALUE => 71 -- Per tap delay used for simulation in ps
)
port map (
BUSY => OPEN, -- 1-bit output: Busy output after CAL
DATAOUT => sdi_delayed,-- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => OPEN, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => OPEN, -- 1-bit output: Delayed data output
TOUT => OPEN, -- 1-bit output: Delayed 3-state output
CAL => '0', -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => '0', -- 1-bit input: Clock input
IDATAIN => sdi, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
INC => '0', -- 1-bit input: Increment / decrement input
IOCLK0 => '0', -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
RST => '0', -- 1-bit input: Reset to zero or 1/2 of total delay period
T => '0' -- 1-bit input: 3-state input signal
);
 
--------------------------------------------
 
--------------------------------------------
serrx_spi : PROCESS(sclk)
BEGIN
IF (sclk'EVENT AND sclk = '0') THEN
 
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
sertx_spi : PROCESS(sclk, ssn)
BEGIN
IF (ssn = '1') THEN
-- Tant que le ssn n'est pas actif, on reste inactif
shifter_spitx <= (OTHERS => '0');
cptbit_tx <= "000";
front_ssn <= '1';
ELSIF (sclk'EVENT and sclk = '0') THEN
-- Sur front descendant de sclk
 
cptbit_tx <= cptbit_tx + 1; -- a chaque sclk on compte 1 bit
IF (cptbit_tx = "000")THEN
-- Pour le 1er sclk de chaque octet
IF (front_ssn = '1') THEN
 
 
ELSE
 
shifter_spitx <= data_rdspi;
END IF;
ELSE
-- Pour tous les autres bist, on fait un shift
shifter_spitx <= shifter_spitx(6 DOWNTO 0) & '0';
END IF;
END IF;
END PROCESS;
sdo <= shifter_spitx(7);
 
--------------------------------------------
-- Process de gestion d'un cycle SPI
 
 
 
-- mais rendue effective que si le PIC la veut vraiment (i.e. le cycle SPI n'est pas
-- interrompu avant)
--------------------------------------------
managespi : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
ssnr <= "111";
sclkr <= "111";
spi_encours <= '0';
cpt_bitspi <= "000";
dat_adn <= '0';
rwn_spi <= '0';
adrd_spi <= (OTHERS => '0');
rd_reg <= '0';
latch_rdspi <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
 
 
IF (ssn_fall = '1') THEN
-- Initialisations sur activation de ssn
spi_encours <= '1'; -- On est en cours de traitement
 
 
ELSIF (ssn_rise = '1') THEN
-- A la fin du scycle spi
spi_encours <= '0';
ELSE
 
IF (spi_encours = '1') THEN
-- Si on est dans un cycle spi
IF (sclk_rise = '1') THEN
-- Sur chaque front montant de sclk
cpt_bitspi <= cpt_bitspi + 1; -- On comtpe un bit de plus
IF (cpt_bitspi = "110") THEN
 
IF (dat_adn = '0') THEN
-- Si c'est le 1er octet de la trame SPI
 
ELSE
 
 
IF (adrd_spi /= adreg_fiforx1 AND
adrd_spi /= adreg_fiforx2 AND
adrd_spi /= adreg_fifotx AND
adrd_spi /= adreg_promtx AND
adrd_spi /= adreg_promrx) THEN
 
adrd_spi <= adrd_spi + 1;
END IF;
END IF;
 
ELSIF (cpt_bitspi = "111") THEN
 
 
IF (dat_adn = '0') THEN
-- Si c'est le 1er octet de la trame SPI
 
END IF;
ELSIF (cpt_bitspi = "000") THEN
 
 
END IF;
ELSE
-- En dehors des front de sclk, on assure que les signaux de lecture ne durent qu'un cycle
rd_reg <= '0';
latch_rdspi <= '0';
END IF;
ELSE
-- En dehors d'un cycle SPI, on assure qu'on fait pas de lecture non voulue
rd_reg <= '0';
latch_rdspi <= '0';
END IF;
END IF;
END IF;
END PROCESS;
 
 
 
 
-- - on est en write
wr_reg <= dat_adn AND NOT(rwn_spi) WHEN (sclk_rise = '1' AND cpt_bitspi = "111") ELSE '0';
 
ssn_fall <= ssnr(2) AND NOT(ssnr(1));
 
ssn_rise <= NOT(ssnr(2)) AND ssnr(1);
 
sclk_rise <= NOT(sclkr(2)) AND sclkr(1);
 
--------------------------------------------
-- Process de latch d'un registre en lecture
--------------------------------------------
mux_read: PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
data_rdspi <= (OTHERS => '0');
ELSIF (clk_sys'event AND clk_sys ='1') THEN
IF (latch_rdspi = '1') THEN
 
CASE adrd_spi IS
WHEN adreg_iid => data_rdspi <= iid(63 DOWNTO 56);
WHEN adreg_iid+1 => data_rdspi <= iid(55 DOWNTO 48);
WHEN adreg_iid+2 => data_rdspi <= iid(47 DOWNTO 40);
WHEN adreg_iid+3 => data_rdspi <= iid(39 DOWNTO 32);
WHEN adreg_iid+4 => data_rdspi <= iid(31 DOWNTO 24);
WHEN adreg_iid+5 => data_rdspi <= iid(23 DOWNTO 16);
WHEN adreg_iid+6 => data_rdspi <= iid(15 DOWNTO 8);
WHEN adreg_iid+7 => data_rdspi <= iid(7 DOWNTO 0);
WHEN adreg_tid => data_rdspi <= reg_tid_spi;
WHEN adreg_ctl => data_rdspi <= reg_ctl_spi;
WHEN adreg_stat => data_rdspi <= reg_stat_spi;
WHEN adreg_rxsize1=> data_rdspi <= reg_rx1size_spi;
WHEN adreg_rxsize2=> data_rdspi <= reg_rx2size_spi;
WHEN adreg_txfree => data_rdspi <= reg_txfree_spi;
WHEN adreg_fiforx1=> data_rdspi <= reg_fiforx1_spi;
WHEN adreg_fiforx2=> data_rdspi <= reg_fiforx2_spi;
-- WHEN adreg_fifotx => data_rdspi <= dummy -- Ce registre est Write Only
WHEN adreg_version=> data_rdspi <= version;
WHEN adreg_promctl=> data_rdspi <= rxprom_val & reg_promctl(6 DOWNTO 4) & prom_busy & reg_promctl(2 DOWNTO 0);
WHEN adreg_promnbrd=>data_rdspi <= reg_promnbrd;
-- WHEN adreg_promtx => data_rdspi <= dummy -- Ce registre est Write Only
WHEN adreg_promrx=> data_rdspi <= rxprom_dat;
WHEN adreg_trafic=> data_rdspi <= reg_trafic;
WHEN OTHERS => data_rdspi <= reg_stat_spi;
END CASE;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
write_reg : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_tid_spi <= x"8F";
reg_ctl_spi <= x"84";
reg_promctl <= x"00";
reg_promnbrd <= x"00";
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (wr_reg = '1') THEN
 
CASE adwr_spi IS
WHEN adreg_tid => reg_tid_spi <= shifter_spirx;
WHEN adreg_ctl =>
 
reg_ctl_spi(7 DOWNTO 5) <= shifter_spirx(7 DOWNTO 5);
reg_ctl_spi(2 DOWNTO 0) <= shifter_spirx(2 DOWNTO 0);
WHEN adreg_promnbrd => reg_promnbrd <= shifter_spirx;
WHEN OTHERS =>
END CASE;
END IF;
IF (clr_starttx = '1') THEN
-- Si on a fini de traiter une trame en Tx
 
ELSE
IF (wr_reg = '1') AND (adwr_spi = adreg_ctl) AND (shifter_spirx(3) = '1') THEN
 
reg_ctl_spi(3) <= '1';
END IF;
END IF;
IF (wr_reg = '1' AND adwr_spi = adreg_promctl) THEN
reg_promctl <= shifter_spirx;
ELSE
-- Le bit 3 ne doit durer qu'un seul coup de clk_sys
reg_promctl(3) <= '0';
END IF;
END IF;
END PROCESS;
-- Affectation des sorties en fonction des registres internes
cpy1 <= reg_ctl_spi(0);
cpy2 <= reg_ctl_spi(1);
rst_fifotx <= reg_ctl_spi(2);
start_tx <= reg_ctl_spi(3);
repli<= reg_ctl_spi(7);
tid <= reg_tid_spi;
 
--------------------------------------------
-- Process de gestion du registre de status
 
 
--------------------------------------------
gest_stat : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_stat_spi(7 DOWNTO 2) <= (OTHERS => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (l7_newframe1 = '1' AND l7_l2ok1 = '0') THEN
 
reg_stat_spi(2) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(2) <= reg_stat_spi(2) AND NOT(shifter_spirx(2));
END IF;
IF (l7_newframe2 = '1' AND l7_l2ok2 = '0') THEN
 
reg_stat_spi(3) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(3) <= reg_stat_spi(3) AND NOT(shifter_spirx(3));
END IF;
IF (l7_overflow1 = '1') THEN
 
reg_stat_spi(4) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(4) <= reg_stat_spi(4) AND NOT(shifter_spirx(4));
END IF;
IF (l7_overflow2 = '1') THEN
 
reg_stat_spi(5) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(5) <= reg_stat_spi(5) AND NOT(shifter_spirx(5));
END IF;
reg_stat_spi(6) <= NOT(fifotx_empty); -- Indique que la FIFO Tx n'est pas vide
END IF;
END PROCESS;
reg_stat_spi(1 DOWNTO 0) <= frm2 & frm1; -- Indication que les FIFO Rx sont pas vides
 
--------------------------------------------
-- Process de gestion du registre TRAFIC
--------------------------------------------
gest_trafic : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_trafic <= x"03";
mem_activity1 <= '1';
mem_activity2 <= '1';
ELSIF (clk_sys'EVENT AND clk_sys = '1') THEN
IF (wr_reg = '1' AND adwr_spi = adreg_ctl AND shifter_spirx(4) = '1') THEN
 
 
 
mem_activity2 <= activity2;
ELSE
 
IF (activity1 = '1') THEN
 
mem_activity1 <= '1';
END IF;
IF (activity2 = '1') THEN
mem_activity2 <= '1';
END IF;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
-- Process de gestion de la FIFO Tx
--------------------------------------------
difftx_free <= "10000000010" - fifotx_datacnt; -- Calcul du nombre d'octets dispo dans la FIFO 1026-cnt
 
 
 
 
wr_datatx_spi <= '1' WHEN (wr_reg = '1' AND adwr_spi = adreg_fifotx) ELSE '0';
clr_fifo_tx <= '0'; -- Spare pour l'instant on ne fait pas de clear de la fifo tx aval
 
 
-- ou bien en cours de transfert lorsque le module suivant est dispo
rd_datatx_sys <= '1' WHEN ((fsm_tx = idle_st AND fifotx_empty = '0' AND start_tx = '1') OR
(fsm_tx = senddat_st AND txdat_free = '1' AND fifotx_empty = '0')) ELSE
'0';
 
 
 
val_txdat <= NOT(fifotx_empty) WHEN (fsm_tx = idle_st) ELSE '1';
 
tx_dat <= datatx_rd_sys;
-- La fin de trame est valide si le module suivant est dispo
tx_eof <= txdat_free WHEN (fsm_tx = senddat_st AND cpt_tx = "00000001") ELSE '0';
 
gest_fsm_tx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_tx <= idle_st;
tx_sof <= '0';
cpt_tx <= (OTHERS => '0');
clr_starttx <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_tx IS
WHEN idle_st =>
 
IF (fifotx_empty = '0' AND start_tx = '1') THEN
 
cpt_tx <= datatx_rd_sys; -- On initialise le compteur avec la longueur de la trame (1er octet dans la FIFO)
 
 
clr_starttx <= '1'; -- On indique qu'on a pris en compte l'ordre de Tx
END IF;
 
WHEN senddat_st =>
 
clr_starttx <= '0'; -- Ne dure qu'un seul cycle
IF (txdat_free = '1') THEN
 
 
cpt_tx <= cpt_tx - 1; -- Dans ce cas on enregistre une donnee de moins
tx_sof <= '0'; -- On peut annuler le sof car on est sur que le module suivant l'a pris en comtpe
 
fsm_tx <= idle_st; -- On a fini
END IF;
END IF;
WHEN OTHERS =>
fsm_tx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fiftx : fifotx_spi
PORT MAP (
rst => rst_fifotx,
clk => clk_sys,
din => shifter_spirx,
wr_en => wr_datatx_spi,
rd_en => rd_datatx_sys,
dout => datatx_rd_sys,
full => OPEN,
empty => fifotx_empty,
data_count => fifotx_datacnt
);
--------------------------------------------
-- Process de gestion des FIFO Rx
--------------------------------------------
-- Ordre de lecture dans les FIFO Rx
rd_datarx_spi1 <= '1' WHEN (rd_reg = '1' AND adrd_spi = adreg_fiforx1) ELSE '0';
rd_datarx_spi2 <= '1' WHEN (rd_reg = '1' AND adrd_spi = adreg_fiforx2) ELSE '0';
 
 
l7_rd1buf <= (l7_rd AND NOT(sel_voie) AND comdispo AND NOT(soc)) WHEN (fsm_rx = recdat_st) ELSE
(l7_rd AND NOT(sel_voie));
l7_rd1 <= l7_rd1buf;
l7_rd2buf <= (l7_rd AND sel_voie AND comdispo AND NOT(soc)) WHEN (fsm_rx = recdat_st) ELSE
(l7_rd AND sel_voie);
l7_rd2 <= l7_rd2buf;
comdispo <= l7_comdispo1 WHEN (sel_voie = '0') ELSE l7_comdispo2;
soc <= l7_soc1 WHEN (sel_voie = '0') ELSE l7_soc2;
 
gest_fsm_rx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
l7_rd <= '0';
sel_voie <= '0';
fsm_rx <= idle_st;
frm2 <= '0';
frm1 <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_rx IS
WHEN idle_st =>
-- Etat d'attente qu'une FIFO Rx1 ou Rx2 soit vide et qu'il y'ait une trame disponible
-- sur la voie correspondante
frm1 <= NOT(fiforx_empty1); -- On indique s'il y'a des trames en FIFO Rx
frm2 <= NOT(fiforx_empty2);
IF ((l7_comdispo1 = '1' AND fiforx_empty1 = '1') AND
(l7_comdispo2 = '0' OR fiforx_empty2 = '0' OR sel_voie = '1')) THEN
 
 
 
 
fsm_rx <= pump_st;
ELSIF (l7_comdispo2 = '1' AND fiforx_empty2 = '1') THEN
sel_voie <= '1';
l7_rd <= '1';
fsm_rx <= pump_st;
ELSE
l7_rd <= '0';
END IF;
WHEN pump_st =>
 
fsm_rx <= recdat_st;
 
WHEN recdat_st =>
-- Etat de lecture de chaque octet de la trame
IF (soc = '1' OR comdispo = '0') THEN
 
l7_rd <= '0';
fsm_rx <= waitnotempty_st;
END IF;
WHEN waitnotempty_st =>
 
 
-- en cas de plusieurs petites trames dispo en DPRAM et donc garantir qu'on a
-- une seule trame en FIFO Rx
IF ((fiforx_empty1 = '0' AND sel_voie = '0') OR
(fiforx_empty2 = '0' AND sel_voie = '1')) THEN
fsm_rx <= idle_st;
END IF;
 
WHEN OTHERS =>
fsm_rx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fifrx1 : fiforx_spi
PORT MAP (
rst => NOT(rst_n),
clk => clk_sys,
din => l7_rx1,
wr_en => l7_rd1buf,
rd_en => rd_datarx_spi1,
dout => reg_fiforx1_spi,
full => OPEN,
empty => fiforx_empty1,
data_count => fiforx_datacnt1
);
-- Taille de la trame dans la FIFO : 255 si >= 256, sinon Nb octets dans la FIFO
reg_rx1size_spi <= x"FF" WHEN fiforx_datacnt1(10 DOWNTO 8) /= "000" ELSE
fiforx_datacnt1(7 DOWNTO 0);
 
inst_fifrx2 : fiforx_spi
PORT MAP (
rst => NOT(rst_n),
clk => clk_sys,
din => l7_rx2,
wr_en => l7_rd2buf,
rd_en => rd_datarx_spi2,
dout => reg_fiforx2_spi,
full => OPEN,
empty => fiforx_empty2,
data_count => fiforx_datacnt2
);
-- Taille de la trame dans la FIFO : 255 si >= 256, sinon Nb octets dans la FIFO
reg_rx2size_spi <= x"FF" WHEN fiforx_datacnt2(10 DOWNTO 8) /= "000" ELSE
fiforx_datacnt2(7 DOWNTO 0);
 
-------------------------------------------------
-- Signaux de gestion de l'I/F SPI vers la PROM
-------------------------------------------------
 
 
txprom_val <= wr_reg WHEN (adwr_spi = adreg_promtx) ELSE '0';
 
rxprom_next <= rd_reg WHEN (adrd_spi = adreg_promrx) ELSE '0';
-- Affectation des signaux de controle
prom_type_com <= reg_promctl(0);
prom_exec_com <= reg_promctl(3);
prom_rstn <= reg_promctl(4);
prom_nbread <= reg_promnbrd;
 
END rtl;
 
/tags/Release IPCommunication v1.0/if_picspi_sil4.vhd
0,0 → 1,741
--=============================================================================
-- TITRE : IF_PICSPI
-- DESCRIPTION :
 
 
 
-- FICHIER : if_picspi.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
-- 24/11/2014 DRA SATURN 1.01
 
 
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
 
ENTITY if_picspi_sil4 IS
GENERIC (
version : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"10");
PORT (
 
 
 
 
-- Interface SPI
sclk : IN STD_LOGIC; -- Clock SPI
sdi : IN STD_LOGIC; -- Bit IN SPI
sdo : OUT STD_LOGIC; -- Bit OUT SPI
ssn : IN STD_LOGIC; -- CSn SPI
 
-- Interface avec les autres modules du FPGA
 
-- Signaux de configurations
iid : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- Identifiant IID du FPGA
tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Identifiant TID du FPGA
cpy1 : OUT STD_LOGIC; -- Autorise la recopie du port 1 sur port 2
cpy2 : OUT STD_LOGIC; -- Autorise la recopie du port 2 sur port 1
repli : OUT STD_LOGIC; -- Indique que le module est en repli (gestion des LED)
topcyc : OUT STD_LOGIC;
enafiltdble : OUT STD_LOGIC;
-- Interfaces de lecture des trames port 1
 
 
 
l7_comdispo1 : IN STD_LOGIC; -- Indique qu'il y'a au moins une trame de dispo
 
l7_l2ok1 : IN STD_LOGIC; -- Indique si la couche transport est bonne ou non
 
activity1 : IN STD_LOGIC; -- Indique une trame sur le port 1 (couche 2)
-- Interfaces de lecture des trames port 2
 
 
 
l7_comdispo2 : IN STD_LOGIC; -- Indique qu'il y'a au moins une trame de dispo
 
l7_l2ok2 : IN STD_LOGIC; -- Indique si la couche transport est bonne ou non
 
activity2 : IN STD_LOGIC; -- Indique une trame sur le port 2 (couche 2)
 
 
 
val_txdat : OUT STD_LOGIC; -- Validant de chaque octet
 
tx_eof : OUT STD_LOGIC; -- Indique la fin d'une trame
txdat_free : IN STD_LOGIC; -- Indique que la couche transport en tx est libre
clr_fifo_tx : OUT STD_LOGIC; -- Permet de purger les FIFO Tx
-- Gestion de l'interface SPI PROM
 
txprom_val : OUT STD_LOGIC; -- Validant de txprom_data
 
 
 
 
prom_exec_com: OUT STD_LOGIC; -- Lance une commande dans le module de reprog
 
prom_nbread : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-- Nombre d'octet qu'il faut lire avec une commande de lecture
prom_rstn : OUT STD_LOGIC -- Reset du module de reprog
);
END if_picspi_sil4;
 
ARCHITECTURE rtl of if_picspi_sil4 is
 
SIGNAL fsm_tx : fsmtx_state;
 
 
SIGNAL fsm_rx : fsmrx_state;
 
 
CONSTANT adreg_iid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 7);
CONSTANT adreg_tid : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(8, 7);
CONSTANT adreg_ctl : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(9, 7);
CONSTANT adreg_stat : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(10, 7);
CONSTANT adreg_rxsize1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(11, 7);
CONSTANT adreg_rxsize2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(12, 7);
CONSTANT adreg_txfree : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(13, 7);
CONSTANT adreg_fiforx1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(14, 7);
CONSTANT adreg_fiforx2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(15, 7);
CONSTANT adreg_fifotx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(16, 7);
CONSTANT adreg_version : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(17, 7);
CONSTANT adreg_promtx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(18, 7);
CONSTANT adreg_promrx : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(19, 7);
CONSTANT adreg_promctl : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(20, 7);
CONSTANT adreg_promnbrd : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(21, 7);
CONSTANT adreg_trafic : STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(22, 7);
 
SIGNAL reg_tid_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_ctl_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_stat_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_rx1size_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_rx2size_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_txfree_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_fiforx1_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_fiforx2_spi : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_promctl : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_promnbrd : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg_trafic : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Signaux de gestion de l'interface SPI
SIGNAL cpt_bitspi : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Compte le nombre de bits sur un cycle SPI
SIGNAL cptbit_tx : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Compte le nombre de bits en Tx sur le SPI
 
 
 
SIGNAL dat_adn : STD_LOGIC; -- Indique si l'octet en cours sur SPI est une data ou l'adresse
 
 
SIGNAL spi_encours : STD_LOGIC; -- Indique un cycle SPI en cours
 
 
SIGNAL rd_reg : STD_LOGIC; -- 1 pulse pour lire le registre adrd_spi
 
 
 
 
 
 
 
 
 
-- Signaux de gestion interne et changement d'horloge
SIGNAL difftx_free : STD_LOGIC_VECTOR(10 DOWNTO 0); -- Pour calculer la taille dispo en FIFO Tx sur 8 bits
 
 
SIGNAL rd_datatx_sys : STD_LOGIC; -- Ordre de lecture dans la FIFO Tx
 
SIGNAL fifotx_empty : STD_LOGIC; -- Indique une FFIO Tx vide
SIGNAL rst_fifotx : STD_LOGIC; -- Effacement FIFO Tx
SIGNAL cpt_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Compteur d'octet pour relire la FIFO Tx
 
 
 
SIGNAL rd_datarx_spi1 : STD_LOGIC; -- Ordre de lecture dans la FIFO Rx1
SIGNAL fiforx_empty1 : STD_LOGIC; -- FIFO Rx1 vide
 
 
SIGNAL rd_datarx_spi2 : STD_LOGIC; -- Ordre de lecture dans la FIFO Rx2
SIGNAL fiforx_empty2 : STD_LOGIC; -- FIFO Rx2 vide
 
SIGNAL l7_rd : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx1 ou l7_rx2
SIGNAL l7_rd1buf : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx1
SIGNAL l7_rd2buf : STD_LOGIC; -- Demande un octet de plus sur le bus l7_rx2
 
 
 
 
 
 
 
 
COMPONENT fifotx_spi
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
COMPONENT fiforx_spi
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
--------------------------------------------
-- Module de Delay du SDI
--------------------------------------------
IODELAY2_inst : IODELAY2
generic map (
COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
IDELAY_TYPE => "FIXED", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
-- or "DIFF_PHASE_DETECTOR"
 
ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
SERDES_MODE => "NONE", -- "NONE", "MASTER" or "SLAVE"
SIM_TAPDELAY_VALUE => 71 -- Per tap delay used for simulation in ps
)
port map (
BUSY => OPEN, -- 1-bit output: Busy output after CAL
DATAOUT => sdi_delayed,-- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => OPEN, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => OPEN, -- 1-bit output: Delayed data output
TOUT => OPEN, -- 1-bit output: Delayed 3-state output
CAL => '0', -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => '0', -- 1-bit input: Clock input
IDATAIN => sdi, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
INC => '0', -- 1-bit input: Increment / decrement input
IOCLK0 => '0', -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
RST => '0', -- 1-bit input: Reset to zero or 1/2 of total delay period
T => '0' -- 1-bit input: 3-state input signal
);
 
--------------------------------------------
 
--------------------------------------------
serrx_spi : PROCESS(sclk)
BEGIN
IF (sclk'EVENT AND sclk = '1') THEN
 
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
sertx_spi : PROCESS(sclk, ssn)
BEGIN
IF (ssn = '1') THEN
-- Tant que le ssn n'est pas actif, on reste inactif
shifter_spitx <= (OTHERS => '0');
cptbit_tx <= "000";
front_ssn <= '1';
ELSIF (sclk'EVENT and sclk = '0') THEN
-- Sur front descendant de sclk
 
cptbit_tx <= cptbit_tx + 1; -- a chaque sclk on compte 1 bit
IF (cptbit_tx = "000")THEN
-- Pour le 1er sclk de chaque octet
IF (front_ssn = '1') THEN
 
 
ELSE
 
shifter_spitx <= data_rdspi;
END IF;
ELSE
-- Pour tous les autres bist, on fait un shift
shifter_spitx <= shifter_spitx(6 DOWNTO 0) & '0';
END IF;
END IF;
END PROCESS;
sdo <= shifter_spitx(7);
 
--------------------------------------------
-- Process de gestion d'un cycle SPI
 
 
 
-- mais rendue effective que si le PIC la veut vraiment (i.e. le cycle SPI n'est pas
-- interrompu avant)
--------------------------------------------
managespi : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
ssnr <= "111";
sclkr <= "111";
spi_encours <= '0';
cpt_bitspi <= "000";
dat_adn <= '0';
rwn_spi <= '0';
adrd_spi <= (OTHERS => '0');
rd_reg <= '0';
latch_rdspi <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
 
 
IF (ssn_fall = '1') THEN
-- Initialisations sur activation de ssn
spi_encours <= '1'; -- On est en cours de traitement
 
 
ELSIF (ssn_rise = '1') THEN
-- A la fin du scycle spi
spi_encours <= '0';
ELSE
 
IF (spi_encours = '1') THEN
-- Si on est dans un cycle spi
IF (sclk_rise = '1') THEN
-- Sur chaque front montant de sclk
cpt_bitspi <= cpt_bitspi + 1; -- On comtpe un bit de plus
IF (cpt_bitspi = "110") THEN
 
IF (dat_adn = '0') THEN
-- Si c'est le 1er octet de la trame SPI
 
ELSE
 
 
IF (adrd_spi /= adreg_fiforx1 AND
adrd_spi /= adreg_fiforx2 AND
adrd_spi /= adreg_fifotx AND
adrd_spi /= adreg_promtx AND
adrd_spi /= adreg_promrx) THEN
 
adrd_spi <= adrd_spi + 1;
END IF;
END IF;
 
ELSIF (cpt_bitspi = "111") THEN
 
 
IF (dat_adn = '0') THEN
-- Si c'est le 1er octet de la trame SPI
 
END IF;
ELSIF (cpt_bitspi = "000") THEN
 
 
END IF;
ELSE
-- En dehors des front de sclk, on assure que les signaux de lecture ne durent qu'un cycle
rd_reg <= '0';
latch_rdspi <= '0';
END IF;
ELSE
-- En dehors d'un cycle SPI, on assure qu'on fait pas de lecture non voulue
rd_reg <= '0';
latch_rdspi <= '0';
END IF;
END IF;
END IF;
END PROCESS;
 
 
 
 
-- - on est en write
wr_reg <= dat_adn AND NOT(rwn_spi) WHEN (sclk_rise = '1' AND cpt_bitspi = "111") ELSE '0';
 
ssn_fall <= ssnr(2) AND NOT(ssnr(1));
 
ssn_rise <= NOT(ssnr(2)) AND ssnr(1);
 
sclk_rise <= NOT(sclkr(2)) AND sclkr(1);
 
--------------------------------------------
-- Process de latch d'un registre en lecture
--------------------------------------------
mux_read: PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
data_rdspi <= (OTHERS => '0');
ELSIF (clk_sys'event AND clk_sys ='1') THEN
IF (latch_rdspi = '1') THEN
 
CASE adrd_spi IS
WHEN adreg_iid => data_rdspi <= iid(63 DOWNTO 56);
WHEN adreg_iid+1 => data_rdspi <= iid(55 DOWNTO 48);
WHEN adreg_iid+2 => data_rdspi <= iid(47 DOWNTO 40);
WHEN adreg_iid+3 => data_rdspi <= iid(39 DOWNTO 32);
WHEN adreg_iid+4 => data_rdspi <= iid(31 DOWNTO 24);
WHEN adreg_iid+5 => data_rdspi <= iid(23 DOWNTO 16);
WHEN adreg_iid+6 => data_rdspi <= iid(15 DOWNTO 8);
WHEN adreg_iid+7 => data_rdspi <= iid(7 DOWNTO 0);
WHEN adreg_tid => data_rdspi <= reg_tid_spi;
WHEN adreg_ctl => data_rdspi <= reg_ctl_spi;
WHEN adreg_stat => data_rdspi <= reg_stat_spi;
WHEN adreg_rxsize1=> data_rdspi <= reg_rx1size_spi;
WHEN adreg_rxsize2=> data_rdspi <= reg_rx2size_spi;
WHEN adreg_txfree => data_rdspi <= reg_txfree_spi;
WHEN adreg_fiforx1=> data_rdspi <= reg_fiforx1_spi;
WHEN adreg_fiforx2=> data_rdspi <= reg_fiforx2_spi;
-- WHEN adreg_fifotx => data_rdspi <= dummy -- Ce registre est Write Only
WHEN adreg_version=> data_rdspi <= version;
WHEN adreg_promctl=> data_rdspi <= rxprom_val & reg_promctl(6 DOWNTO 4) & prom_busy & reg_promctl(2 DOWNTO 0);
WHEN adreg_promnbrd=>data_rdspi <= reg_promnbrd;
-- WHEN adreg_promtx => data_rdspi <= dummy -- Ce registre est Write Only
WHEN adreg_promrx=> data_rdspi <= rxprom_dat;
WHEN adreg_trafic=> data_rdspi <= reg_trafic;
WHEN OTHERS => data_rdspi <= reg_stat_spi;
END CASE;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
write_reg : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_tid_spi <= x"8F";
reg_ctl_spi <= x"84";
reg_promctl <= x"00";
reg_promnbrd <= x"00";
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (wr_reg = '1') THEN
 
CASE adwr_spi IS
WHEN adreg_tid => reg_tid_spi <= shifter_spirx;
WHEN adreg_ctl =>
 
reg_ctl_spi(7 DOWNTO 5) <= shifter_spirx(7 DOWNTO 5);
reg_ctl_spi(2 DOWNTO 0) <= shifter_spirx(2 DOWNTO 0);
WHEN adreg_promnbrd => reg_promnbrd <= shifter_spirx;
WHEN OTHERS =>
END CASE;
END IF;
IF (clr_starttx = '1') THEN
-- Si on a fini de traiter une trame en Tx
 
ELSE
IF (wr_reg = '1') AND (adwr_spi = adreg_ctl) AND (shifter_spirx(3) = '1') THEN
 
reg_ctl_spi(3) <= '1';
END IF;
END IF;
IF (wr_reg = '1' AND adwr_spi = adreg_promctl) THEN
reg_promctl <= shifter_spirx;
ELSE
-- Le bit 3 ne doit durer qu'un seul coup de clk_sys
reg_promctl(3) <= '0';
END IF;
END IF;
END PROCESS;
-- Affectation des sorties en fonction des registres internes
cpy1 <= reg_ctl_spi(0);
cpy2 <= reg_ctl_spi(1);
rst_fifotx <= reg_ctl_spi(2);
start_tx <= reg_ctl_spi(3);
topcyc <= reg_ctl_spi(4);
enafiltdble <= reg_ctl_spi(6);
repli <= reg_ctl_spi(7);
tid <= reg_tid_spi;
 
--------------------------------------------
-- Process de gestion du registre de status
 
 
--------------------------------------------
gest_stat : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_stat_spi(7 DOWNTO 2) <= (OTHERS => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (l7_newframe1 = '1' AND l7_l2ok1 = '0') THEN
 
reg_stat_spi(2) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(2) <= reg_stat_spi(2) AND NOT(shifter_spirx(2));
END IF;
IF (l7_newframe2 = '1' AND l7_l2ok2 = '0') THEN
 
reg_stat_spi(3) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(3) <= reg_stat_spi(3) AND NOT(shifter_spirx(3));
END IF;
IF (l7_overflow1 = '1') THEN
 
reg_stat_spi(4) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(4) <= reg_stat_spi(4) AND NOT(shifter_spirx(4));
END IF;
IF (l7_overflow2 = '1') THEN
 
reg_stat_spi(5) <= '1';
ELSIF (wr_reg = '1' AND adwr_spi = adreg_stat) THEN
reg_stat_spi(5) <= reg_stat_spi(5) AND NOT(shifter_spirx(5));
END IF;
reg_stat_spi(6) <= NOT(fifotx_empty); -- Indique que la FIFO Tx n'est pas vide
END IF;
END PROCESS;
reg_stat_spi(1 DOWNTO 0) <= frm2 & frm1; -- Indication que les FIFO Rx sont pas vides
 
--------------------------------------------
-- Process de gestion du registre TRAFIC
--------------------------------------------
gest_trafic : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
reg_trafic <= x"03";
mem_activity1 <= '1';
mem_activity2 <= '1';
ELSIF (clk_sys'EVENT AND clk_sys = '1') THEN
IF (wr_reg = '1' AND adwr_spi = adreg_ctl AND shifter_spirx(4) = '1') THEN
 
 
 
mem_activity2 <= activity2;
ELSE
 
IF (activity1 = '1') THEN
 
mem_activity1 <= '1';
END IF;
IF (activity2 = '1') THEN
mem_activity2 <= '1';
END IF;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
-- Process de gestion de la FIFO Tx
--------------------------------------------
difftx_free <= "10000000010" - fifotx_datacnt; -- Calcul du nombre d'octets dispo dans la FIFO 1026-cnt
 
 
 
 
wr_datatx_spi <= '1' WHEN (wr_reg = '1' AND adwr_spi = adreg_fifotx) ELSE '0';
clr_fifo_tx <= '0'; -- Spare pour l'instant on ne fait pas de clear de la fifo tx aval
 
 
-- ou bien en cours de transfert lorsque le module suivant est dispo
rd_datatx_sys <= '1' WHEN ((fsm_tx = idle_st AND fifotx_empty = '0' AND start_tx = '1') OR
(fsm_tx = senddat_st AND txdat_free = '1' AND fifotx_empty = '0')) ELSE
'0';
 
 
 
val_txdat <= NOT(fifotx_empty) WHEN (fsm_tx = idle_st) ELSE '1';
 
tx_dat <= datatx_rd_sys;
-- La fin de trame est valide si le module suivant est dispo
tx_eof <= txdat_free WHEN (fsm_tx = senddat_st AND cpt_tx = "00000001") ELSE '0';
 
gest_fsm_tx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_tx <= idle_st;
tx_sof <= '0';
cpt_tx <= (OTHERS => '0');
clr_starttx <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_tx IS
WHEN idle_st =>
 
IF (fifotx_empty = '0' AND start_tx = '1') THEN
 
cpt_tx <= datatx_rd_sys; -- On initialise le compteur avec la longueur de la trame (1er octet dans la FIFO)
 
 
clr_starttx <= '1'; -- On indique qu'on a pris en compte l'ordre de Tx
END IF;
 
WHEN senddat_st =>
 
clr_starttx <= '0'; -- Ne dure qu'un seul cycle
IF (txdat_free = '1') THEN
 
 
cpt_tx <= cpt_tx - 1; -- Dans ce cas on enregistre une donnee de moins
tx_sof <= '0'; -- On peut annuler le sof car on est sur que le module suivant l'a pris en comtpe
 
fsm_tx <= idle_st; -- On a fini
END IF;
END IF;
WHEN OTHERS =>
fsm_tx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fiftx : fifotx_spi
PORT MAP (
rst => rst_fifotx,
clk => clk_sys,
din => shifter_spirx,
wr_en => wr_datatx_spi,
rd_en => rd_datatx_sys,
dout => datatx_rd_sys,
full => OPEN,
empty => fifotx_empty,
data_count => fifotx_datacnt
);
--------------------------------------------
-- Process de gestion des FIFO Rx
--------------------------------------------
-- Ordre de lecture dans les FIFO Rx
rd_datarx_spi1 <= '1' WHEN (rd_reg = '1' AND adrd_spi = adreg_fiforx1) ELSE '0';
rd_datarx_spi2 <= '1' WHEN (rd_reg = '1' AND adrd_spi = adreg_fiforx2) ELSE '0';
 
 
l7_rd1buf <= (l7_rd AND NOT(sel_voie) AND comdispo AND NOT(soc)) WHEN (fsm_rx = recdat_st) ELSE
(l7_rd AND NOT(sel_voie));
l7_rd1 <= l7_rd1buf;
l7_rd2buf <= (l7_rd AND sel_voie AND comdispo AND NOT(soc)) WHEN (fsm_rx = recdat_st) ELSE
(l7_rd AND sel_voie);
l7_rd2 <= l7_rd2buf;
comdispo <= l7_comdispo1 WHEN (sel_voie = '0') ELSE l7_comdispo2;
soc <= l7_soc1 WHEN (sel_voie = '0') ELSE l7_soc2;
 
gest_fsm_rx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
l7_rd <= '0';
sel_voie <= '0';
fsm_rx <= idle_st;
frm2 <= '0';
frm1 <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_rx IS
WHEN idle_st =>
-- Etat d'attente qu'une FIFO Rx1 ou Rx2 soit vide et qu'il y'ait une trame disponible
-- sur la voie correspondante
frm1 <= NOT(fiforx_empty1); -- On indique s'il y'a des trames en FIFO Rx
frm2 <= NOT(fiforx_empty2);
IF ((l7_comdispo1 = '1' AND fiforx_empty1 = '1') AND
(l7_comdispo2 = '0' OR fiforx_empty2 = '0' OR sel_voie = '1')) THEN
 
 
 
 
fsm_rx <= pump_st;
ELSIF (l7_comdispo2 = '1' AND fiforx_empty2 = '1') THEN
sel_voie <= '1';
l7_rd <= '1';
fsm_rx <= pump_st;
ELSE
l7_rd <= '0';
END IF;
WHEN pump_st =>
 
fsm_rx <= recdat_st;
 
WHEN recdat_st =>
-- Etat de lecture de chaque octet de la trame
IF (soc = '1' OR comdispo = '0') THEN
 
l7_rd <= '0';
fsm_rx <= waitnotempty_st;
END IF;
WHEN waitnotempty_st =>
 
 
-- en cas de plusieurs petites trames dispo en DPRAM et donc garantir qu'on a
-- une seule trame en FIFO Rx
IF ((fiforx_empty1 = '0' AND sel_voie = '0') OR
(fiforx_empty2 = '0' AND sel_voie = '1')) THEN
fsm_rx <= idle_st;
END IF;
 
WHEN OTHERS =>
fsm_rx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fifrx1 : fiforx_spi
PORT MAP (
rst => NOT(rst_n),
clk => clk_sys,
din => l7_rx1,
wr_en => l7_rd1buf,
rd_en => rd_datarx_spi1,
dout => reg_fiforx1_spi,
full => OPEN,
empty => fiforx_empty1,
data_count => fiforx_datacnt1
);
-- Taille de la trame dans la FIFO : 255 si >= 256, sinon Nb octets dans la FIFO
reg_rx1size_spi <= x"FF" WHEN fiforx_datacnt1(10 DOWNTO 8) /= "000" ELSE
fiforx_datacnt1(7 DOWNTO 0);
 
inst_fifrx2 : fiforx_spi
PORT MAP (
rst => NOT(rst_n),
clk => clk_sys,
din => l7_rx2,
wr_en => l7_rd2buf,
rd_en => rd_datarx_spi2,
dout => reg_fiforx2_spi,
full => OPEN,
empty => fiforx_empty2,
data_count => fiforx_datacnt2
);
-- Taille de la trame dans la FIFO : 255 si >= 256, sinon Nb octets dans la FIFO
reg_rx2size_spi <= x"FF" WHEN fiforx_datacnt2(10 DOWNTO 8) /= "000" ELSE
fiforx_datacnt2(7 DOWNTO 0);
 
-------------------------------------------------
-- Signaux de gestion de l'I/F SPI vers la PROM
-------------------------------------------------
 
 
txprom_val <= wr_reg WHEN (adwr_spi = adreg_promtx) ELSE '0';
 
rxprom_next <= rd_reg WHEN (adrd_spi = adreg_promrx) ELSE '0';
-- Affectation des signaux de controle
prom_type_com <= reg_promctl(0);
prom_exec_com <= reg_promctl(3);
prom_rstn <= reg_promctl(4);
prom_nbread <= reg_promnbrd;
 
END rtl;
 
/tags/Release IPCommunication v1.0/if_promspi.vhd
0,0 → 1,297
--=============================================================================
-- TITRE : IF_PROMSPI
-- DESCRIPTION :
 
 
 
-- Il supporte 2 types de commandes selon type_com et sur ordre de exec_com
 
 
 
 
-- | sur RX_DAT
-- FICHIER : if_promspi.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY if_promspi IS
GENERIC (
 
 
);
PORT (
 
 
 
 
 
 
 
spi_sdo : OUT STD_LOGIC; -- Data Write
spi_sdi : IN STD_LOGIC; -- Data Read
spi_clk : OUT STD_LOGIC; -- SPI Clock en (CPOL, CPHA) = (0, 0)
 
 
tx_val : IN STD_LOGIC; -- Validant du bus tx_dat
 
 
 
 
 
 
 
);
END if_promspi;
 
ARCHITECTURE rtl of if_promspi is
CONSTANT com_wronly : STD_LOGIC := '0'; -- Commande de type Write Only
CONSTANT com_wrrd : STD_LOGIC := '1'; -- Commande de type Write + Read (nb_read)
SIGNAL rst : STD_LOGIC; -- Reset des FIFO Tx et Rx
 
SIGNAL rise_clk : STD_LOGIC; -- Front montant de l'horloge SPI
SIGNAL fall_clk : STD_LOGIC; -- Front descendant de l'horloge SPI
 
SIGNAL mask_clk : STD_LOGIC; -- Signal de masque de l'horloge SPI
SIGNAL cpt_bit : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Compteur de bit pour le ser/deser
 
SIGNAL fifotx_rd : STD_LOGIC; -- Signal de lecture de la FIFO Tx
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Data lue dans la FIFO Tx
SIGNAL fifotx_empty : STD_LOGIC; -- FIFO Tx vide
 
SIGNAL fiforx_empty : STD_LOGIC; -- FIFO Rx vide
SIGNAL shifter_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Serialisateur
 
SIGNAL read_stat : STD_LOGIC; -- A 1 lors d'une lecture du registre de status
 
 
TYPE fsmspi_typ IS (idle_st, latchcom_st, sendcom_st, getdat_st, releasecs_st, readstat_st, endcom_st);
SIGNAL fsm_spi : fsmspi_typ;
-- FIFO (256 x 8bits) TX et RX en FWFT
COMPONENT fifo_spi
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
 
BEGIN
rst <= NOT(rst_n);
------------------------------------------
-- Process de generation de la clock SPI
------------------------------------------
gen_clk : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
div_clk <= (OTHERS => '0');
fallclk_r <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
div_clk <= div_clk + 1;
fallclk_r <= fall_clk;
END IF;
END PROCESS;
 
 
rise_clk <= '1' WHEN (div_clk = CONV_STD_LOGIC_VECTOR(2**(div_rate-1)-1, div_rate)) ELSE '0';
 
fall_clk <= '1' WHEN (div_clk = CONV_STD_LOGIC_VECTOR(2**div_rate-1, div_rate)) ELSE '0';
 
-------------------------------------------------
 
-------------------------------------------------
spi_sdo <= shifter_tx(7); -- On SER les data MSB first
 
man_fm : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_spi <= idle_st;
spi_csn <= '1';
mask_clk <= '0';
spi_busy <= '1'; -- En reset, on indique le SPI est inutilisable
shifter_tx <= (OTHERS => '0');
fifotx_rd <= '0';
shifter_rx <= (OTHERS => '0');
fiforx_wr <= '0';
read_stat <= '0';
latch_typcom <= '0';
cpt_bit <= "000";
cpt_byt <= (OTHERS => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_spi IS
WHEN idle_st =>
 
IF (exec_com = '1' AND fifotx_empty = '0') THEN
 
 
 
fsm_spi <= latchcom_st;
ELSE
spi_busy <= '0';
END IF;
 
WHEN latchcom_st =>
-- Etat d'attent du 1er front montant de sclk
IF (rise_clk = '1') THEN
spi_csn <= '0'; -- On active la Flash
 
 
fsm_spi <= sendcom_st; -- On va envoyer la commande
END IF;
WHEN sendcom_st =>
-- Etat de transmission de la commande
IF (fall_clk = '1') THEN
-- Sur chaque front descendant de la clock SPI
IF (cpt_bit = "000") THEN
-- Si on a transmis tous les bits (ou bien aucun pour le premier passage)
cpt_bit <= "111";
IF (fifotx_empty = '0' AND read_stat = '0') THEN
 
-- note : si read_stat = 1 et fifo Tx n'est pas vide est un cas d'erreur
shifter_tx <= data_tx; -- On va le SER
fifotx_rd <= '1'; -- On lit l'octet suivant dans la FIFO
ELSE
-- Si on a fini de transmettre les octets
IF (latch_typcom = com_wrrd or read_stat = '1') THEN
-- Si c'est une commande de type WR+RD ou bien si on lit le registre de staut
 
fsm_spi <= getdat_st;
ELSE
-- Si c'est une commande WR only
mask_clk <= '0'; -- On masque l'horloge
 
END IF;
END IF;
ELSE
-- Si on a pas SER tous les bits de l'octets
shifter_tx <= shifter_tx(6 DOWNTO 0) & '0';
cpt_bit <= cpt_bit - 1;
fifotx_rd <= '0';
END IF;
ELSE
-- On s'assure que le read dans la FIFO Tx ne dure qu'un cycle
fifotx_rd <= '0';
IF (fallclk_r = '1') THEN
 
 
mask_clk <= '1';
END IF;
END IF;
 
WHEN getdat_st =>
 
 
IF (rise_clk = '1') THEN
 
shifter_rx <= shifter_rx(6 DOWNTO 0) & spi_sdi; -- On DESER MSB first
END IF;
IF (fall_clk = '1') THEN
IF (cpt_bit = "000") THEN
-- Si on a DESER les 8 bits
 
IF ((latch_typcom = com_wrrd AND cpt_byt = CONV_STD_LOGIC_VECTOR(1, cpt_byt'LENGTH)) OR
(read_stat = '1' AND spi_sdi = '0')) THEN
 
 
mask_clk <= '0'; -- On a fini
read_stat <= '0';
fsm_spi <= endcom_st;
ELSE
 
cpt_byt <= cpt_byt - 1;
END IF;
cpt_bit <= "111";
ELSE
-- Si on n'a pas encore 7 bits
cpt_bit <= cpt_bit - 1;
fiforx_wr <= '0';
END IF;
ELSE
-- On s'assure que le signal de WR dans la FIFO Rx ne dure que 1 cycle
fiforx_wr <= '0';
END IF;
WHEN releasecs_st =>
-- Etat de relachement du CS avant envoie de la commande de lecture du status.
IF (rise_clk = '1') THEN
spi_csn <= '1';
-- On ajuste la tempo pour assurer que le release du CS fait bien 100ns quel que soit la clock SPI
cpt_byt <= CONV_STD_LOGIC_VECTOR(100*spiclk_freq/1000+1, cpt_byt'LENGTH);
fsm_spi <= readstat_st;
END IF;
 
WHEN readstat_st =>
-- Etat de temporisation avant d'envoyer la commande de lecture du status
IF (rise_clk = '1') THEN
cpt_byt <= cpt_byt - 1;
END IF;
IF (fall_clk = '1' AND cpt_byt = CONV_STD_LOGIC_VECTOR(0, cpt_byt'LENGTH)) THEN
spi_csn <= '0'; -- On recommence un cycle SPI
cpt_bit <= "111";
shifter_tx <= x"05"; -- On force la transmission de la commande de lecture du status
read_stat <= '1';
fsm_spi <= sendcom_st;
END IF;
 
WHEN endcom_st =>
 
fiforx_wr <= '0';
IF (rise_clk = '1') THEN
spi_busy <= '0';
spi_csn <= '1';
fsm_spi <= idle_st;
END IF;
WHEN OTHERS =>
fsm_spi <= idle_st;
END CASE;
END IF;
END PROCESS;
 
inst_fiftx : fifo_spi
PORT MAP (
clk => clk_sys,
rst => rst,
din => tx_dat,
wr_en => tx_val,
rd_en => fifotx_rd,
dout => data_tx,
full => OPEN,
empty => fifotx_empty
);
 
inst_fifrx : fifo_spi
PORT MAP (
clk => clk_sys,
rst => rst,
din => shifter_rx,
wr_en => fiforx_wr,
rd_en => rx_next,
dout => rx_dat,
full => OPEN,
empty => fiforx_empty
);
rx_val <= NOT(fiforx_empty);
 
END rtl;
 
/tags/Release IPCommunication v1.0/if_smi.vhd
0,0 → 1,148
--=============================================================================
-- TITRE : IF_SPI
-- DESCRIPTION :
 
 
 
-- Il supporte 3 types de commandes selon type_com et sur ordre de exec_com
 
 
 
 
-- | sur RX_DAT
-- FICHIER : if_spi.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 29/02/2012 DRA CONCERTO V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
ENTITY if_smi IS
GENERIC (
 
);
PORT (
 
 
 
 
 
mdc : OUT STD_LOGIC; -- Signal MDC de l'IF SMI
mdio : INOUT STD_LOGIC; -- Signal MDIO de l'IF SMI
smi_datwr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
smi_datrd : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
smi_com : IN STD_LOGIC
);
END if_smi;
 
ARCHITECTURE rtl of if_smi is
 
SIGNAL rise_clk : STD_LOGIC; -- Front montant de l'horloge SMI
SIGNAL fall_clk : STD_LOGIC; -- Front descendant de l'horloge SMI
SIGNAL mask_clk : STD_LOGIC; -- Signal de masque de l'horloge SMI
SIGNAL cpt_bit : STD_LOGIC_VECTOR(6 DOWNTO 0); -- Compteur de bit pour le ser/deser
SIGNAL shifter_tx : STD_LOGIC_VECTOR(63 DOWNTO 0); -- SER Tx
SIGNAL shifter_rx : STD_LOGIC_VECTOR(15 DOWNTO 0); -- DESER Rx
SIGNAL txena : STD_LOGIC; -- Pour sortir le MDIO du 'Z'
 
 
BEGIN
------------------------------------------
-- Process de generation de la clock SMI
------------------------------------------
gen_clk : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
div_clk <= (OTHERS => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
div_clk <= div_clk + 1;
END IF;
END PROCESS;
 
 
rise_clk <= '1' WHEN (div_clk = CONV_STD_LOGIC_VECTOR(2**(div_rate-1)-1, div_rate)) ELSE '0';
 
fall_clk <= '1' WHEN (div_clk = CONV_STD_LOGIC_VECTOR(2**div_rate-1, div_rate)) ELSE '0';
 
mdio <= 'Z' WHEN (txena = '0') ELSE shifter_tx(63);
smi_datrd <= shifter_rx;
 
rx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
shifter_rx <= (others => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (mask_clk = '1' AND rise_clk = '1') THEN
shifter_rx <= shifter_rx(14 DOWNTO 0) & mdio;
END IF;
END IF;
END PROCESS;
 
com: PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
sendcom <= '0';
txena <= '0';
com_rdwrn <= '0';
mask_clk <= '0';
shifter_tx <= (others => '1');
cpt_bit <= (OTHERS => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (sendcom = '1') THEN
IF (fall_clk = '1') THEN
IF (cpt_bit = "0000000") THEN
mask_clk <= '1';
txena <= '1';
cpt_bit <= cpt_bit + 1;
ELSE
IF (cpt_bit /= "1000000") THEN
cpt_bit <= cpt_bit + 1;
shifter_tx <= shifter_tx(62 downto 0) & '0';
ELSE
mask_clk <= '0';
sendcom <= '0';
txena <= '0';
END IF;
-- IF (cpt_bit = "0110000") AND (com_rdwrn = '1') THEN
IF (cpt_bit = "0101110") AND (com_rdwrn = '1') THEN
txena <= '0';
END IF;
END IF;
END IF;
ELSE
IF (smi_com = '1') THEN
cpt_bit <= (OTHERS => '0');
 
shifter_tx <= x"FFFFFFFF" & smi_datwr; --"0101" & "00000" & "11011" & "00" & "1000000000000000";
IF (smi_datwr(29 DOWNTO 28) = "01") THEN
com_rdwrn <= '0';
ELSIF (smi_datwr(29 DOWNTO 28) = "00") THEN
 
ELSE
com_rdwrn <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
 
END rtl;
 
/tags/Release IPCommunication v1.0/jk_chgclk.vhd
0,0 → 1,85
--=============================================================================
-- TITRE : jk_chgclk
-- DESCRIPTION :
-- Assure la transformation d'un pulse synchrone de clk1
-- en un pulse de clk2
-- Il faut
-- - que freq(clk1) >> freq(clk2);
 
 
 
 
-- le front montant avec clk1 et clearer la JK
 
-- FICHIER : jk_chgclk.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 29/02/2012 DRA CONCERTO V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
ENTITY jk_chgclk IS
PORT (
 
clk1 : IN STD_LOGIC; -- Horloge principale 1
clk2 : IN STD_LOGIC; -- Horloge principale 2
 
pulseout : OUT STD_LOGIC -- Pulse sur clk2 sur front montant de pulse1
);
END jk_chgclk;
 
ARCHITECTURE rtl of jk_chgclk is
SIGNAL clk1_to_clk2 : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Triple FF pour le front de JK avec clk2
SIGNAL clk2_to_clk1 : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Triple FF pour le front de front_jk avec clk1
 
 
 
BEGIN
 
toclk2 : PROCESS(clk2, rstn)
BEGIN
IF (rstn = '0') THEN
clk1_to_clk2 <= (OTHERS => '0');
ELSIF (clk2'EVENT and clk2 = '1') THEN
-- Triple FF sur la bascule JK
clk1_to_clk2 <= clk1_to_clk2(1 DOWNTO 0) & jk_clk1;
END IF;
END PROCESS;
front_jk <= clk1_to_clk2(2) AND NOT(clk1_to_clk2(1));
pulseout <= front_jk;
 
 
backtoclk1 : PROCESS(clk1, rstn)
BEGIN
IF (rstn = '0') THEN
clk2_to_clk1 <= (OTHERS => '0');
jk_clk1 <= '0';
ELSIF (clk1'EVENT and clk1 = '1') THEN
clk2_to_clk1 <= clk2_to_clk1(1 DOWNTO 0) & front_jk; -- Triple FF sur le front_jk
IF (clk2_to_clk1(2) = '1' AND clk2_to_clk1(1) = '0') THEN
 
jk_clk1 <= '0';
ELSIF (pulsein = '1') THEN
-- A chaque pulse sur pulse1
 
END IF;
END IF;
END PROCESS;
 
END rtl;
 
/tags/Release IPCommunication v1.0/layer2_rx.vhd
0,0 → 1,285
--=============================================================================
-- TITRE : LAYER2_RX
-- DESCRIPTION :
 
 
 
-- dans le flux de sortie mais le CRC oui
-- Limitation : Il faut au moins 1 pulse de clk_sys au niveau '0' entre 2
 
 
-- FICHIER : layer2_rx.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity layer2_rx is
GENERIC (
nbbit_div : INTEGER := 10); -- Nombre de bits pour coder le diviseur d'horloge
PORT (
 
 
 
ad_mio : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Adresse logique du MIO (TID)
 
-- Interfaces ves le module SWITCH
sw_ena : OUT STD_LOGIC; -- Indique qu'on est entre 2 trames (autorise le switch du tx)
 
val_in : IN STD_LOGIC; -- validant du bus dat_in
 
-- Interfaces vers le module FRAME_STORE
 
 
 
 
val_out : OUT STD_LOGIC -- Validant du bus dat_out
);
end layer2_rx;
 
architecture rtl of layer2_rx is
-- Buffer prenant la valeur du flux de sortie
SIGNAL dat_out_buf: STD_LOGIC_VECTOR(7 downto 0);
 
 
 
SIGNAL cpt_timer: STD_LOGIC_VECTOR(nbbit_div+4-1 DOWNTO 0);
 
 
SIGNAL rec_encours : STD_LOGIC; -- A 1 pour indiquer qu'une trame est en cours d'analyse
SIGNAL crc : STD_LOGIC_VECTOR(15 downto 0); -- Valeur dynamique du crc
 
SIGNAL init_crc : STD_LOGIC; -- Initialise le calcul du CRC
 
 
 
 
TYPE layer2_rx_type IS (idle_st, rec_st, destuf_st, endnok_st, endok_st, newdat_st);
SIGNAL fsm_layer2_rx : layer2_rx_type;
 
-- Module de calcul du CRC16
COMPONENT crc16
GENERIC (
 
);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
data : IN std_logic_vector(7 downto 0);
val : IN std_logic;
init : IN std_logic;
crc : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
BEGIN
--------------------------------------------
 
--------------------------------------------
timer : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cpt_timer <= (others => '0');
timeout <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (val_in = '1') THEN
 
cpt_timer <= (others => '0');
timeout <= '0';
ELSE
 
 
IF (cpt_timer = (tc_divclk & "0000")) THEN
 
 
END IF;
END IF;
END IF;
END PROCESS;
 
--------------------------------------------
 
--------------------------------------------
 
man_fsm : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_layer2_rx <= idle_st;
init_crc <= '1';
val_crc <= '0';
val_out <= '0';
cpt_byt <= "00";
eof <= '0';
sof <= '0';
l2_ok <= '0';
adest_ok <= '0';
rec_encours <= '0';
dat_out_buf <= (others => '0');
 
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_layer2_rx IS
WHEN idle_st =>
 
init_crc <= '1';
val_crc <= '0';
val_out <= '0';
cpt_byt <= "00";
eof <= '0';
sof <= '0';
l2_ok <= '0';
adest_ok <= '0';
rec_encours <= '0';
fanion_recu <= '0';
fsm_layer2_rx <= rec_st;
WHEN rec_st =>
 
val_out <= '0'; -- On s'assure que les validants ne dure qu'1 pulse
sof <= '0';
val_crc <= '0';
init_crc <= '0';
IF (val_in = '1') THEN
 
IF (dat_in = x"7E") THEN
 
 
IF (rec_encours = '1') THEN
 
IF (crc(15 downto 0) = x"470F") THEN
 
fsm_layer2_rx <= endok_st;
ELSE
-- Sinon on annule la trame
fsm_layer2_rx <= endnok_st;
END IF;
 
END IF;
ELSIF (fanion_recu = '1') THEN
 
rec_encours <= '1'; -- On est au milieu d'une trame
IF (dat_in = x"7D") THEN
-- Si c'est un mot de bourage, on va attendre le mot suivant
fsm_layer2_rx <= destuf_st;
ELSE
 
 
fsm_layer2_rx <= newdat_st;
END IF;
END IF;
ELSIF (timeout = '1') THEN
 
IF (rec_encours = '1') THEN
 
fsm_layer2_rx <= endnok_st; -- On va traiter une erreur
ELSIF (fanion_recu = '1') THEN
 
 
END IF;
 
END IF;
WHEN newdat_st =>
 
IF (timeout = '1') THEN
 
fsm_layer2_rx <= endnok_st;
ELSE
fsm_layer2_rx <= rec_st; -- Quand on aura fini de traiter on ira attendre le mot suivant
 
 
 
 
 
END IF;
IF (cpt_byt /= "10") THEN
-- On ne compte que les 2 premiers octets
cpt_byt <= cpt_byt + 1;
END IF;
IF (cpt_byt = "00") THEN -- Le premier octet indique l'adresse de destination de la trame
IF ((dat_out_buf = ad_mio) OR (dat_out_buf = x"90") OR (dat_out_buf = x"FF")) THEN
 
adest_ok <= '1';
ELSE
adest_ok <= '0';
END IF;
END IF;
END IF;
 
WHEN destuf_st =>
 
IF (timeout = '1') THEN
fsm_layer2_rx <= endnok_st;
ELSE
IF (val_in = '1') THEN
 
IF (dat_in = x"5E") THEN
-- Si l'octet de stfuffing est 5E
 
fsm_layer2_rx <= newdat_st; -- On va la traiter
ELSIF (dat_in = x"5D") THEN
-- Si l'octet de stfuffing est 5E
 
fsm_layer2_rx <= newdat_st; -- On va la traiter
ELSE
-- Si le stuffing est ni 5E ni 5D, c'est un cas d'erreur
fsm_layer2_rx <= endnok_st;
END IF;
END IF;
END IF;
 
WHEN endnok_st =>
 
 
 
 
 
fanion_recu <= '0';
fsm_layer2_rx <= idle_st;
 
WHEN endok_st =>
 
 
 
l2_ok <= '1'; -- On indique que la trame est bonne
 
fanion_recu <= '0';
fsm_layer2_rx <= idle_st;
WHEN OTHERS =>
fsm_layer2_rx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
 
 
--------------------------------------------
-- Calcul du crc16
--------------------------------------------
inst_crc16: crc16
GENERIC MAP (
poly => x"1021" -- CCITT16
)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
data => dat_out_buf,
val => val_crc,
init => init_crc,
crc => crc
);
end rtl;
 
/tags/Release IPCommunication v1.0/layer2_tx.vhd
0,0 → 1,303
--=============================================================================
-- TITRE : LAYER2_TX
-- DESCRIPTION :
-- Encapsule la trame applicative dans une trame Layer2
 
-- et calcule le CRC
-- FICHIER : layer2_tx.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity layer2_tx is
PORT (
 
 
 
 
-- Interfaces vers le module d'interface du PIC
 
 
val_in : IN STD_LOGIC; -- validant du bus dat_in
 
 
 
 
-- Interfaces vers les FIFO de transmissions
 
val_out : OUT STD_LOGIC; -- Validant du bus dat_out
clr_fifo : IN STD_LOGIC; -- Signal de reset des FIFO Tx
progfull1: IN STD_LOGIC; -- Indique la FIFO Tx1 est presque pleine
progfull2: IN STD_LOGIC; -- Indique la FIFO Tx2 est presque pleine
full1 : IN STD_LOGIC; -- Indique la FIFO Tx1 est pleine
empty1 : IN STD_LOGIC; -- Indique la FIFO Tx1 est vide
full2 : IN STD_LOGIC; -- Indique la FIFO Tx2 est pleine
empty2 : IN STD_LOGIC -- Indique la FIFO Tx2 est vide
);
end layer2_tx;
 
architecture rtl of layer2_tx is
SIGNAL crc : STD_LOGIC_VECTOR(15 downto 0); -- Valeur dynamique du crc
SIGNAL val_crc : STD_LOGIC; -- Validant du CCRC
SIGNAL init_crc : STD_LOGIC; -- Initialise le calcul du CRC
 
 
SIGNAL empty1_r1, empty1_r2: STD_LOGIC; -- Pour changer empty1 d'horloge
SIGNAL empty2_r1, empty2_r2: STD_LOGIC; -- Pour changer empty2 d'horloge
 
TYPE layer2_tx_type IS (idle_st, addest_st, data_st, fifo_full_st, stuf5E_st, stuf5D_st,
waitcrc_st, crc1_st, stufcrc1_st, crc2_st, stufcrc2_st, fanionfin_st, waitendsend_st);
SIGNAL fsm_layer2_tx : layer2_tx_type;
 
-- Module de calcul du CRC16
COMPONENT crc16
GENERIC (
 
);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
data : IN std_logic_vector(7 downto 0);
val : IN std_logic;
init : IN std_logic;
crc : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
BEGIN
--------------------------------------------
 
 
-- En testant le prog_full, on a donc toujours au moins 15 octets de libre
 
 
-- le niveau de remplissage
--------------------------------------------
 
 
datin_free <= '1' WHEN (fsm_layer2_tx = data_st OR fsm_layer2_tx = addest_st) ELSE '0';
man_fsm : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_layer2_tx <= idle_st;
init_crc <= '1';
val_crc <= '0';
val_out <= '0';
last_char <= '0';
empty1_r1 <= '0';
empty1_r2 <= '0';
empty2_r1 <= '0';
empty2_r2 <= '0';
dat_out <= (others => '0');
dat_crc <= (others => '0');
 
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
empty1_r1 <= empty1; -- Changement d'horloge de empty1
empty1_r2 <= empty1_r1;
empty2_r1 <= empty2; -- Changement d'horloge de empty2
empty2_r2 <= empty2_r1;
CASE fsm_layer2_tx IS
WHEN idle_st =>
-- Etat d'attente du signal sof
IF (sof = '1' AND full1 = '0' AND full2 = '0' AND clr_fifo = '0') THEN
 
 
-- le relachement du clr_fifo
 
init_crc <= '0'; -- On annule le reset du CRC
val_crc <= '0'; -- L'octet qu'on va sortir ne compte pas dans le calcul du crc
 
 
ELSE
 
init_crc <= '1'; -- On initialise le CRC
val_crc <= '0'; -- On fait rien
val_out <= '0';
END IF;
WHEN addest_st =>
IF (val_in = '1') THEN
 
 
val_crc <= '1'; -- Elle compte dans le calcul du CRC
 
dat_crc <= dat_in; -- On la forunit au CRC
fsm_layer2_tx <= data_st; -- On va traiter l'octet suivant
ELSE
 
val_out <= '0'; -- Rien dans le FIFO
 
END IF;
WHEN data_st =>
 
IF (val_in = '1') THEN
 
 
dat_crc <= dat_in;
 
IF (dat_in = x"7E") THEN
 
 
 
ELSIF (dat_in = x"7D") THEN
 
 
 
ELSE
 
dat_out <= dat_in; -- On la met dans le flux
 
 
ELSIF (progfull1 = '1' OR progfull2 = '1') THEN
 
fsm_layer2_tx <= fifo_full_st; -- On va attendre
END IF;
END IF;
ELSE
 
val_crc <= '0'; -- On fait rien
val_out <= '0';
END IF;
 
WHEN fifo_full_st =>
 
val_crc <= '0'; -- On fait rien
val_out <= '0';
IF (progfull1 = '0' AND progfull2 = '0') THEN
-- On attend que les 2 FIFO ne soient plus pleines
fsm_layer2_tx <= data_st;
END IF;
WHEN stuf5E_st =>
-- Etat d'insertion du char 5E dans le flux
dat_out <= x"5E";
 
 
 
fsm_layer2_tx <= crc1_st;
ELSE
fsm_layer2_tx <= data_st;
END IF;
 
WHEN stuf5D_st =>
-- Etat d'insertion du char 5D dans le flux
dat_out <= x"5D";
 
 
 
fsm_layer2_tx <= crc1_st;
ELSE
fsm_layer2_tx <= data_st;
END IF;
 
WHEN waitcrc_st =>
 
val_crc <= '0';
val_out <= '0';
fsm_layer2_tx <= crc1_st; -- On va traiter les 8 MSB du CRC
 
WHEN crc1_st =>
-- Etat de traitement des 8 MSB du CRC
val_crc <= '0'; -- On doit pas modifier le CRC
 
IF (crc(15 downto 8) = x"7E" OR crc(15 downto 8) = x"7D") THEN
 
 
fsm_layer2_tx <= stufcrc1_st; -- On va traiter le stuf
ELSE
 
dat_out <= crc(15 downto 8); -- On les met tel quel dans le flux
fsm_layer2_tx <= crc2_st; -- On va traiter les 8 LSB du CRC
END IF;
 
WHEN stufcrc1_st =>
-- Etat de gestion du stuffing des 8 MSB du CRC
val_crc <= '0';
val_out <= '1';
IF (crc(15 downto 8) = x"7E") THEN
 
dat_out <= x"5E"; -- On envoie le bon code
ELSE
dat_out <= x"5D";
END IF;
fsm_layer2_tx <= crc2_st; -- On va traiter les 8 LSB du CRC
 
WHEN crc2_st =>
-- Etat de traitement des 8 LSB du CRC
val_crc <= '0';
val_out <= '1';
IF (crc(7 downto 0) = x"7E" OR crc(7 downto 0) = x"7D") THEN
 
dat_out <= x"7D";
fsm_layer2_tx <= stufcrc2_st;
ELSE
 
dat_out <= crc(7 downto 0);
 
END IF;
 
WHEN stufcrc2_st =>
-- Etat de gestion du stuffing des 8 LSB du CRC
val_crc <= '0';
val_out <= '1';
IF (crc(7 downto 0) = x"7E") THEN
dat_out <= x"5E";
ELSE
dat_out <= x"5D";
END IF;
fsm_layer2_tx <= fanionfin_st;
 
WHEN fanionfin_st =>
-- On envoie le fanion de fin
dat_out <= x"7E";
val_crc <= '0';
init_crc <= '1';
val_out <= '1';
fsm_layer2_tx <= waitendsend_st; -- On va attendre la fin des transmission
WHEN waitendsend_st =>
 
-- reprendre la main sur le Tx
val_out <= '0';
IF (empty1_r2 = '1' AND empty2_r2 = '1') THEN
-- Si les 2 FIFO Tx sont vides
fsm_layer2_tx <= idle_st;
END IF;
 
WHEN OTHERS =>
fsm_layer2_tx <= idle_st;
END CASE;
END IF;
END PROCESS;
 
--------------------------------------------
-- Calcul du crc16
--------------------------------------------
inst_crc16: crc16
GENERIC MAP (
poly => x"1021" -- CCITT16
)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
 
val => val_crc,
init => init_crc,
crc => crc
);
end rtl;
 
/tags/Release IPCommunication v1.0/readmac.vhd
0,0 → 1,95
--=============================================================================
-- TITRE : READMAC
-- DESCRIPTION :
 
 
-- FICHIER : readmac.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
-- 17/11/14 DRA SATURN V1.1
-- Suppression d'un coup de shift pour garder les 57 bits utiles en LSB
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
 
ENTITY readmac IS
GENERIC (
 
sim_dna_value : STD_LOGIC_VECTOR(59 DOWNTO 0) := X"023456789ABCDEF");
PORT (
 
 
 
 
mac : OUT STD_LOGIC_VECTOR(63 downto 0);
 
);
END readmac;
 
ARCHITECTURE rtl of readmac is
SIGNAL cptbit : STD_LOGIC_VECTOR(5 downto 0); -- compteur de bit
 
SIGNAL gnd : STD_LOGIC; -- '0' logique
SIGNAL read : STD_LOGIC; -- Ordre de lecture du DNA
 
SIGNAL shift : STD_LOGIC; -- Signal de shift d'un bit du DNA
SIGNAL dout : STD_LOGIC; -- Bit sorti du DNA
BEGIN
gnd <= '0';
--------------------------------------------
 
--------------------------------------------
inst_cpt : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cptbit <= (OTHERS => '0');
read <= '1';
read_r <= '1';
mac_rdy <= '0';
ELSIF (clk_sys'EVENT AND clk_sys = '1') THEN
read <= '0';
 
IF (read_r = '0') THEN -- Quand la lecture est finie
IF (cptbit /= "111001") THEN -- On shifte 57 bits
 
shift <= '1'; -- On ordonne le shift au DNA
shifter <= shifter(55 DOWNTO 0) & dout; -- On prend un bit de plus
cptbit <= cptbit + 1;
ELSE
 
shift <= '0'; -- On annule le shift DNA
 
END IF;
END IF;
END IF;
END PROCESS;
mac <= "1111111" & shifter; -- DNA sur 57 bits et MAC sur 64
 
-- Instantiation de la ressource DNA du FPGA
dn_port_inst : DNA_PORT
GENERIC MAP (
sim_dna_value => TO_BITVECTOR(sim_dna_value)
)
port map (
dout => dout,
clk => clk_sys,
din => gnd,
read => read_r,
shift => shift
);
 
END rtl;
 
/tags/Release IPCommunication v1.0/rxtx_tb.vhd
0,0 → 1,124
--=============================================================================
-- TITRE : SWITCH
-- DESCRIPTION :
 
-- - Copie octet par octet du port Rx sur le port Tx
-- - Gestion du switch entre les sources Tx (recopie du port Rx sur Tx ou tranmission d'une trame)
 
 
-- FICHIER : switch2.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
-- 18/09/2014 DRA SATURN V1.1
 
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
 
ENTITY rxtx_tb IS
END rxtx_tb;
 
ARCHITECTURE rtl of rxtx_tb is
 
 
 
 
 
CONSTANT nbbit_div : INTEGER := 10; -- Nombre de bits pour coder le diviseur d'horloge
 
 
 
 
 
 
 
 
 
COMPONENT serial_tx
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
tc_divclk : IN std_logic_vector(nbbit_div-1 downto 0);
start_ser : IN std_logic;
tx_dat : IN std_logic_vector(7 downto 0);
tx : OUT std_logic;
ser_rdy : OUT std_logic
);
END COMPONENT;
 
 
COMPONENT serial_rx2
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
baud_lock : IN STD_LOGIC;
tc_divclk : IN std_logic_vector(nbbit_div-1 downto 0);
rx : IN std_logic;
tx : OUT std_logic;
busy : OUT STD_LOGIC;
val : OUT std_logic;
rx_dat : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
BEGIN
clk_sys1 <= NOT(clk_sys1) AFTER 3999 ps;
clk_sys2 <= NOT(clk_sys2) AFTER 4001 ps;
rst_n <= '0', '1' after 10 ns;
 
inst_serial_rx: serial_rx2
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys2,
rst_n => rst_n,
baud_lock => baud_lock,
tc_divclk => tc_divclk,
tx => OPEN,
rx => rx,
busy => rx_encours,
val => val,
rx_dat => rx_dat
);
inst_serial_tx: serial_tx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys1,
rst_n => rst_n,
tc_divclk => tc_divclk,
tx => rx,
ser_rdy => ser_rdy,
start_ser => start_ser,
tx_dat => datatx
);
start_ser <= ser_rdy;
process(clk_sys1)
begin
IF (rising_edge(clk_sys1)) THEN
IF (ser_rdy = '1') THEN
datatx <= datatx + 1;
END IF;
END IF;
end process;
 
END rtl;
 
/tags/Release IPCommunication v1.0/serial_rx.vhd
0,0 → 1,139
--=============================================================================
-- TITRE : serial_rx
-- DESCRIPTION :
 
 
 
--
 
 
 
-- FICHIER : serial_rx.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 29/02/2012 DRA CONCERTO V1.0
 
 
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
ENTITY serial_rx IS
GENERIC (
nbbit_div : INTEGER := 10); -- Nombre de bits pour coder le diviseur d'horloge
PORT (
 
 
 
 
 
 
 
 
 
 
 
 
 
);
END serial_rx;
 
ARCHITECTURE rtl of serial_rx is
 
 
SIGNAL front_des_rx_c : STD_LOGIC; -- Un pulse de clk_sys sur front descendant de rx
 
 
 
 
BEGIN
--------------------------------------------
 
--------------------------------------------
 
front_rx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
rx_r <= (OTHERS => '1');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx_r <= rx_r(0) & rx;
END IF;
END PROCESS;
 
sumrx <= CONV_STD_LOGIC_VECTOR(rx_r(0), 2) + CONV_STD_LOGIC_VECTOR(rx_r(1), 2) +
 
 
--------------------------------------------
 
 
--------------------------------------------
deser_shaper : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cptbit_rx <= (OTHERS => '0');
divclk_rx <= (OTHERS => '0');
rx_encours <= '0';
tx <= '1';
val <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rx_encours = '0') THEN
 
 
IF (front_des_rx_c = '1') THEN
 
cptbit_rx <= (OTHERS => '0');
 
 
divclk_rx <= ('0' & tc_divclk(tc_divclk'LEFT downto 1))+2;
rx_encours <= '1';
END IF;
tx <= '1';
ELSE
-- Si on est en train de recevoir un car
IF (divclk_rx = tc_divclk) THEN
-- Si on atteind le terminal count (TC) du diviseur d'horloge
divclk_rx <= (OTHERS => '0');
 
 
shifter_rx <= sumrx(1) & shifter_rx(7 downto 1); -- On garde le bit LSB first
IF (baud_lock = '0') THEN
 
tx <= '1'; -- On ne recopie rien
ELSE
 
END IF;
 
 
 
 
 
val <= '0'; -- On s'assure que le signal dure 1 pulse
END IF;
ELSE
 
val <= '0'; -- On s'assure que le signal dure 1 pulse
END IF;
END IF;
END IF;
END PROCESS;
 
busy <= rx_encours;
END rtl;
 
/tags/Release IPCommunication v1.0/serial_rx2.vhd
0,0 → 1,132
--=============================================================================
-- TITRE : serial_rx2
-- DESCRIPTION :
 
 
 
--
 
-- Si la somme est > tc_divclk/2, c'est un '1', sinon, c'est un '0'
-- FICHIER : serial_rx2.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY serial_rx2 IS
GENERIC (
nbbit_div : INTEGER := 10); -- Nombre de bits pour coder le diviseur d'horloge
PORT (
 
 
 
 
 
 
 
 
 
 
 
 
 
);
END serial_rx2;
 
ARCHITECTURE rtl of serial_rx2 is
 
 
 
 
 
 
 
BEGIN
--------------------------------------------
 
--------------------------------------------
front_rx : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
rx_r <= '1';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx_r <= rx;
END IF;
END PROCESS;
 
 
consol_bit <= '1' WHEN (('0' & sumrx) + rx) > ("00" & tc_divclk(nbbit_div-1 DOWNTO 1)) ELSE '0';
 
--------------------------------------------
 
 
--------------------------------------------
deser_shaper : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cptbit_rx <= (OTHERS => '0');
divclk_rx <= (OTHERS => '0');
rx_encours <= '0';
tx <= '1';
val <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (rx_encours = '0') THEN
 
 
IF (rx = '0' and rx_r = '1') THEN
 
cptbit_rx <= (OTHERS => '0'); -- On initialise le compteur de bits
 
 
 
divclk_rx <= (others => '0');
sumrx <= (others => '0'); -- On init la somme des sur-echantillonnages
 
END IF;
tx <= '1'; -- Idle de la ligne Tx
ELSE
-- Si on est en train de recevoir un car
IF (divclk_rx = tc_divclk) THEN
-- Si on atteind le terminal count (TC) du diviseur d'horloge
-- On va traiter un bit de plus
divclk_rx <= (OTHERS => '0'); -- re init du diviseur d'horloge
sumrx <= (others => '0'); -- re init de la somme
 
 
IF (baud_lock = '0') THEN
 
tx <= '1'; -- On ne recopie rien
ELSE
 
END IF;
 
 
 
ELSIF (cptbit_rx = "0000") AND (consol_bit = '1') THEN
-- Si on est au premier bit et que c'est pas un '0' (bit de START)
 
END IF;
ELSE
 
 
val <= '0'; -- On s'assure que le signal dure 1 pulse
END IF;
END IF;
END IF;
END PROCESS;
 
busy <= rx_encours;
END rtl;
 
/tags/Release IPCommunication v1.0/serial_tx.vhd
0,0 → 1,96
--=============================================================================
-- TITRE : serial_tx
-- DESCRIPTION :
 
 
 
-- FICHIER : serial_tx.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY serial_tx IS
GENERIC (
nbbit_div : INTEGER := 10); -- Nombre de bits pour coder le diviseur d'horloge
PORT (
 
 
 
 
 
 
 
 
 
 
 
);
END serial_tx;
 
ARCHITECTURE rtl of serial_tx is
 
 
 
 
BEGIN
 
--------------------------------------------
 
--------------------------------------------
ser : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
cptbit_tx <= (OTHERS => '0');
divclk_tx <= (OTHERS => '0');
ser_rdy_buf <= '1';
shifter_tx <= (OTHERS => '1');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
IF (ser_rdy_buf = '1') THEN
 
IF (start_ser = '1') THEN
 
 
 
cptbit_tx <= (OTHERS => '0'); -- On init le compteur de bit
divclk_tx <= (OTHERS => '0'); -- On init le diviseur d'horloge
END IF;
ELSE
 
IF (divclk_tx = tc_divclk) THEN
 
 
 
IF (cptbit_tx = "1001") THEN
-- Lorsqu'on a transmis les 10 bits
ser_rdy_buf <= '1'; -- On revient en disponible
ELSIF (cptbit_tx = "1000") THEN
 
 
-- ser_rdy soit synhcrone du dernier clk_sys du dernier bit
ELSE
 
divclk_tx <= (OTHERS => '0');
END IF;
ELSE
divclk_tx <= divclk_tx + 1;
END IF;
END IF;
END IF;
END PROCESS;
ser_rdy <= ser_rdy_buf;
tx <= shifter_tx(0);
 
END rtl;
 
/tags/Release IPCommunication v1.0/switch.vhd
0,0 → 1,291
--=============================================================================
-- TITRE : SWITCH
-- DESCRIPTION :
 
-- - Copie du port Rx sur le port Tx avec remise en forme du signal
-- - Gestion du switch entre les sources Tx
 
 
-- FICHIER : switch.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 29/02/2012 DRA CONCERTO V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
ENTITY switch IS
GENERIC (
nbbit_div : INTEGER := 10); -- Nombre de bits pour coder le diviseur d'horloge
PORT (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
-- Gestion de la recopie
 
copy_ena : IN STD_LOGIC -- Autorisation de recopie d'un port sur l'autre
);
END switch;
 
ARCHITECTURE rtl of switch is
 
 
 
 
 
 
 
 
 
 
 
 
SIGNAL cop_read_c : STD_LOGIC; -- Lit un car dans la FIFO de recopie
 
SIGNAL cop_empty : STD_LOGIC; -- FIFO de recopie vide
SIGNAL cop_clr : STD_LOGIC; -- Purge de la FIFO de recopie
 
SIGNAL tempo : STD_LOGIC_VECTOR(nbbit_div-1 downto 0); -- Tempo de 1 bit
 
TYPE switch_state IS (idle_st, txreq_st, wait1bit_st, txproc_st, copproc_st);
SIGNAL fsm_switch : switch_state;
-- Composant de serialisation
COMPONENT serial_tx
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
tc_divclk : IN std_logic_vector(nbbit_div-1 downto 0);
start_ser : IN std_logic;
tx_dat : IN std_logic_vector(7 downto 0);
tx : OUT std_logic;
ser_rdy : OUT std_logic
);
END COMPONENT;
 
 
COMPONENT serial_rx
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
baud_lock : IN STD_LOGIC;
tc_divclk : IN std_logic_vector(nbbit_div-1 downto 0);
rx : IN std_logic;
tx : OUT std_logic;
busy : OUT STD_LOGIC;
val : OUT std_logic;
rx_dat : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
-- La FIFO est en FWFT
COMPONENT fifo_copy
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--------------------------------------------
 
 
--------------------------------------------
inst_serial_rx: serial_rx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_lock,
tc_divclk => tc_divclk,
tx => tx_copy,
rx => rx,
busy => rx_encours,
val => rx_wr_buf,
rx_dat => data_deser
);
rx_dat <= data_deser;
rx_val <= rx_wr_buf;
--------------------------------------------
 
--------------------------------------------
inst_serial_tx: serial_tx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
tx => tx_ser,
ser_rdy => ser_rdy,
start_ser => start_ser_c,
tx_dat => datatx_mux_c
);
 
--------------------------------------------
 
-- Soit on recopie le rx
 
 
--------------------------------------------
 
-- copy_ena) dans la FIFO de recopie
req_cop_c <= NOT(cop_empty) OR ((rx_encours OR rx_wr_buf) AND copy_ena);
man_fsm : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_switch <= idle_st;
sel_ser <= '0';
sel_par <= '1';
cop_clr <= '1';
tempo <= (OTHERS => '0');
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
CASE fsm_switch IS
WHEN idle_st =>
 
 
 
END IF;
sel_par <= '1';
 
IF (tx_empty = '0') THEN
 
fsm_switch <= txreq_st;
END IF;
WHEN txreq_st =>
-- Etat d'attente que les conditions soient favorables pour changer la source du tx
IF ((sw_ena = '1' AND rx_encours = '0') OR
(copy_ena = '0')) THEN
-- Si la recopie est interdite, on change quand on veut
 
 
 
cop_clr <= not(copy_ena); -- Si la recopie est interdite on purge la FIFO de recopie
tempo <= (OTHERS => '0');
fsm_switch <= wait1bit_st;
END IF;
 
WHEN wait1bit_st =>
 
IF (tempo = tc_divclk) THEN
fsm_switch <= txproc_st;
ELSE
tempo <= tempo + 1;
END IF;
WHEN txproc_st =>
 
IF ((tx_empty = '1') AND (req_cop_c = '1')) THEN
 
 
 
cop_clr <= not(copy_ena);
fsm_switch <= copproc_st;
ELSIF ((tx_empty = '1') AND (ser_rdy = '1') AND (req_cop_c = '0')) THEN
 
 
sel_par <= '1';
cop_clr <= '1';
fsm_switch <= idle_st;
END IF;
WHEN copproc_st =>
 
IF ((tx_empty = '0') AND (req_cop_c = '0')) THEN
 
 
 
cop_clr <= not(copy_ena);
fsm_switch <= txproc_st;
ELSIF ((tx_empty = '1') AND (ser_rdy = '1') AND (req_cop_c = '0') AND
(sw_ena = '1' OR copy_ena = '0')) THEN
 
-- et que soit on est pas au milieu d'une trame (sw_ena = 1) ou bien que la copy n'est pas
 
 
sel_par <= '1';
cop_clr <= '1';
fsm_switch <= idle_st;
END IF;
WHEN OTHERS =>
fsm_switch <= idle_st;
END CASE;
END IF;
END PROCESS;
 
cop_read_c <= ser_rdy AND NOT(cop_empty) WHEN (fsm_switch = copproc_st) ELSE '0';
 
tx_read_c <= ser_rdy AND NOT(tx_empty) WHEN (fsm_switch = txproc_st) ELSE '0';
tx_rd <= tx_read_c;
 
start_ser_c <= cop_read_c OR tx_read_c;
 
datatx_mux_c <= tx_dat WHEN (sel_par = '0') ELSE fifocopy_dout;
 
 
tx <= tx_ser WHEN (sel_ser = '0') ELSE tx_copy;
inst_fifo_copy : fifo_copy
PORT MAP (
clk => clk_sys,
srst => cop_clr,
din => data_deser,
wr_en => rx_wr_buf,
rd_en => cop_read_c,
dout => fifocopy_dout,
full => OPEN,
overflow => OPEN,
empty => cop_empty
);
END rtl;
 
/tags/Release IPCommunication v1.0/switch2.vhd
0,0 → 1,235
--=============================================================================
-- TITRE : SWITCH
-- DESCRIPTION :
 
-- - Copie octet par octet du port Rx sur le port Tx
-- - Gestion du switch entre les sources Tx (recopie du port Rx sur Tx ou tranmission d'une trame)
 
 
-- FICHIER : switch2.vhd
--=============================================================================
-- CREATION
-- DATE AUTEUR PROJET REVISION
-- 10/04/2014 DRA SATURN V1.0
--=============================================================================
-- HISTORIQUE DES MODIFICATIONS :
-- DATE AUTEUR PROJET REVISION
-- 18/09/2014 DRA SATURN V1.1
 
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
 
ENTITY switch IS
GENERIC (
nbbit_div : INTEGER := 10); -- Nombre de bits pour coder le diviseur d'horloge
PORT (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
-- Gestion de la recopie
sw_ena : IN STD_LOGIC; -- A '1' entre 2 trames sur le port Rx (RFU)
copy_ena : IN STD_LOGIC; -- Autorisation de recopie du Rx sur Tx;
etat : OUT STD_LOGIC
);
END switch;
 
ARCHITECTURE rtl of switch is
 
 
 
 
 
 
 
 
 
SIGNAL cop_read_c : STD_LOGIC; -- Lit un car dans la FIFO de recopie
 
SIGNAL cop_empty : STD_LOGIC; -- FIFO de recopie vide
SIGNAL cop_clr : STD_LOGIC; -- Purge de la FIFO de recopie
 
SIGNAL rx_wr_buf_r : STD_LOGIC;
SIGNAL rx_wr_buf_rr : STD_LOGIC;
 
TYPE switch_state IS (copproc_st, txproc_st);
SIGNAL fsm_switch : switch_state;
-- Composant de serialisation
COMPONENT serial_tx
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
tc_divclk : IN std_logic_vector(nbbit_div-1 downto 0);
start_ser : IN std_logic;
tx_dat : IN std_logic_vector(7 downto 0);
tx : OUT std_logic;
ser_rdy : OUT std_logic
);
END COMPONENT;
 
 
COMPONENT serial_rx2
GENERIC (
nbbit_div : INTEGER := 10);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
baud_lock : IN STD_LOGIC;
tc_divclk : IN std_logic_vector(nbbit_div-1 downto 0);
rx : IN std_logic;
tx : OUT std_logic;
busy : OUT STD_LOGIC;
val : OUT std_logic;
rx_dat : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
-- La FIFO est en FWFT
COMPONENT fifo_copy
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
etat <= '0' when (fsm_switch = copproc_st) else '1';
--------------------------------------------
 
--------------------------------------------
inst_serial_rx: serial_rx2
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
baud_lock => baud_lock,
tc_divclk => tc_divclk,
tx => OPEN,
rx => rx,
busy => rx_encours,
val => rx_wr_buf,
rx_dat => data_deser
);
rx_dat <= data_deser;
rx_val <= rx_wr_buf;
--------------------------------------------
 
--------------------------------------------
inst_serial_tx: serial_tx
GENERIC MAP (
nbbit_div => nbbit_div)
PORT MAP(
clk_sys => clk_sys,
rst_n => rst_n,
tc_divclk => tc_divclk,
tx => tx,
ser_rdy => ser_rdy,
start_ser => start_ser_c,
tx_dat => datatx_mux_c
);
 
--------------------------------------------
 
 
 
--------------------------------------------
 
-- copy_ena) dans la FIFO de recopie
req_cop_c <= NOT(cop_empty) OR ((rx_encours OR rx_wr_buf OR rx_wr_buf_r OR rx_wr_buf_rr) AND copy_ena);
 
cop_clr <= NOT(baud_lock); --NOT(copy_ena) OR NOT(baud_lock);
 
cop_read_c <= ser_rdy AND NOT(cop_empty) WHEN (fsm_switch = copproc_st) ELSE '0';
 
tx_read_c <= ser_rdy AND NOT(tx_empty) WHEN (fsm_switch = txproc_st) ELSE '0';
tx_rd <= tx_read_c; -- Signal de lecture de la FIFO externe
 
start_ser_c <= cop_read_c OR tx_read_c;
 
datatx_mux_c <= tx_dat WHEN (sel_par = '0') ELSE fifocopy_dout;
man_fsm : PROCESS(clk_sys, rst_n)
BEGIN
IF (rst_n = '0') THEN
fsm_switch <= copproc_st;
sel_par <= '1';
rx_wr_buf_r <= '0';
rx_wr_buf_rr <= '0';
ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
rx_wr_buf_r <= rx_wr_buf;
rx_wr_buf_rr <= rx_wr_buf_r;
CASE fsm_switch IS
WHEN copproc_st =>
 
IF ((tx_empty = '0') AND (req_cop_c = '0') AND (ser_rdy = '1') AND (sw_ena = '1')) THEN
 
 
-- octet est fini d'envoyer (ser_rdy = 1)
 
 
END IF;
 
WHEN txproc_st =>
 
IF (tx_empty = '1') THEN
 
 
 
END IF;
WHEN OTHERS =>
fsm_switch <= copproc_st;
END CASE;
END IF;
END PROCESS;
 
inst_fifo_copy : fifo_copy
PORT MAP (
clk => clk_sys,
srst => cop_clr,
din => data_deser,
wr_en => fifo_cop_wren,
rd_en => cop_read_c,
dout => fifocopy_dout,
full => OPEN,
overflow => OPEN,
empty => cop_empty
);
END rtl;
 
/tags/Release IPCommunication v1.0/test_spi.vhd
0,0 → 1,228
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:40:33 12/03/2012
-- Design Name:
-- Module Name: R:/CONCERTO/LP/IP Communication/test_spi.vhd
-- Project Name: fpga_mio10s
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: if_spi
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_spi IS
END test_spi;
ARCHITECTURE behavior OF test_spi IS
CONSTANT adreg_loadfpga: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(124, 7);
CONSTANT adreg_spinbr: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(125, 7);
CONSTANT adreg_spictl: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(126, 7);
CONSTANT adreg_spidat: STD_LOGIC_VECTOR(6 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(127, 7);
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT if_spi
GENERIC (
 
spiclk_freq : INTEGER := 12
);
PORT(
clk_sys : IN std_logic;
rst_n : IN std_logic;
spi_csn : OUT std_logic;
spi_wpn : OUT std_logic;
spi_sdo : OUT std_logic;
spi_sdi : IN std_logic;
spi_clk : OUT std_logic;
tx_dat : IN std_logic_vector(7 downto 0);
tx_val : IN std_logic;
rx_dat : OUT std_logic_vector(7 downto 0);
rx_val : OUT std_logic;
rx_next : IN std_logic;
type_com : IN std_logic;
exec_com : IN std_logic;
spi_busy : OUT std_logic;
nb_read : IN std_logic_vector(7 downto 0)
);
END COMPONENT;
 
COMPONENT m25p80
PORT (
c : IN std_logic;
data_in : IN std_logic;
s : IN std_logic;
w : IN std_logic;
hold : IN std_logic;
data_out : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal clk_sys : std_logic := '0';
signal rst_n : std_logic := '0';
signal spi_sdi : std_logic := '0';
signal tx_dat : std_logic_vector(7 downto 0) := (others => '0');
signal tx_val : std_logic := '0';
signal rx_next : std_logic := '0';
signal type_com : std_logic := '0';
signal exec_com : std_logic := '0';
signal nb_read : std_logic_vector(7 downto 0) := (others => '0');
 
--Outputs
signal spi_csn : std_logic;
signal spi_wpn : std_logic;
signal spi_sdo : std_logic;
signal spi_clk : std_logic;
signal rx_dat : std_logic_vector(7 downto 0);
signal rx_val : std_logic;
signal spi_busy : std_logic;
 
-- Clock period definitions
constant clk_sys_period : time := 22 ns;
BEGIN
rst_n <= '0', '1' after 10 ns;
-- Instantiate the Unit Under Test (UUT)
uut: if_spi
GENERIC MAP (
div_rate => 2,
spiclk_freq => 12)
PORT MAP (
clk_sys => clk_sys,
rst_n => rst_n,
spi_csn => spi_csn,
spi_wpn => spi_wpn,
spi_sdo => spi_sdo,
spi_sdi => spi_sdi,
spi_clk => spi_clk,
tx_dat => tx_dat,
tx_val => tx_val,
rx_dat => rx_dat,
rx_val => rx_val,
rx_next => rx_next,
type_com => type_com,
exec_com => exec_com,
spi_busy => spi_busy,
nb_read => nb_read
);
 
instflash : m25p80
PORT MAP(
c => spi_clk,
data_in => spi_sdo,
s => spi_csn,
w => spi_wpn,
hold => '1',
data_out => spi_sdi
);
 
-- Clock process definitions
clk_sys_process :process
begin
clk_sys <= '0';
wait for clk_sys_period/2;
clk_sys <= '1';
wait for clk_sys_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
-- Commande 06h (WREN)
wait until rising_edge(clk_sys);
tx_dat <= x"06";
tx_val <= '1';
wait until rising_edge(clk_sys);
tx_val <= '0';
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
type_com <= '0';
exec_com <= '1';
wait until spi_busy = '0';
 
-- Commande D8h (SE)
wait until rising_edge(clk_sys);
tx_dat <= x"D8";
nb_read <= x"14";
tx_val <= '1';
wait until rising_edge(clk_sys);
tx_dat <= x"01";
wait until rising_edge(clk_sys);
tx_dat <= x"02";
wait until rising_edge(clk_sys);
tx_dat <= x"03";
wait until rising_edge(clk_sys);
tx_val <= '0';
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
type_com <= '0';
exec_com <= '1';
wait until spi_busy = '0';
 
-- Commande 06h (WREN)
wait until rising_edge(clk_sys);
tx_dat <= x"06";
tx_val <= '1';
wait until rising_edge(clk_sys);
tx_val <= '0';
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
type_com <= '0';
exec_com <= '1';
wait until spi_busy = '0';
 
-- Commande PP
wait until rising_edge(clk_sys);
tx_dat <= x"02";
tx_val <= '1';
wait until rising_edge(clk_sys);
tx_dat <= x"01";
wait until rising_edge(clk_sys);
tx_dat <= x"02";
wait until rising_edge(clk_sys);
tx_dat <= x"03";
FOR i IN 0 TO 124 LOOP
wait until rising_edge(clk_sys);
tx_dat <= conv_std_logic_vector(i, 8);
END LOOP;
wait until rising_edge(clk_sys);
tx_val <= '0';
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
type_com <= '0';
exec_com <= '1';
wait until spi_busy = '0';
wait;
end process;
 
END;

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