URL
https://opencores.org/ocsvn/sd_card_controller/sd_card_controller/trunk
Subversion Repositories sd_card_controller
Compare Revisions
- This comparison shows the changes necessary to convert path
/sd_card_controller/trunk/bench
- from Rev 3 to Rev 8
- ↔ Reverse comparison
Rev 3 → Rev 8
/verilog/monostable_domain_cross_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for monostable_domain_cross module //// |
/verilog/sd_cmd_master_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for sd_cmd_master module //// |
/verilog/sd_fifo_filler_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for sd_fifo_filler module //// |
/verilog/sd_data_xfer_trig_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for sd_data_xfer_trig module //// |
/verilog/sd_data_master_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for sd_data_master module //// |
/verilog/bistable_domain_cross_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for bistable_domain_cross module //// |
/verilog/sd_cmd_serial_host_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for sd_cmd_serial_host module //// |
/verilog/sd_data_serial_host_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for sd_data_serial_host module //// |
/verilog/edge_detect_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for edge_detect module //// |
/verilog/sd_controller_wb_tb.sv
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// testbench for sd_controller_wb module //// |