URL
https://opencores.org/ocsvn/sd_card_controller/sd_card_controller/trunk
Subversion Repositories sd_card_controller
Compare Revisions
- This comparison shows the changes necessary to convert path
/sd_card_controller/trunk/rtl
- from Rev 6 to Rev 8
- ↔ Reverse comparison
Rev 6 → Rev 8
/verilog/sdc_controller.v
6,15 → 6,15
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Top level entity. //// |
//// This core is based on SD Card IP core project from //// |
//// This core is based on the "sd card controller" project from //// |
//// http://opencores.org/project,sdcard_mass_storage_controller //// |
//// and is a major rewrite of original work. Effort was put to //// |
//// make the core more generic and be able to be used with //// |
//// OS's like Linux. //// |
//// but has been largely rewritten. A lot of effort has been //// |
//// made to make the core more generic and easily usable //// |
//// with OSs like Linux. //// |
//// - data transfer commands are not fixed //// |
//// - data transfer block size is configurable //// |
//// - multiple block transfer support //// |
/verilog/bistable_domain_cross.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Clock synchronisation beetween two clock domains. //// |
/verilog/sd_cmd_serial_host.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Module resposible for sending and receiving commands //// |
/verilog/sd_defines.h
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Header file with common definitions //// |
/verilog/sd_clock_divider.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Control of sd card clock rate //// |
/verilog/sd_data_serial_host.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Module resposible for sending and receiving data through //// |
/verilog/edge_detect.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Signal edge detection. If input signal transitions between //// |
/verilog/sd_controller_wb.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Wishbone interface responsible for comunication with core //// |
/verilog/monostable_domain_cross.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Clock synchronisation beetween two clock domains. //// |
/verilog/sd_cmd_master.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// State machine resposible for controlling command transfers //// |
/verilog/sd_fifo_filler.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Fifo interface between sd card and wishbone clock domains //// |
/verilog/sd_data_xfer_trig.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// Module resposible for triggering data transfer based on //// |
/verilog/sd_data_master.v
6,7 → 6,7
//// //// |
//// This file is part of the WISHBONE SD Card //// |
//// Controller IP Core project //// |
//// http://www.opencores.org/cores/xxx/ //// |
//// http://opencores.org/project,sd_card_controller //// |
//// //// |
//// Description //// |
//// State machine resposible for controlling data transfers //// |