URL
https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk
Subversion Repositories sdcard_mass_storage_controller
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdcard_mass_storage_controller/trunk/bench
- from Rev 98 to Rev 102
- ↔ Reverse comparison
Rev 98 → Rev 102
/sdc_dma/verilog/SD_controller_top_tb.v
221,7 → 221,7
.CYC_I(wbm_sdm_cyc_o), |
.DAT_O(wbm_sdm_dat_i), |
.DAT_I(wbm_sdm_dat_o), |
.ERR_O(wbm_sdm_dat_o), |
.ERR_O(), |
.RTY_O(), // NOT USED for now! |
.SEL_I(wbm_sdm_sel_o), |
.STB_I(wbm_sdm_stb_o), |
276,8 → 276,8
.ACK_I(wbm_sdm_ack_i), |
.ADDR_O(wbm_sdm_adr_o), |
.CYC_O(wbm_sdm_cyc_o), |
.DAT_I(wbm_sdm_dat_o), |
.DAT_O(wbm_sdm_dat_i), |
.DAT_I(wbm_sdm_dat_i), |
.DAT_O(wbm_sdm_dat_o), |
.ERR_I(0), |
.RTY_I(1'b0), |
.SEL_O(wbm_sdm_sel_o), |
815,7 → 815,10
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); |
|
|
addr = `SD_BASE + `BD_ISR ; |
addr = `SD_BASE + `BD_ISR ; |
data=0; |
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); |
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits); |
|
while ( resp_data[0] !=1 ) begin |
/sdc_dma/verilog/sdModel.v
58,7 → 58,7
reg [120:0] CID; |
reg Busy; //0 when busy |
wire [6:0] crcOut; |
reg [3:0] crc_c; |
reg [4:0] crc_c; |
|
reg [3:0] CurrentState; |
reg [3:0] DataCurrentState; |
672,10 → 672,10
|
end |
else begin |
crcDat_en<=0; |
crcDat_rst<=1; |
oeDat<=1; |
crc_c<=15; |
crcDat_en<=0; |
crcDat_rst<=1; |
oeDat<=1; |
crc_c<=16; |
end |
|
if (transf_cnt==1) begin |
686,7 → 686,7
data_send_index<=1; |
end |
else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin |
data_send_index=~data_send_index; |
data_send_index<=~data_send_index; |
if (!data_send_index) begin |
last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4]; |
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4]; |
706,12 → 706,15
|
end |
else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin |
datOut<= last_din; |
crcDat_en<=0; |
crc_c<=crc_c-1; |
crc_c<=crc_c-1; |
if (crc_c<= 16) begin |
datOut[0]<=crcDat_out[0][crc_c-1]; |
datOut[1]<=crcDat_out[1][crc_c-1]; |
datOut[2]<=crcDat_out[2][crc_c-1]; |
datOut[3]<=crcDat_out[3][crc_c-1]; |
datOut[3]<=crcDat_out[3][crc_c-1]; |
end |
end |
else if (transf_cnt==`BIT_BLOCK-2) begin |
datOut<=4'b1111; |