OpenCores
URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

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    /sdcard_mass_storage_controller/trunk/bench
    from Rev 97 to Rev 98
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  •

Rev 97 → Rev 98

/sdc_dma/verilog/wb_slave_behavioral.v
102,6 → 102,16
reg `WB_DATA_TYPE mem_wr_data_out;
reg `WB_DATA_TYPE mem_rd_data_in;
 
initial $readmemh("wb_memory.txt",wb_memory);
 
integer k;
initial begin
$display("Contents of Mem after reading data file:");
for (k=0; k<10; k=k+1) $display("%d:%h",k,wb_memory[k]);
end
 
 
 
/*------------------------------------------------------------------------------------------------------
Maximum values for WAIT and RETRY counters and which response !!!
------------------------------------------------------------------------------------------------------*/
114,7 → 124,7
begin
if (RST_I)
begin
a_e_r_resp <= 3'b000; // do not respond
a_e_r_resp <= 3'b100; // do not respond
wait_cyc <= 4'b0; // no wait cycles
max_retry <= 8'h0; // no retries
end
/sdc_dma/verilog/SD_controller_top_tb.v
360,7 → 360,7
#423 wb_rst = 1'b0;
 
// Clear memories
clear_memories;
//clear_memories;
 
#423 StartTB = 1'b1;
end
431,12 → 431,18
$display("T2 test_init_sequence Completed");
$display("===========================================================================");
test_send_data(0, 1);
// test_send_data(0, 1);
$display("");
$display("===========================================================================");
$display("T3 test_send_data Completed");
$display("===========================================================================");
// test_send_rec_data
test_send_rec_data(0, 1);
$display("");
$display("===========================================================================");
$display("T4 test_send_rec_data Completed");
$display("===========================================================================");
end
444,6 → 450,417
//TEST Cases
//
//
//
 
task test_send_rec_data;
input [31:0] start_task;
input [31:0] end_task;
integer bit_start_1;
integer bit_end_1;
integer bit_start_2;
integer bit_end_2;
integer num_of_reg;
integer i_addr;
integer i_data;
integer i_length;
integer tmp_data;
integer resp_data;
reg [31:0] tx_bd_num;
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
integer i;
integer i1;
integer i2;
integer i3;
integer fail;
integer test_num;
reg [31:0] addr;
reg [31:0] data;
reg [3:0] sel;
reg [3:0] rand_sel;
reg [31:0] data_max;
reg [31:0] rsp;
begin
// access_to_reg
test_heading("access_to_reg");
$display(" ");
$display("access_to_reg TEST");
fail = 0;
resp_data = 0;
// reset MAC registers
hard_reset;
 
 
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
begin
//////////////////////////////////////////////////////////////////////
//// ////
//Test 3.0: Init sequence, With response check
//CMD 0. Reset Card
//CMD 8. Get voltage (Only 2.0 Card response to this) ////
//CMD55. Indicate Next Command are Application specific
//ACMD44. Get Voltage windows
//CMD2. CID reg
//CMD3. Get RCA.
//////////////////////////////////////////////////////////////////////
if (test_num == 0) //
begin
 
test_name = "4.0: Send data ";
`TIME; $display(" TEST 4.0: Send data ");
wbm_init_waits = 0;
wbm_subseq_waits = {$random} % 5;
data = 0;
rand_sel = 0;
sel = 4'hF;
//Reset Core
addr = `SD_BASE + `software ;
data = 1;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Setup timeout reg
addr = `SD_BASE + `timeout ;
data = 16'h2ff;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Clock divider /2
addr = `SD_BASE + `clock_d ;
data = 16'h0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Start Core
addr = `SD_BASE + `software ;
data = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//CMD 0 Reset card
//Setup settings
addr = `SD_BASE + `command ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for send finnish
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1)
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
fail = fail + 1;
test_fail_num("Error occured when sending CMD0 in TEST4.0", i_addr);
`TIME;
$display("Normal status register is not 0x1: %h", tmp_data);
end
//CMD 8. Get voltage (Only 2.0 Card response to this)
addr = `SD_BASE + `command ;
data = `CMD8 | `RSP_48 ;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for send finnish or timeout
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 8, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
tmp_data=1;
end
end
resp_data[31]=1; //Just to make it to not skip first
while (resp_data[31]) begin //Wait until busy is clear in the card
//Send CMD 55
addr = `SD_BASE + `command ;
data = `CMD55 |`CICE | `CRCE | `RSP_48 ;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
addr = `SD_BASE + `error_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
test_fail_num("Error occured when sending CMD55 in TEST 4.0", i_addr);
`TIME;
$display("Error in TEST 4.0 status reg: %h", tmp_data);
end
end
//Send ACMD 41
addr = `SD_BASE + `command ;
data = `ACMD41 | `RSP_48 ;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
addr = `SD_BASE + `error_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
test_fail_num("Error occured when sending ACMD 41 in TEST 4.0", i_addr);
`TIME;
$display("Error in TEST 4.0 status reg: %h", tmp_data);
end
//Read response data
end
addr = `SD_BASE + `resp1 ;
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
end
//Send CMD 2
addr = `SD_BASE + `command ;
data = `CMD2 | `CRCE | `RSP_136 ; //CMD index 2, CRC and Index Check, rsp = 136 bit;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
addr = `SD_BASE + `error_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
test_fail_num("Error occured when sending CMD2 in TEST 4.0", i_addr);
`TIME;
$display("CMD2 Error in TEST 4.0 status reg: %h", tmp_data);
end
end
addr = `SD_BASE + `resp1 ;
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
$display("CID reg 1: %h", resp_data);
//Send CMD 3
addr = `SD_BASE + `command ;
data = `CMD3 | `CRCE | `CRCE | `RSP_48 ; //CMD index 3, CRC and Index Check, rsp = 48 bit;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
addr = `SD_BASE + `error_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
test_fail_num("Error occured when sending CMD2 in TEST 4.0", i_addr);
`TIME;
$display("CMD3 Error in TEST 4.0 status reg: %h", tmp_data);
end
end
addr = `SD_BASE + `resp1 ;
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
card_rca= resp_data [31:16];
$display("RCA Response: %h", resp_data);
$display("RCA Nr for data transfer: %h", card_rca);
//Put in transferstate
//Send CMD 7
addr = `SD_BASE + `command ;
data = `CMD7 | `CRCE | `CRCE | `RSP_48 ; //CMD index 3, CRC and Index Check, rsp = 48 bit;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data[31:16] = card_rca; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
addr = `SD_BASE + `error_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
test_fail_num("Error occured when sending CMD7 in TEST 4.0", i_addr);
`TIME;
$display("CMD7 Error in TEST 4.0 status reg: %h", tmp_data);
end
end
//Set bus width
//Send CMD 55
addr = `SD_BASE + `command ;
data = `CMD55 |`CICE | `CRCE | `RSP_48 ;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
addr = `SD_BASE + `error_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
test_fail_num("Error occured when sending CMD55 in TEST 4.0", i_addr);
`TIME;
$display("Error in TEST 4.0 status reg: %h", tmp_data);
end
end
//Send ACMD 6
addr = `SD_BASE + `command ;
data = `ACMD6 |`CICE | `CRCE | `RSP_48 ;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//Argument settings
addr = `SD_BASE + `argument ;
data = 2; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
addr = `SD_BASE + `error_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
test_fail_num("Error occured when sending ACMD 6 in TEST 4.0", i_addr);
`TIME;
$display("Error in TEST 4.0 status reg: %h", tmp_data);
end
//Read response data
end
addr = `SD_BASE + `resp1 ;
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
$display("Card status after Bus width set %h", resp_data);
//write data
addr = `SD_BASE + `BD_TX ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
addr = `SD_BASE + `BD_TX ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
addr = `SD_BASE + `BD_ISR ;
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while ( resp_data[0] !=1 ) begin
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (resp_data[1] ) begin
test_fail_num("Error in TEST 4.0: Data resend try >N. BD_ISR %h", resp_data);
`TIME;
$display("Error in TEST 4.0: Data resend try >N. BD_ISR %h", resp_data);
end
else if (resp_data[2] ) begin
test_fail_num("Error in TEST 4.0: FIFO underflow/overflow. BD_ISR %h", resp_data);
`TIME;
$display("Error in TEST 4.0: FIFO underflow/overflow. BD_ISR %h", resp_data);
end
else if (resp_data[4] ) begin
test_fail_num("Error in TEST 4.0: Command error. BD_ISR %h", resp_data);
`TIME;
$display("Error in TEST 4.0: Command error. BD_ISR %h", resp_data);
end
else if (resp_data[5] ) begin
test_fail_num("Error in TEST 4.0: Data CRC error. BD_ISR %h", resp_data);
`TIME;
$display("Error in TEST 4.0: Data CRC error. BD_ISR %h", resp_data);
end
end
clear_memories;
 
addr = `SD_BASE + `BD_RX ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
addr = `SD_BASE + `BD_RX ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
addr = `SD_BASE + `BD_ISR ;
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while ( resp_data[0] !=1 ) begin
wbm_read(addr, resp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (resp_data[1] ) begin
test_fail_num("Error in TEST 4.0: Data resend try >N. BD_ISR %h", resp_data);
`TIME;
$display("Error in TEST 4.0: Data resend try >N. BD_ISR %h", resp_data);
end
else if (resp_data[2] ) begin
test_fail_num("Error in TEST 4.0: FIFO underflow/overflow. BD_ISR %h", resp_data);
`TIME;
$display("Error in TEST 4.0: FIFO underflow/overflow. BD_ISR %h", resp_data);
end
else if (resp_data[4] ) begin
test_fail_num("Error in TEST 4.0: Command error. BD_ISR %h", resp_data);
`TIME;
$display("Error in TEST 4.0: Command error. BD_ISR %h", resp_data);
end
else if (resp_data[5] ) begin
test_fail_num("Error in TEST 4.0: Data CRC error. BD_ISR %h", resp_data);
`TIME;
$display("Error in TEST 4.0: Data CRC error. BD_ISR %h", resp_data);
end
end
end
end
if(fail == 0)
test_ok;
else
fail = 0;
end
endtask
 
 
 
 
 
 
 
 
 
task test_send_data;
input [31:0] start_task;
input [31:0] end_task;
806,6 → 1223,7
fail = 0;
end
endtask
 
task test_init_sequnce; //
input [31:0] start_task;
input [31:0] end_task;
/sdc_dma/verilog/sdModel.v
5,6 → 5,7
`define tISU 6 //Input setup time
`define tIH 0 //Input hold time
`define tODL 14 //Output delay
`define DLY_TO_OUTP 47
 
`define BLOCKSIZE 512
`define MEMSIZE 2048 // 4 block
150,8 → 151,7
qCmd<=1;
oeDat<=0;
cmdOut<=0;
cmdWrite<=0;
cmdWrite<=0;
InbuffStatus<=0;
datOut<=0;
inCmd<=0;
177,13 → 177,13
transf_cnt<=0;
BlockAddr<=0;
block_cnt <=0;
wptr<=0;
transf_cnt<=0;
crcDat_rst<=1;
crcDat_en<=0;
crcDat_in<=0;
flash_write_cnt<=0;
flash_blockwrite_cnt<=0;
wptr<=0;
transf_cnt<=0;
crcDat_rst<=1;
crcDat_en<=0;
crcDat_in<=0;
flash_write_cnt<=0;
flash_blockwrite_cnt<=0;
end
 
//CARD logic
224,7 → 224,7
endcase
end
 
always @ (dataState or CardStatus or crc_c or flash_write_cnt or q_start_bit)
always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )
begin : FSM_COMBODAT
next_datastate = 0;
case(dataState)
238,7 → 238,7
end
READ_WAITS: begin
if (q_start_bit == 1'b0 )
if ( dat[0] == 1'b0 )
next_datastate = READ_DATA;
else
next_datastate = READ_WAITS;
255,9 → 255,13
next_datastate = DATA_IDLE;
else
next_datastate = WRITE_FLASH;
end
end
WRITE_DATA : begin
if (transf_cnt >= `BIT_BLOCK)
next_datastate= DATA_IDLE;
else
next_datastate=WRITE_DATA;
end
 
314,7 → 318,7
crcEn<=0;
crcRst<=1;
oeCmd<=0;
oeDat<=0;
cmdRead<=0;
appendCrc<=0;
ValidCmd<=0;
438,10 → 442,26
response_CMD[127:96] <= CardStatus ;
end
17 : response_CMD[127:96]<= 48;
17 : begin
if (outDelayCnt==0) begin
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
CardStatus[12:9] <=`DATAS;//Put card in data state
response_CMD[127:96] <= CardStatus ;
BlockAddr = inCmd[39:8];
if (BlockAddr%512 !=0)
$display("**Block Misalign Error");
end
else begin
response_S <= 0;
response_CMD[127:96] <= 0;
end
end
end
24 : begin
if (outDelayCnt==0) begin
if (CardStatus[12:9] == 4) begin //If card is in transferstate
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
if (CardStatus[8]) begin //If Free write buffer
CardStatus[12:9] <=`RCV;//Put card in Rcv state
response_CMD[127:96] <= CardStatus ;
545,11 → 565,21
endcase
end
 
 
 
integer outdly_cnt;
 
 
 
 
 
 
 
always @ (posedge sdClk) begin
case (dataState)
DATA_IDLE: begin
oeDat<=0;
end
READ_WAITS: begin
576,6 → 606,8
if (wptr)
block_cnt<=block_cnt+1;
wptr<=~wptr;
end
else if ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE-1)) begin
transf_cnt<=transf_cnt+1;
615,34 → 647,110
 
 
 
 
always @ (posedge sdClk) begin
reg data_send_index;
integer write_out_index;
always @ (negedge sdClk) begin
case (dataState)
IDLE: begin
DATA_IDLE: begin
write_out_index<=0;
transf_cnt<=0;
data_send_index<=0;
outdly_cnt<=0;
 
 
end
WRITE_DATA: begin
oeDat<=1;
outdly_cnt<=outdly_cnt+1;
if ( outdly_cnt > `DLY_TO_OUTP) begin
transf_cnt <= transf_cnt+1;
crcDat_en<=1;
crcDat_rst<=0;
end
else begin
crcDat_en<=0;
crcDat_rst<=1;
oeDat<=1;
crc_c<=15;
end
if (transf_cnt==1) begin
last_din <= FLASHmem[BlockAddr+(write_out_index)][7:4];
datOut<=0;
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
data_send_index<=1;
end
else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
data_send_index=~data_send_index;
if (!data_send_index) begin
last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
end
else begin
last_din<=FLASHmem[BlockAddr+(write_out_index)][3:0];
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][3:0];
write_out_index<=write_out_index+1;
end
datOut<= last_din;
if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
crcDat_en<=0;
end
end
else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
crcDat_en<=0;
crc_c<=crc_c-1;
datOut[0]<=crcDat_out[0][crc_c-1];
datOut[1]<=crcDat_out[1][crc_c-1];
datOut[2]<=crcDat_out[2][crc_c-1];
datOut[3]<=crcDat_out[3][crc_c-1];
end
else if (transf_cnt==`BIT_BLOCK-2) begin
datOut<=4'b1111;
end
else if ((transf_cnt !=0) && (crc_c == 0 ))begin
oeDat<=0;
CardStatus[12:9] <= `TRAN;
end
end
WRITE_FLASH: begin
flash_write_cnt<=flash_write_cnt+1;
CardStatus[12:9] <= `PRG;
datOut[0]<=0;
datOut[1]<=1;
datOut[2]<=1;
datOut[3]<=1;
if (flash_write_cnt == 0)
datOut<=1;
else if(flash_write_cnt == 1)
datOut[0]<=1;
else if(flash_write_cnt == 2)
datOut[0]<=0;
else if ((flash_write_cnt > 1) && (flash_write_cnt < 6)) begin
else if ((flash_write_cnt > 2) && (flash_write_cnt < 7)) begin
if (crc_ok)
datOut[0] <=okcrctoken[5-flash_write_cnt];
datOut[0] <=okcrctoken[6-flash_write_cnt];
else
datOut[0] <= invalidcrctoken[5-flash_write_cnt];
datOut[0] <= invalidcrctoken[6-flash_write_cnt];
end
else if ((flash_write_cnt >= 6) && (flash_write_cnt < 263)) begin
else if ((flash_write_cnt >= 7) && (flash_write_cnt < 264)) begin
datOut[0]<=0;
datOut[1]<=1;
datOut[2]<=1;
datOut[3]<=1;
flash_blockwrite_cnt<=flash_blockwrite_cnt+2;
FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];
FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];
712,7 → 820,7
crcDat_rst<=1;
crcDat_en<=0;
crcDat_in<=0;
flash_write_cnt<=0;
flash_write_cnt<=0;
flash_blockwrite_cnt<=0;
end
endtask

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