URL
https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk
Subversion Repositories sdcard_mass_storage_controller
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/verilog
- from Rev 25 to Rev 26
- ↔ Reverse comparison
Rev 25 → Rev 26
/sd_controller_fifo_wb.v
19,7 → 19,10
sd_cmd_dat_i,sd_cmd_out_o, sd_cmd_oe_o, |
sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad |
//PLL CLK_IN |
// sd_clk_i_pad |
`ifdef SD_CLK_EXT |
,sd_clk_i_pad |
`endif |
|
|
); |
input wb_clk_i; // WISHBONE clock |
38,17 → 41,7
output reg wb_ack_o; // WISHBONE acknowledge output |
|
// WISHBONE master |
output [31:0] m_wb_adr_o; |
output [3:0] m_wb_sel_o; |
output m_wb_we_o; |
|
input [31:0] m_wb_dat_i; |
output [31:0] m_wb_dat_o; |
output m_wb_cyc_o; |
output m_wb_stb_o; |
input m_wb_ack_i; |
output [2:0] m_wb_cti_o; |
output [1:0] m_wb_bte_o; |
|
input wire [3:0] sd_dat_dat_i; |
output wire [3:0] sd_dat_out_o; |
60,7 → 53,7
|
output sd_clk_o_pad; |
wire sd_clk_i; |
//input sd_clk_i_pad; |
input sd_clk_i_pad; |
|
`define tx_cmd_fifo 4'h0 |
`define rx_cmd_fifo 4'h1 |