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Rev 88 → Rev 100

/testapp/uart.h File deleted
/testapp/main.c File deleted
/testapp/BootReset.S.lowram File deleted \ No newline at end of file
/testapp/BootReset.S File deleted \ No newline at end of file
/testapp/orsocdef.h File deleted
/testapp/sd_controller.c File deleted
/testapp/spr_defs.h File deleted
/testapp/uart.c File deleted
/testapp/ram.ld File deleted
/testapp/board.h File deleted
/testapp/sd_controller.h File deleted
/sdc_dma/sd_controller.h
0,0 → 1,153
#ifndef __sd_controller_h_
#define __sd_controller_h_
 
 
//SD_CONTROLLER Register
uint32 test_readwrite(unsigned long arg, unsigned short reg);
 
#define WORD_0 0x00
#define WORD_1 0x40
#define WORD_2 0x80
#define WORD_3 0xC0
 
 
#define SD_ARG 0x00
#define SD_COMMAND 0x04
#define SD_STATUS 0x08
#define SD_RESP1 0x0c
 
#define SD_CTRL 0x1c
#define SD_BLOCK 0x20
#define SD_POWER 0x24
#define SD_SOFTWARE_RST 0x28
#define SD_TIMEOUT 0x2c
#define SD_NORMAL_INT_STATUS 0x30
#define SD_ERROR_INT_STATUS 0x34
#define SD_NORMAL_INT_STATUS_ENABLE 0x38
#define SD_ERROR_INT_STATUS_ENABLE 0x3c
#define SD_NOMAL_INT_SIGNAL_ENABLE 0x40
#define SD_ERROR_INT_SIGNAL_ENABLE 0x44
#define SD_CAPABILITY 0x48
#define SD_CLOCK_D 0x4c
#define BD_STATUS 0x50
#define BD_ISR 0x54
#define BD_RX 0x60
#define BD_TX 0x80
 
 
#define CLK_CARD 25000000
#define CLK_CPU 50000000
#define CMD_TIMEOUT_MS ((CLK_CPU/CLK_CARD) * 512)
#define MAX_POL 1000
#define SD_REG(REG) REG32(SD_CONTROLLER_BASE+REG)
 
 
 
//Commands
#define CMD2 0x200
#define CMD3 0x300
#define CMD7 0x700
#define CMD8 0x800
#define CMD9 0x900
#define CMD16 0x1000
#define CMD17 0x1100
 
#define ACMD41 0x2900
#define ACMD6 0x600
#define CMD55 0x3700
//CMD ARG
//CMD8
#define VHS 0x100 //2.7-3.6V
#define CHECK_PATTERN 0xAA
//ACMD41
#define BUSY 0x80000000
#define HCS 0x40000000
#define VOLTAGE_MASK 0xFFFFFF
 
//CMD7
#define READY_FOR_DATA 0x100
#define CARD_STATUS_STB 0x600
 
//Command setting
#define CICE 0x10
#define CRCE 0x08
#define RSP_48 0x2
#define RSP_146 0x1
 
//Status Mask
//Normal interupt status
#define CMD_COMPLETE 0x1
#define EI 0x8000
 
//Error interupt status
#define CMD_TIMEOUT 0x1
#define CCRC 0x1
#define CIE 0x8
 
#define CID_MID_MASK 0x7F8000
#define CID_OID_MASK 0x7FFF
#define CID_B1 0x7F800000
#define CID_B2 0x7F8000
#define CID_B3 0x7F80
#define CID_B4 0x7F
 
#define RCA_RCA_MASK 0xFFFF0000
 
 
typedef struct {
unsigned int pad:18;
unsigned int cmdi:6;
unsigned int cmdt:2;
unsigned int dps:1;
unsigned int cice:1;
unsigned int crce:1;
unsigned int rsvd:1;
unsigned int rts:2;
}sd_controller_csr ;
 
 
typedef struct {
uint8 mid:8;
uint16 oid:16;
unsigned char pnm[5];
uint8 prv:8;
uint32 psn:32;
uint8 rsv:4;
uint16 mdt:12;
}sd_card_cid;
 
typedef struct {
}sd_card_csd;
 
typedef struct {
uint32 rca;
uint32 Voltage_window;
uint8 HCS_s;
uint8 Active;
uint8 phys_spec_2_0;
sd_card_cid * cid_reg;
sd_card_csd * csd_reg;
 
}sd_card ;
 
 
 
 
 
 
 
 
 
int sd_cmd_free();
int sd_get_cid(sd_card *d);
int sd_get_rca(sd_card *d);
uint8 sd_wait_rsp();
unsigned long sd_ocr_set (unsigned long cmd1, unsigned long arg1, unsigned long cmd2, unsigned long arg2);
sd_card sd_controller_init ();
 
 
 
 
#endif
 
/sdc_dma/uart.h
0,0 → 1,190
/*$$HEADER*/
/******************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/******************************************************************************/
 
// Project Name : Development Board Debugger Example
// File Name : uart.h
// Prepared By : jb
// Project Start : 2009-01-01
// Sourced from OpenCores : http://opencores.org/cvsweb.shtml/or1k/orp/orp_soc/sw/uart/uart.h
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/* */
/* C H A N G E H I S T O R Y */
/* */
/******************************************************************************/
 
// Date Version Description
//------------------------------------------------------------------------
// 090101 1.0 First version jb
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
// UART register definitions, function prototypes
 
/*$$PROTOTYPES*/
/******************************************************************************/
/* */
/* P R O T O T Y P E S */
/* */
/******************************************************************************/
 
extern void uart_init(void);
extern void uart_putc(char);
extern char uart_getc(void);
extern void uart_print_str(char *);
extern void uart_print_long(unsigned long);
 
/*$$DEFINES*/
/******************************************************************************/
/* */
/* D E F I N E S */
/* */
/******************************************************************************/
 
#if 1
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
#define UART_IER 1 /* Out: Interrupt Enable Register */
#define UART_IIR 2 /* In: Interrupt ID Register */
#define UART_FCR 2 /* Out: FIFO Control Register */
#define UART_EFR 2 /* I/O: Extended Features Register */
/* (DLAB=1, 16C660 only) */
#define UART_LCR 3 /* Out: Line Control Register */
#define UART_MCR 4 /* Out: Modem Control Register */
#define UART_LSR 5 /* In: Line Status Register */
#define UART_MSR 6 /* In: Modem Status Register */
#define UART_SCR 7 /* I/O: Scratch Register */
 
#else
 
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
#define UART_DLM 4 /* Out: Divisor Latch High (DLAB=1) */
#define UART_IER 4 /* Out: Interrupt Enable Register */
#define UART_IIR 8 /* In: Interrupt ID Register */
#define UART_FCR 8 /* Out: FIFO Control Register */
#define UART_EFR 8 /* I/O: Extended Features Register */
/* (DLAB=1, 16C660 only) */
#define UART_LCR 12 /* Out: Line Control Register */
#define UART_MCR 12 /* Out: Modem Control Register */
#define UART_LSR 20 /* In: Line Status Register */
#define UART_MSR 24 /* In: Modem Status Register */
#define UART_SCR 28 /* I/O: Scratch Register */
 
#endif
 
/*
* These are the definitions for the FIFO Control Register
* (16650 only)
*/
#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
/* 16650 redefinitions */
#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
 
/*
* These are the definitions for the Line Control Register
*
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
*/
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
#define UART_LCR_SBC 0x40 /* Set break control */
#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
#define UART_LCR_EPAR 0x10 /* Even parity select */
#define UART_LCR_PARITY 0x08 /* Parity Enable */
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
 
/*
* These are the definitions for the Line Status Register
*/
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI 0x10 /* Break interrupt indicator */
#define UART_LSR_FE 0x08 /* Frame error indicator */
#define UART_LSR_PE 0x04 /* Parity error indicator */
#define UART_LSR_OE 0x02 /* Overrun error indicator */
#define UART_LSR_DR 0x01 /* Receiver data ready */
 
/*
* These are the definitions for the Interrupt Identification Register
*/
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
 
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_TOI 0x0c /* Receive time out interrupt */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
 
/*
* These are the definitions for the Interrupt Enable Register
*/
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
 
/*
* These are the definitions for the Modem Control Register
*/
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
#define UART_MCR_OUT2 0x08 /* Out2 complement */
#define UART_MCR_OUT1 0x04 /* Out1 complement */
#define UART_MCR_RTS 0x02 /* RTS complement */
#define UART_MCR_DTR 0x01 /* DTR complement */
 
/*
* These are the definitions for the Modem Status Register
*/
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
#define UART_MSR_RI 0x40 /* Ring Indicator */
#define UART_MSR_DSR 0x20 /* Data Set Ready */
#define UART_MSR_CTS 0x10 /* Clear to Send */
#define UART_MSR_DDCD 0x08 /* Delta DCD */
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR 0x02 /* Delta DSR */
#define UART_MSR_DCTS 0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
 
/*
* These are the definitions for the Extended Features Register
* (StarTech 16C660 only, when DLAB=1)
*/
#define UART_EFR_CTS 0x80 /* CTS flow control */
#define UART_EFR_RTS 0x40 /* RTS flow control */
#define UART_EFR_SCD 0x20 /* Special character detect */
#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */
 
/sdc_dma/main.c
0,0 → 1,344
 
 
/*$$HEADER*/
/******************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/******************************************************************************/
 
// Project Name : Development Board Debugger Example
// File Name : main.c
// Prepared By : jb
// Project Start : 2009-01-01
 
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/* */
/* C O P Y R I G H T N O T I C E */
/* */
/******************************************************************************/
 
// Copyright (c) ORSoC 2009 All rights reserved.
 
// The information in this document is the property of ORSoC.
// Except as specifically authorized in writing by ORSoC, the receiver of
// this document shall keep the information contained herein confidential and
// shall protect the same in whole or in part thereof from disclosure and
// dissemination to third parties. Disclosure and disseminations to the receiver's
// employees shall only be made on a strict need to know basis.
 
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
// Perform some simple functions, used as an example when first using the
// debug cable and proxy with GDB.
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/* */
/* C H A N G E H I S T O R Y */
/* */
/******************************************************************************/
 
// Date Version Description
//------------------------------------------------------------------------
// 090101 1.0 First version jb
 
/*$$INCLUDE FILES*/
/******************************************************************************/
/* */
/* I N C L U D E F I L E S */
/* */
/******************************************************************************/
 
#define INCLUDED_FROM_C_FILE
 
#include "orsocdef.h"
#include "board.h"
#include "uart.h"
#include "sd_controller.h"
/*$$PRIVATE MACROS*/
/******************************************************************************/
/* */
/* P R I V A T E M A C R O S */
/* */
/******************************************************************************/
 
/*$$GLOBAL VARIABLES*/
/******************************************************************************/
/* */
/* G L O B A L V A R I A B L E S */
/* */
/******************************************************************************/
 
/*$$PRIVATE VARIABLES*/
/******************************************************************************/
/* */
/* P R I V A T E V A R I A B L E S */
/* */
/******************************************************************************/
 
 
/*$$FUNCTIONS*/
/******************************************************************************/
/* */
/* F U N C T I O N S */
/* */
/******************************************************************************/
 
 
/******************************************************************************/
/* W R I T E T O EXTERNAL SDRAM 1 */
/******************************************************************************/
 
// Write to External SDRAM
void Write_External_SDRAM_1(void)
{
uint32 i;
uint32 read;
uint32 range;
uint32 adr_offset;
 
range = 0x7ff; // Max range: 0x7fffff
adr_offset = 0x00000000; // External memory offset
for (i=0x0; i < range; i=i+4) {
REG32(adr_offset + i) = (adr_offset + i);
}
 
for (i=0x0; i < range; i=i+4) {
read = REG32(adr_offset + i);
if (read != (adr_offset + i)) {
while(TRUE){ //ERROR=HALT PROCESSOR
}
}
}
}
 
 
/*$$EXTERNAL EXEPTIONS*/
/******************************************************************************/
/* E X T E R N A L E X E P T I O N S */
/******************************************************************************/
 
 
void external_exeption()
{
REG uint8 i;
REG uint32 PicSr,sr;
 
}
/*$$MAIN*/
/******************************************************************************/
/* */
/* M A I N P R O G R A M */
/* */
/******************************************************************************/
 
struct sd_card_csr {
unsigned int PAD:18;
unsigned int CMDI:6;
unsigned int CMDT:2;
unsigned int DPS:1;
unsigned int CICE_s:1;
unsigned int CRCE_s:1;
unsigned int RSVD:1;
unsigned int RTS:2;
} ;
 
 
 
 
 
void Start()
{
struct sd_card_csr *sd_set_reg = (struct sd_card_csr *) (SD_CONTROLLER_BASE+SD_COMMAND);
 
volatile unsigned long rtn_reg=0;
volatile unsigned long rtn_reg1=0;
int i;
unsigned char block[512];
unsigned char blocka[512];
unsigned char blockb[512];
unsigned char rec_block[512];
unsigned char rec_blocka[512];
unsigned char rec_blockb[512];
//Generate som data to be writen
 
for (i =0; i<512;i++)
block[i]=i;
for (i =0; i<512;i++)
blocka[i]=i+8;
for (i =0; i<512;i++)
blockb[i]=0xb6;
 
unsigned long b=0x0001;
sd_card sd_card_0;
uart_init();
 
sd_card_0 = sd_controller_init();
if (sd_card_0.Active==1)
{
uart_print_str("Init 2 succes!\n");
uart_print_str("\nvoltage_windows:\n");
uart_print_long(sd_card_0.Voltage_window);
uart_print_str("\nRCA_Nr:\n");
uart_print_long(sd_card_0.rca);
uart_print_str("\nphys_spec_2_0 Y/N 1/0? :\n");
uart_print_long(sd_card_0.phys_spec_2_0);
uart_print_str("\nHCS? :\n");
uart_print_long(sd_card_0.phys_spec_2_0);
uart_print_str(":\n");
}
else
uart_print_str("Init2 failed :/!\n");
 
SD_REG(SD_COMMAND) = CMD9 |WORD_0| CICE | CRCE | RSP_146;
SD_REG(SD_ARG)=sd_card_0.rca | 0xf0f0;
if (!sd_wait_rsp())
uart_print_str(" send failed :/!\n");
else{
uart_print_str("CSD 0 \n");
uart_print_long( SD_REG(SD_RESP1) ) ;
uart_print_str(" \n");
}
uart_print_str("error? \n");
uart_print_long( SD_REG( SD_ERROR_INT_STATUS) ) ;
 
//Put in transfer state
 
SD_REG(SD_COMMAND) = CMD7 | CICE | CRCE | RSP_48;
SD_REG(SD_ARG)=sd_card_0.rca | 0xf0f0;
if (!sd_wait_rsp())
uart_print_str("Go send failed :/!\n");
else if ( SD_REG(SD_RESP1) == (CARD_STATUS_STB | READY_FOR_DATA ) )
uart_print_str("Ready to transfer data!\n");
//Set block size
SD_REG(SD_COMMAND) = CMD16 | CICE | CRCE | RSP_48;
SD_REG(SD_ARG)=512;
if (!sd_wait_rsp())
uart_print_str("Go send failed :/!\n");
uart_print_str("Card Status reg CMD16: \n");
uart_print_long( SD_REG(SD_RESP1) ) ;
 
//Set Bus width to 4, CMD55 followed by ACMD 6
REG32(SD_CONTROLLER_BASE+SD_COMMAND) = CMD55|RSP_48;
REG32(SD_CONTROLLER_BASE+SD_ARG) =sd_card_0.rca | 0xf0f0;
if (!sd_wait_rsp())
uart_print_str("CMD55 send failed :/!\n");
SD_REG(SD_COMMAND) = ACMD6 | CICE | CRCE | RSP_48;
SD_REG(SD_ARG)=0x2;
if (!sd_wait_rsp())
uart_print_str("ACMD6 send failed :/!\n");
uart_print_str("Card Status reg ACMD6: \n");
uart_print_long( SD_REG(SD_RESP1) ) ;
uart_print_str("\n");
int cnt=0;
uart_print_str("FREE BD beg: \n");
uart_print_long( SD_REG(BD_STATUS) ) ;
uart_print_str("\n");
SD_REG(BD_TX) = &block;
SD_REG(BD_TX) = 512;
SD_REG(BD_TX) = &blocka;
SD_REG(BD_TX) = 1024;
SD_REG(BD_TX) = &blockb;
SD_REG(BD_TX) = 2048;
SD_REG(BD_RX) = &rec_block;
SD_REG(BD_RX) = 512;
SD_REG(BD_RX) = &rec_blocka;
SD_REG(BD_RX) = 1024;
SD_REG(BD_RX) = &rec_blockb;
SD_REG(BD_RX) = 2048;
//Check data transfer complete statusbit
//(An easier way is to check the BD_STATUS and wait for it to get Empty and then check for transfer errors)
while ( (( SD_REG(BD_ISR) &1) !=1 ) ){
rtn_reg= SD_REG(BD_ISR) ;
}
SD_REG(BD_ISR) =0;
while ( (( SD_REG(BD_ISR) &1) !=1 ) ){
rtn_reg= SD_REG(BD_ISR) ;
}
SD_REG(BD_ISR) =0;
while ( (( SD_REG(BD_ISR) &1) !=1 ) ){
rtn_reg= SD_REG(BD_ISR) ;
}
SD_REG(BD_ISR) =0;
while ( (( SD_REG(BD_ISR) &1) !=1 ) ){
rtn_reg= SD_REG(BD_ISR) ;
}
SD_REG(BD_ISR) =0;
while ( (( SD_REG(BD_ISR) &1) !=1 ) ){
rtn_reg= SD_REG(BD_ISR) ;
}
SD_REG(BD_ISR) =0;
while ( (( SD_REG(BD_ISR) &1) !=1 ) ){
rtn_reg= SD_REG(BD_ISR) ;
}
SD_REG(BD_ISR) =0;
uart_print_str("FREE BD: \n");
uart_print_long( SD_REG(BD_STATUS) ) ;
uart_print_str("\n");
SD_REG(BD_ISR) =0;
uart_print_str("\n");
for (i =0; i<512;i++) {
uart_print_short (rec_block[i]);
uart_print_str(".");
}
uart_print_str("\n");
for (i =0; i<512;i++) {
uart_print_short (rec_blocka[i]);
uart_print_str(".");
}
uart_print_str("\n");
for (i =0; i<512;i++) {
uart_print_short (rec_blockb[i]);
uart_print_str(".");
}
uart_print_str("done");
#endif
 
 
}
 
/sdc_dma/BootReset.S
0,0 → 1,320
/*$$HEADER*/
/******************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/******************************************************************************/
 
// Project Name : Development Board Debugger Example
// File Name : BootReset.S
// Prepared By : jb
// Project Start : 2009-01-01
 
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/* */
/* C O P Y R I G H T N O T I C E */
/* */
/******************************************************************************/
 
// Copyright (c) ORSoC 2009 All rights reserved.
 
// The information in this document is the property of ORSoC.
// Except as specifically authorized in writing by ORSoC, the receiver of
// this document shall keep the information contained herein confidential and
// shall protect the same in whole or in part thereof from disclosure and
// dissemination to third parties. Disclosure and disseminations to the receiver's
// employees shall only be made on a strict need to know basis.
 
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
// Define the contents of the reset vector (from 0x100), an IC enable routine
// as well as en external IRQ service routine.
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/* */
/* C H A N G E H I S T O R Y */
/* */
/******************************************************************************/
 
// Date Version Description
//------------------------------------------------------------------------
// 090101 1.0 First version jb
 
 
/*$$INCLUDE FILES*/
/******************************************************************************/
/* */
/* I N C L U D E F I L E S */
/* */
/******************************************************************************/
 
#include "board.h"
#include "spr_defs.h"
 
/*$$PRIVATE MACROS*/
/******************************************************************************/
/* */
/* P R I V A T E M A C R O S */
/* */
/******************************************************************************/
 
/******************************************************************************/
/* L O A D 3 2 B I T C O N S T A N T I N T O R E G I S T E R */
/******************************************************************************/
 
.macro load32i reg const
l.movhi \reg,hi(\const)
l.ori \reg,\reg,lo(\const)
.endm
 
/******************************************************************************/
/* S E T U P E X C E P T I O N V E C T O R */
/******************************************************************************/
 
.macro exception_vector name org
.org \org
.p2align 8
.global __exception_\name
__exception_\name:
l.j __exception_\name
l.nop
.endm
 
/******************************************************************************/
/* B R A N C H T O N A M E */
/******************************************************************************/
 
.macro BSR name
l.j \name
l.nop
ret_\name:
.endm
 
 
/*$$RESET START*/
/******************************************************************************/
/* */
/* R E S E T S T A R T */
/* */
/******************************************************************************/
 
.section .vectors, "ax"
 
.org 0x100 - 0x100 // Sector .vectors start at 0x100
 
 
_reset:
 
// Set stack pointer (r1) to 00003560
// Clear all other registers
 
.equ sp,0x00003560 ;
l.movhi r0,0x0000 ; #r0 = 0
l.ori r0,r0,0x0000 ;
l.movhi r1,hi(sp) ; #r1 = sp
l.ori r1,r1,lo(sp) ;
l.or r2,r0,r0 ; #clear r2
l.or r3,r0,r0 ; #clear r3
l.or r4,r0,r0 ; #clear r4
l.or r5,r0,r0 ; #clear r5
l.or r6,r0,r0 ; #clear r6
l.or r7,r0,r0 ; #clear r7
l.or r8,r0,r0 ; #clear r8
l.or r9,r0,r0 ; #clear r9
l.or r10,r0,r0 ; #clear r10
l.or r11,r0,r0 ; #clear r11
l.or r12,r0,r0 ; #clear r12
l.or r13,r0,r0 ; #clear r13
l.or r14,r0,r0 ; #clear r14
l.or r15,r0,r0 ; #clear r15
l.or r16,r0,r0 ; #clear r16
l.or r17,r0,r0 ; #clear r17
l.or r18,r0,r0 ; #clear r18
l.or r19,r0,r0 ; #clear r19
l.or r20,r0,r0 ; #clear r20
l.or r21,r0,r0 ; #clear r21
l.or r22,r0,r0 ; #clear r22
l.or r23,r0,r0 ; #clear r23
l.or r24,r0,r0 ; #clear r24
l.or r25,r0,r0 ; #clear r25
l.or r26,r0,r0 ; #clear r26
l.or r27,r0,r0 ; #clear r27
l.or r28,r0,r0 ; #clear r28
l.or r29,r0,r0 ; #clear r29
l.or r30,r0,r0 ; #clear r30
l.or r31,r0,r0 ; #clear r31
 
#if IC_ENABLE == 1 /* INSTRUCTION CACHE */
BSR ic_enable
#endif
 
// Jump to start of program
 
load32i r2, (_Start)
l.jr r2
l.nop
 
exception_vector bus_error 0x200 - 0x100 // Sector .vectors start at 0x100
exception_vector data_page_fault 0x300 - 0x100 // Sector .vectors start at 0x100
exception_vector instruction_page_fault 0x400 - 0x100 // Sector .vectors start at 0x100
exception_vector tick_timer 0x500 - 0x100 // Sector .vectors start at 0x100
exception_vector unaligned_access 0x600 - 0x100 // Sector .vectors start at 0x100
exception_vector illegal_instruction 0x700 - 0x100 // Sector .vectors start at 0x100
 
 
// Defines what will happen when an external interrupt occurs
 
.org 0x800 - 0x100
 
.global __external_IRQ
 
__external_IRQ:
l.addi r1,r1,-30*4 //move SP 30*4 adresses lower
 
l.sw 0x1c(r1),r9
l.jal (save_state)
l.nop
// we mess with r3, r4 and r9
//
l.mfspr r3,r0,SPR_ESR_BASE // get SR before interrupt
l.andi r4,r3,SPR_SR_IEE // check if it had SPR_SR_IEE bit enabled
l.sfeqi r4,0
l.bnf JUMP // external irq enabled, all ok.
l.nop
 
JUMP: l.jal (_external_exeption)
l.nop
 
l.jal (restore_state)
l.nop
 
l.lwz r9 ,0x1c(r1)
l.addi r1,r1,30*4 //move SP 30*4 adresses lower
//Return from exception
l.rfe
 
 
// Save current state (all general purpose registers)
 
save_state:
l.sw 0x0(r1),r2
l.sw 0x4(r1),r3
l.sw 0x8(r1),r4
l.sw 0xc(r1),r5
l.sw 0x10(r1),r6
l.sw 0x14(r1),r7
l.sw 0x18(r1),r8
l.sw 0x20(r1),r10
l.sw 0x24(r1),r11
l.sw 0x28(r1),r12
l.sw 0x2c(r1),r13
l.sw 0x30(r1),r14
l.sw 0x34(r1),r15
l.sw 0x38(r1),r16
l.sw 0x3c(r1),r17
l.sw 0x40(r1),r18
l.sw 0x44(r1),r19
l.sw 0x48(r1),r20
l.sw 0x4c(r1),r21
l.sw 0x50(r1),r22
l.sw 0x54(r1),r23
l.sw 0x58(r1),r24
l.sw 0x5c(r1),r25
l.sw 0x60(r1),r26
l.sw 0x64(r1),r27
l.sw 0x68(r1),r28
l.sw 0x6c(r1),r29
l.sw 0x70(r1),r30
l.jr r9
l.nop
 
// Restore current state
 
restore_state:
// disable interrupts (if needed)
l.lwz r2,0x0(r1)
l.lwz r3 ,0x4(r1)
l.lwz r4 ,0x8(r1)
l.lwz r5 ,0xc(r1)
l.lwz r6 ,0x10(r1)
l.lwz r7 ,0x14(r1)
l.lwz r8 ,0x18(r1)
l.lwz r10,0x20(r1)
l.lwz r11,0x24(r1)
l.lwz r12,0x28(r1)
l.lwz r13,0x2c(r1)
l.lwz r14,0x30(r1)
l.lwz r15,0x34(r1)
l.lwz r16,0x38(r1)
l.lwz r17,0x3c(r1)
l.lwz r18,0x40(r1)
l.lwz r19,0x44(r1)
l.lwz r20,0x48(r1)
l.lwz r21,0x4c(r1)
l.lwz r22,0x50(r1)
l.lwz r23,0x54(r1)
l.lwz r24,0x58(r1)
l.lwz r25,0x5c(r1)
l.lwz r26,0x60(r1)
l.lwz r27,0x64(r1)
l.lwz r28,0x68(r1)
l.lwz r29,0x6c(r1)
l.lwz r30,0x70(r1)
l.jr r9
l.nop
 
 
 
/***************************
* Instruction cache enable
*/
#if IC_ENABLE == 1
ic_enable:
 
/* Disable IC */
l.mfspr r6,r0,SPR_SR
l.addi r5,r0,-1
l.xori r5,r5,SPR_SR_ICE
l.and r5,r6,r5
l.mtspr r0,r5,SPR_SR
 
/* Invalidate IC */
l.addi r6,r0,0
l.addi r5,r0,IC_SIZE
1:
l.mtspr r0,r6,SPR_ICBIR
l.sfne r6,r5
l.bf 1b
l.addi r6,r6,IC_LINE
 
/* Enable IC */
l.mfspr r6,r0,SPR_SR
l.ori r6,r6,SPR_SR_ICE
l.mtspr r0,r6,SPR_SR
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.j ret_ic_enable
l.nop
#endif
/sdc_dma/BootReset.S.lowram
0,0 → 1,320
/*$$HEADER*/
/******************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/******************************************************************************/
 
// Project Name : Development Board Debugger Example
// File Name : BootReset.S
// Prepared By : jb
// Project Start : 2009-01-01
 
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/* */
/* C O P Y R I G H T N O T I C E */
/* */
/******************************************************************************/
 
// Copyright (c) ORSoC 2009 All rights reserved.
 
// The information in this document is the property of ORSoC.
// Except as specifically authorized in writing by ORSoC, the receiver of
// this document shall keep the information contained herein confidential and
// shall protect the same in whole or in part thereof from disclosure and
// dissemination to third parties. Disclosure and disseminations to the receiver's
// employees shall only be made on a strict need to know basis.
 
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
// Define the contents of the reset vector (from 0x100), an IC enable routine
// as well as en external IRQ service routine.
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/* */
/* C H A N G E H I S T O R Y */
/* */
/******************************************************************************/
 
// Date Version Description
//------------------------------------------------------------------------
// 090101 1.0 First version jb
 
 
/*$$INCLUDE FILES*/
/******************************************************************************/
/* */
/* I N C L U D E F I L E S */
/* */
/******************************************************************************/
 
#include "board.h"
#include "spr_defs.h"
 
/*$$PRIVATE MACROS*/
/******************************************************************************/
/* */
/* P R I V A T E M A C R O S */
/* */
/******************************************************************************/
 
/******************************************************************************/
/* L O A D 3 2 B I T C O N S T A N T I N T O R E G I S T E R */
/******************************************************************************/
 
.macro load32i reg const
l.movhi \reg,hi(\const)
l.ori \reg,\reg,lo(\const)
.endm
 
/******************************************************************************/
/* S E T U P E X C E P T I O N V E C T O R */
/******************************************************************************/
 
.macro exception_vector name org
.org \org
.p2align 8
.global __exception_\name
__exception_\name:
l.j __exception_\name
l.nop
.endm
 
/******************************************************************************/
/* B R A N C H T O N A M E */
/******************************************************************************/
 
.macro BSR name
l.j \name
l.nop
ret_\name:
.endm
 
 
/*$$RESET START*/
/******************************************************************************/
/* */
/* R E S E T S T A R T */
/* */
/******************************************************************************/
 
.section .vectors, "ax"
 
.org 0x100 - 0x100 // Sector .vectors start at 0x100
 
 
_reset:
 
// Set stack pointer (r1) to 00003560
// Clear all other registers
 
.equ sp,0x00003560 ;
l.movhi r0,0x0000 ; #r0 = 0
l.ori r0,r0,0x0000 ;
l.movhi r1,hi(sp) ; #r1 = sp
l.ori r1,r1,lo(sp) ;
l.or r2,r0,r0 ; #clear r2
l.or r3,r0,r0 ; #clear r3
l.or r4,r0,r0 ; #clear r4
l.or r5,r0,r0 ; #clear r5
l.or r6,r0,r0 ; #clear r6
l.or r7,r0,r0 ; #clear r7
l.or r8,r0,r0 ; #clear r8
l.or r9,r0,r0 ; #clear r9
l.or r10,r0,r0 ; #clear r10
l.or r11,r0,r0 ; #clear r11
l.or r12,r0,r0 ; #clear r12
l.or r13,r0,r0 ; #clear r13
l.or r14,r0,r0 ; #clear r14
l.or r15,r0,r0 ; #clear r15
l.or r16,r0,r0 ; #clear r16
l.or r17,r0,r0 ; #clear r17
l.or r18,r0,r0 ; #clear r18
l.or r19,r0,r0 ; #clear r19
l.or r20,r0,r0 ; #clear r20
l.or r21,r0,r0 ; #clear r21
l.or r22,r0,r0 ; #clear r22
l.or r23,r0,r0 ; #clear r23
l.or r24,r0,r0 ; #clear r24
l.or r25,r0,r0 ; #clear r25
l.or r26,r0,r0 ; #clear r26
l.or r27,r0,r0 ; #clear r27
l.or r28,r0,r0 ; #clear r28
l.or r29,r0,r0 ; #clear r29
l.or r30,r0,r0 ; #clear r30
l.or r31,r0,r0 ; #clear r31
 
#if IC_ENABLE == 1 /* INSTRUCTION CACHE */
BSR ic_enable
#endif
 
// Jump to start of program
 
load32i r2, (_Start)
l.jr r2
l.nop
 
exception_vector bus_error 0x200 - 0x100 // Sector .vectors start at 0x100
exception_vector data_page_fault 0x300 - 0x100 // Sector .vectors start at 0x100
exception_vector instruction_page_fault 0x400 - 0x100 // Sector .vectors start at 0x100
exception_vector tick_timer 0x500 - 0x100 // Sector .vectors start at 0x100
exception_vector unaligned_access 0x600 - 0x100 // Sector .vectors start at 0x100
exception_vector illegal_instruction 0x700 - 0x100 // Sector .vectors start at 0x100
 
 
// Defines what will happen when an external interrupt occurs
 
.org 0x800 - 0x100
 
.global __external_IRQ
 
__external_IRQ:
l.addi r1,r1,-30*4 //move SP 30*4 adresses lower
 
l.sw 0x1c(r1),r9
l.jal (save_state)
l.nop
// we mess with r3, r4 and r9
//
l.mfspr r3,r0,SPR_ESR_BASE // get SR before interrupt
l.andi r4,r3,SPR_SR_IEE // check if it had SPR_SR_IEE bit enabled
l.sfeqi r4,0
l.bnf JUMP // external irq enabled, all ok.
l.nop
 
JUMP: l.jal (_external_exeption)
l.nop
 
l.jal (restore_state)
l.nop
 
l.lwz r9 ,0x1c(r1)
l.addi r1,r1,30*4 //move SP 30*4 adresses lower
//Return from exception
l.rfe
 
 
// Save current state (all general purpose registers)
 
save_state:
l.sw 0x0(r1),r2
l.sw 0x4(r1),r3
l.sw 0x8(r1),r4
l.sw 0xc(r1),r5
l.sw 0x10(r1),r6
l.sw 0x14(r1),r7
l.sw 0x18(r1),r8
l.sw 0x20(r1),r10
l.sw 0x24(r1),r11
l.sw 0x28(r1),r12
l.sw 0x2c(r1),r13
l.sw 0x30(r1),r14
l.sw 0x34(r1),r15
l.sw 0x38(r1),r16
l.sw 0x3c(r1),r17
l.sw 0x40(r1),r18
l.sw 0x44(r1),r19
l.sw 0x48(r1),r20
l.sw 0x4c(r1),r21
l.sw 0x50(r1),r22
l.sw 0x54(r1),r23
l.sw 0x58(r1),r24
l.sw 0x5c(r1),r25
l.sw 0x60(r1),r26
l.sw 0x64(r1),r27
l.sw 0x68(r1),r28
l.sw 0x6c(r1),r29
l.sw 0x70(r1),r30
l.jr r9
l.nop
 
// Restore current state
 
restore_state:
// disable interrupts (if needed)
l.lwz r2,0x0(r1)
l.lwz r3 ,0x4(r1)
l.lwz r4 ,0x8(r1)
l.lwz r5 ,0xc(r1)
l.lwz r6 ,0x10(r1)
l.lwz r7 ,0x14(r1)
l.lwz r8 ,0x18(r1)
l.lwz r10,0x20(r1)
l.lwz r11,0x24(r1)
l.lwz r12,0x28(r1)
l.lwz r13,0x2c(r1)
l.lwz r14,0x30(r1)
l.lwz r15,0x34(r1)
l.lwz r16,0x38(r1)
l.lwz r17,0x3c(r1)
l.lwz r18,0x40(r1)
l.lwz r19,0x44(r1)
l.lwz r20,0x48(r1)
l.lwz r21,0x4c(r1)
l.lwz r22,0x50(r1)
l.lwz r23,0x54(r1)
l.lwz r24,0x58(r1)
l.lwz r25,0x5c(r1)
l.lwz r26,0x60(r1)
l.lwz r27,0x64(r1)
l.lwz r28,0x68(r1)
l.lwz r29,0x6c(r1)
l.lwz r30,0x70(r1)
l.jr r9
l.nop
 
 
 
/***************************
* Instruction cache enable
*/
#if IC_ENABLE == 1
ic_enable:
 
/* Disable IC */
l.mfspr r6,r0,SPR_SR
l.addi r5,r0,-1
l.xori r5,r5,SPR_SR_ICE
l.and r5,r6,r5
l.mtspr r0,r5,SPR_SR
 
/* Invalidate IC */
l.addi r6,r0,0
l.addi r5,r0,IC_SIZE
1:
l.mtspr r0,r6,SPR_ICBIR
l.sfne r6,r5
l.bf 1b
l.addi r6,r6,IC_LINE
 
/* Enable IC */
l.mfspr r6,r0,SPR_SR
l.ori r6,r6,SPR_SR_ICE
l.mtspr r0,r6,SPR_SR
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.j ret_ic_enable
l.nop
#endif
/sdc_dma/orsocdef.h
0,0 → 1,136
#ifndef __orsocdef_h_
#define __orsocdef_h_
/*$$HEADER*/
/******************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/******************************************************************************/
 
// Project Name : Development Board Debugger Example
// File Name : orsocdef.h
// Prepared By : jb
// Project Start : 2009-01-01
 
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/* */
/* C O P Y R I G H T N O T I C E */
/* */
/******************************************************************************/
 
// Copyright (c) ORSoC 2009 All rights reserved.
 
// The information in this document is the property of ORSoC.
// Except as specifically authorized in writing by ORSoC, the receiver of
// this document shall keep the information contained herein confidential and
// shall protect the same in whole or in part thereof from disclosure and
// dissemination to third parties. Disclosure and disseminations to the receiver's
// employees shall only be made on a strict need to know basis.
 
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
// Define some types used in our project.
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/* */
/* C H A N G E H I S T O R Y */
/* */
/******************************************************************************/
 
// Date Version Description
//------------------------------------------------------------------------
// 090101 1.0 First version jb
 
/*$$GENERAL PARTS*/
/******************************************************************************/
/* */
/* G E N E R A L P A R T S */
/* */
/******************************************************************************/
 
 
/******************************************************************************/
/* T Y P E D E F S */
/******************************************************************************/
 
typedef unsigned int uint;
 
/******************************************************************************/
/* M A C R O S */
/******************************************************************************/
 
/* Max and min functions */
 
#define MIN(a,b) (((a)<(b))?(a):(b))
#define MAX(a,b) (((a)>(b))?(a):(b))
 
/* the nuldelimiter of a string */
 
#define NUL3 '\n'
 
#define OK 1
#define NOK 0
 
/* nullpointer is defined if not already done */
 
#ifndef NULL
#define NULL (void *)0
#endif
 
/* define min and max for all types */
 
#define INT8_MAX 0x7F
#define UINT8_MAX 0xFF
#define INT16_MAX 0x7FFF
#define UINT16_MAX 0xFFFF
#define INT32_MAX 0x7FFFFFFF
#define UINT32_MAX 0xFFFFFFFF
#define FALSE 0
#define TRUE !FALSE
 
/******************************************************************************/
/* R E G I S T E R A C C E S S M A C R O S */
/******************************************************************************/
 
#define REG8(add) *((volatile unsigned char *) (add))
#define REG16(add) *((volatile unsigned short *) (add))
#define REG32(add) *((volatile unsigned long *) (add))
 
 
/******************************************************************************/
/* G C C C O M P I L E R */
/******************************************************************************/
 
#if defined (__GNUC__)
 
typedef unsigned char bool;
 
typedef signed char int8;
typedef signed short int16;
typedef signed long int32;
 
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned long uint32;
 
typedef unsigned char char8;
typedef unsigned short char16;
 
 
#else
 
#error Undefined compiler used !
 
#endif
 
#endif
 
/sdc_dma/sd_controller.c
0,0 → 1,133
 
#include "orsocdef.h"
#include "board.h"
#include "sd_controller.h"
 
#define SD_REG(REG) REG32(SD_CONTROLLER_BASE+REG)
 
 
 
int sd_get_rca(sd_card *d)
{
uint32 rtn_reg=0;
SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48;
SD_REG(SD_ARG)=0;
 
if (sd_wait_rsp() == 0)
return 0;
else{
rtn_reg = SD_REG(SD_NORMAL_INT_STATUS);
if ( (rtn_reg & EI) == EI) //Error in response, init failed return.
return 0;
rtn_reg = SD_REG(SD_RESP1);
d->rca=((rtn_reg&RCA_RCA_MASK)>>16);
uart_print_str("rca fine");
}
return 1;
 
}
 
 
//return 0 if no response else return 1.
uint8 sd_wait_rsp()
{
volatile unsigned long r1, r2;
//Polling for timeout and command complete
while (1 )
{
r1= SD_REG(SD_ERROR_INT_STATUS);
r2= SD_REG(SD_NORMAL_INT_STATUS) ;
if (( r1 & CMD_TIMEOUT ) == CMD_TIMEOUT)
return 0;
else if ((r2 & CMD_COMPLETE ) == CMD_COMPLETE)
return 1;
}
//Later Exception restart module
return 0;
}
 
 
 
int sd_cmd_free() //Return 1 if CMD is busy
{
unsigned int a= SD_REG(SD_STATUS);
return (a & 1);
}
sd_card sd_controller_init ()
{
sd_card dev;
 
volatile unsigned long rtn_reg=0;
volatile unsigned long rtn_reg1=0;
REG32(SD_CONTROLLER_BASE+SD_TIMEOUT)=0x00008FF;
REG32(SD_CONTROLLER_BASE+SD_SOFTWARE_RST)=0x0000001;
REG32(SD_CONTROLLER_BASE+SD_CLOCK_D)=0x0000002;
REG32(SD_CONTROLLER_BASE+SD_SOFTWARE_RST)=0x0000000;
REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000;
REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;
sd_wait_rsp();
SD_REG(SD_COMMAND) = ( CMD8 | CICE | CRCE | RSP_48);
SD_REG(SD_ARG) = VHS|CHECK_PATTERN;
dev.phys_spec_2_0 = sd_wait_rsp();
REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000;
REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;
sd_wait_rsp();
if (dev.phys_spec_2_0)
{
// uart_print_str("2_0 CARD /n");
return dev;
}
else
{
REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000;
REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;
while (REG32(SD_CONTROLLER_BASE+SD_STATUS)& 1) {}
 
rtn_reg=0;
while ((rtn_reg & BUSY) != BUSY)
{
REG32(SD_CONTROLLER_BASE+SD_COMMAND) = CMD55|RSP_48;
REG32(SD_CONTROLLER_BASE+SD_ARG) =0;
if (!sd_wait_rsp())
return dev;
REG32(SD_CONTROLLER_BASE+SD_COMMAND) =ACMD41 | RSP_48;
REG32(SD_CONTROLLER_BASE+SD_ARG) =0;
if (!sd_wait_rsp())
return dev;
rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ;
}
dev.Voltage_window=rtn_reg&VOLTAGE_MASK;
dev.HCS_s = 0;
 
}
 
//GET CID
REG32(SD_CONTROLLER_BASE+SD_COMMAND) =CMD2 | RSP_146;
REG32(SD_CONTROLLER_BASE+SD_ARG) =0;
if (!sd_wait_rsp())
return dev;
//Get RCA
SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48;
SD_REG(SD_ARG)=0;
if (!sd_wait_rsp())
return dev;
rtn_reg = SD_REG(SD_RESP1);
dev.rca = ((rtn_reg&RCA_RCA_MASK));
dev.Active=1;
return dev;
 
}
/sdc_dma/spr_defs.h
0,0 → 1,473
 
/*$$HEADER*/
/******************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/******************************************************************************/
 
// Project Name : Development Board Debugger Example
// File Name : BootReset.S
// Prepared By : jb
// Project Start : 2009-01-01
 
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/* */
/* C O P Y R I G H T N O T I C E */
/* */
/******************************************************************************/
 
// Copyright (c) ORSoC 2009 All rights reserved.
 
// The information in this document is the property of ORSoC.
// Except as specifically authorized in writing by ORSoC, the receiver of
// this document shall keep the information contained herein confidential and
// shall protect the same in whole or in part thereof from disclosure and
// dissemination to third parties. Disclosure and disseminations to the receiver's
// employees shall only be made on a strict need to know basis.
 
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
 
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/* */
/* C H A N G E H I S T O R Y */
/* */
/******************************************************************************/
 
// Date Version Description
//------------------------------------------------------------------------
// 090101 1.0 First version jb
 
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
// spr_defs.h -- Defines OR1K architecture specific special-purpose registers
 
 
/*$$DEFINES*/
/******************************************************************************/
/* */
/* D E F I N E S */
/* */
/******************************************************************************/
 
#define MAX_GRPS (32)
#define MAX_SPRS_PER_GRP_BITS (11)
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
#define MAX_SPRS (0x10000)
 
/* Base addresses for the groups */
#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
 
/* System control and status group */
#define SPR_VR (SPRGROUP_SYS + 0)
#define SPR_UPR (SPRGROUP_SYS + 1)
#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
#define SPR_DCCFGR (SPRGROUP_SYS + 5)
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
#define SPR_DCFGR (SPRGROUP_SYS + 7)
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
 
/* Data MMU group */
#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
 
/* Instruction MMU group */
#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
 
/* Data cache group */
#define SPR_DCCR (SPRGROUP_DC + 0)
#define SPR_DCBPR (SPRGROUP_DC + 1)
#define SPR_DCBFR (SPRGROUP_DC + 2)
#define SPR_DCBIR (SPRGROUP_DC + 3)
#define SPR_DCBWR (SPRGROUP_DC + 4)
#define SPR_DCBLR (SPRGROUP_DC + 5)
#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
 
/* Instruction cache group */
#define SPR_ICCR (SPRGROUP_IC + 0)
#define SPR_ICBPR (SPRGROUP_IC + 1)
#define SPR_ICBIR (SPRGROUP_IC + 2)
#define SPR_ICBLR (SPRGROUP_IC + 3)
#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
 
/* MAC group */
#define SPR_MACLO (SPRGROUP_MAC + 1)
#define SPR_MACHI (SPRGROUP_MAC + 2)
 
/* Debug group */
#define SPR_DVR(N) (SPRGROUP_D + (N))
#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
#define SPR_DMR1 (SPRGROUP_D + 16)
#define SPR_DMR2 (SPRGROUP_D + 17)
#define SPR_DWCR0 (SPRGROUP_D + 18)
#define SPR_DWCR1 (SPRGROUP_D + 19)
#define SPR_DSR (SPRGROUP_D + 20)
#define SPR_DRR (SPRGROUP_D + 21)
 
/* Performance counters group */
#define SPR_PCCR(N) (SPRGROUP_PC + (N))
#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
 
/* Power management group */
#define SPR_PMR (SPRGROUP_PM + 0)
 
/* PIC group */
#define SPR_PICMR (SPRGROUP_PIC + 0)
#define SPR_PICPR (SPRGROUP_PIC + 1)
#define SPR_PICSR (SPRGROUP_PIC + 2)
 
/* Tick Timer group */
#define SPR_TTMR (SPRGROUP_TT + 0)
#define SPR_TTCR (SPRGROUP_TT + 1)
 
/*
* Bit definitions for the Version Register
*
*/
#define SPR_VR_VER 0xffff0000 /* Processor version */
#define SPR_VR_REV 0x0000003f /* Processor revision */
 
/*
* Bit definitions for the Unit Present Register
*
*/
#define SPR_UPR_UP 0x00000001 /* UPR present */
#define SPR_UPR_DCP 0x00000002 /* Data cache present */
#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */
#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */
#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */
#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */
#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */
#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */
#define SPR_UPR_DUP 0x00000800 /* Debug unit present */
#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */
#define SPR_UPR_PMP 0x00002000 /* Power management present */
#define SPR_UPR_PICP 0x00004000 /* PIC present */
#define SPR_UPR_TTP 0x00008000 /* Tick timer present */
#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */
#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */
#define SPR_UPR_CUST 0xff000000 /* Custom units */
 
/*
* Bit definitions for the Supervision Register
*
*/
#define SPR_SR_CID 0xf0000000 /* Context ID */
#define SPR_SR_FO 0x00008000 /* Fixed one */
#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */
#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
#define SPR_SR_OV 0x00000800 /* Overflow flag */
#define SPR_SR_CY 0x00000400 /* Carry flag */
#define SPR_SR_F 0x00000200 /* Condition Flag */
#define SPR_SR_CE 0x00000100 /* CID Enable */
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
 
/*
* Bit definitions for the Data MMU Control Register
*
*/
#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
 
/*
* Bit definitions for the Instruction MMU Control Register
*
*/
#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
 
/*
* Bit definitions for the Data TLB Match Register
*
*/
#define SPR_DTLBMR_V 0x00000001 /* Valid */
#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
 
/*
* Bit definitions for the Data TLB Translate Register
*
*/
#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
#define SPR_DTLBTR_A 0x00000010 /* Accessed */
#define SPR_DTLBTR_D 0x00000020 /* Dirty */
#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
 
/*
* Bit definitions for the Instruction TLB Match Register
*
*/
#define SPR_ITLBMR_V 0x00000001 /* Valid */
#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
 
/*
* Bit definitions for the Instruction TLB Translate Register
*
*/
#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
#define SPR_ITLBTR_A 0x00000010 /* Accessed */
#define SPR_ITLBTR_D 0x00000020 /* Dirty */
#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
 
/*
* Bit definitions for Data Cache Control register
*
*/
#define SPR_DCCR_EW 0x000000ff /* Enable ways */
 
/*
* Bit definitions for Insn Cache Control register
*
*/
#define SPR_ICCR_EW 0x000000ff /* Enable ways */
 
/*
* Bit definitions for Debug Control registers
*
*/
#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
#define SPR_DCR_CC 0x0000000e /* Compare condition */
#define SPR_DCR_SC 0x00000010 /* Signed compare */
#define SPR_DCR_CT 0x000000e0 /* Compare to */
 
/* Bit results with SPR_DCR_CC mask */
#define SPR_DCR_CC_MASKED 0x00000000
#define SPR_DCR_CC_EQUAL 0x00000001
#define SPR_DCR_CC_LESS 0x00000002
#define SPR_DCR_CC_LESSE 0x00000003
#define SPR_DCR_CC_GREAT 0x00000004
#define SPR_DCR_CC_GREATE 0x00000005
#define SPR_DCR_CC_NEQUAL 0x00000006
 
/* Bit results with SPR_DCR_CT mask */
#define SPR_DCR_CT_DISABLED 0x00000000
#define SPR_DCR_CT_IFEA 0x00000020
#define SPR_DCR_CT_LEA 0x00000040
#define SPR_DCR_CT_SEA 0x00000060
#define SPR_DCR_CT_LD 0x00000080
#define SPR_DCR_CT_SD 0x000000a0
#define SPR_DCR_CT_LSEA 0x000000c0
 
/*
* Bit definitions for Debug Mode 1 register
*
*/
#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */
#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */
#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */
#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */
#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */
#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */
#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */
#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */
#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */
#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */
#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
#define SPR_DMR1_BT 0x00800000 /* Branch trace */
#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */
 
/*
* Bit definitions for Debug Mode 2 register
*
*/
#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */
#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */
 
/*
* Bit definitions for Debug watchpoint counter registers
*
*/
#define SPR_DWCR_COUNT 0x0000ffff /* Count */
#define SPR_DWCR_MATCH 0xffff0000 /* Match */
 
/*
* Bit definitions for Debug stop register
*
*/
#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */
#define SPR_DSR_AE 0x00000020 /* Alignment exception */
#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
#define SPR_DSR_RE 0x00000400 /* Range exception */
#define SPR_DSR_SCE 0x00000800 /* System call exception */
#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
#define SPR_DSR_TE 0x00002000 /* Trap exception */
 
/*
* Bit definitions for Debug reason register
*
*/
#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
#define SPR_DRR_AE 0x00000020 /* Alignment exception */
#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
#define SPR_DRR_RE 0x00000400 /* Range exception */
#define SPR_DRR_SCE 0x00000800 /* System call exception */
#define SPR_DRR_TE 0x00001000 /* Trap exception */
 
/*
* Bit definitions for Performance counters mode registers
*
*/
#define SPR_PCMR_CP 0x00000001 /* Counter present */
#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
#define SPR_PCMR_LA 0x00000010 /* Load access event */
#define SPR_PCMR_SA 0x00000020 /* Store access event */
#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
 
/*
* Bit definitions for the Power management register
*
*/
#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
 
/*
* Bit definitions for PICMR
*
*/
#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
 
/*
* Bit definitions for PICPR
*
*/
#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
 
/*
* Bit definitions for PICSR
*
*/
#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
 
/*
* Bit definitions for Tick Timer Control Register
*
*/
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
#define SPR_TTMR_RT 0x40000000 /* Restart tick */
#define SPR_TTMR_SR 0x80000000 /* Single run */
#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
#define SPR_TTMR_M 0xc0000000 /* Tick mode */
 
/*
* l.nop constants
*
*/
#define NOP_NOP 0x0000 /* Normal nop instruction */
#define NOP_EXIT 0x0001 /* End of simulation */
#define NOP_REPORT 0x0002 /* Simple report */
#define NOP_PRINTF 0x0003 /* Simprintf instruction */
#define NOP_REPORT_FIRST 0x0400 /* Report with number */
#define NOP_REPORT_LAST 0x03ff /* Report with number */
/sdc_dma/uart.c
0,0 → 1,209
/*$$HEADER*/
/******************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/******************************************************************************/
 
// Project Name : Development Board Debugger Example
// File Name : uart.c
// Prepared By : jb
// Project Start : 2009-01-01
// Sourced from OpenCores : http://opencores.org/cvsweb.shtml/or1k/orp/orp_soc/sw/uart/uart.c
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/* */
/* C H A N G E H I S T O R Y */
/* */
/******************************************************************************/
 
// Date Version Description
//------------------------------------------------------------------------
// 090101 1.0 First version, commented out main() jb
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
// UART initialisation and usage functions
 
/*$$INCLUDE FILES*/
/******************************************************************************/
/* */
/* I N C L U D E F I L E S */
/* */
/******************************************************************************/
 
#include "orsocdef.h"
#include "board.h"
#include "uart.h"
 
/*$$DEFINES*/
/******************************************************************************/
/* */
/* D E F I N E S */
/* */
/******************************************************************************/
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
/*$$GLOBAL VARIABLES*/
/******************************************************************************/
/* */
/* G L O B A L V A R I A B L E S */
/* */
/******************************************************************************/
 
char tx_buff[UART_TX_BUFF_LEN];
volatile int tx_level, rx_level;
 
/*$$FUNCTIONS*/
/******************************************************************************/
/* */
/* F U N C T I O N S */
/* */
/******************************************************************************/
 
void uart_init(void)
{
int devisor;
/* Reset receiver and transmiter */
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
/* Disable all interrupts */
REG8(UART_BASE + UART_IER) = 0x00;
/* Set 8 bit char, 1 stop bit, no parity */
REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
/* Set baud rate */
devisor = IN_CLK/(16 * UART_BAUD_RATE);
REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff;
REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff;
REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
return;
}
 
void uart_putc(char c)
{
unsigned char lsr;
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = c;
if(c == '\n') {
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = '\r';
}
WAIT_FOR_XMITR;
}
 
void uart_print_str(char *p)
{
while(*p != 0) {
uart_putc(*p);
p++;
}
}
 
 
void uart_print_long(unsigned long ul)
{
int i;
char c;
uart_print_str("");
 
for(i=0; i<8; i++) {
c = (char) (ul>>((7-i)*4)) & 0xf;
if(c >= 0x0 && c<=0x9)
c += '0';
else
c += 'a' - 10;
uart_putc(c);
}
}
 
 
void uart_print_short(unsigned long ul)
{
int i;
char c;
char flag=0;
 
uart_print_str("");
 
for(i=0; i<8; i++) {
c = (char) (ul>>((7-i)*4)) & 0xf;
if(c >= 0x0 && c<=0x9)
c += '0';
else
c += 'a' - 10;
if ((c != '0') || (i==7))
flag=1;
if(flag)
uart_putc(c);
}
}
 
 
 
char uart_getc()
{
unsigned char lsr;
char c;
WAIT_FOR_CHAR;
c = REG8(UART_BASE + UART_RX);
return c;
}
 
/******************************************************************************/
/* */
/* E X A M P L E U S A G E */
/* */
/******************************************************************************/
/*
int main()
{
uart_init();
// We can't use printf because in this simple example
// we don't link C library.
uart_print_str("Hello World.\n\r");
report(0xdeaddead);
exit(0);
}
*/
/sdc_dma/board.h
0,0 → 1,139
/*$$HEADER*/
/******************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/******************************************************************************/
 
// Project Name : Development Board Debugger Example
// File Name : board.h
// Prepared By : jb
// Project Start : 2009-01-01
 
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/* */
/* C O P Y R I G H T N O T I C E */
/* */
/******************************************************************************/
 
// Copyright (c) ORSoC 2009 All rights reserved.
 
// The information in this document is the property of ORSoC.
// Except as specifically authorized in writing by ORSoC, the receiver of
// this document shall keep the information contained herein confidential and
// shall protect the same in whole or in part thereof from disclosure and
// dissemination to third parties. Disclosure and disseminations to the receiver's
// employees shall only be made on a strict need to know basis.
 
 
/*$$DESCRIPTION*/
/******************************************************************************/
/* */
/* D E S C R I P T I O N */
/* */
/******************************************************************************/
 
// This file contains definitions for the FPGA board used.
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/* */
/* C H A N G E H I S T O R Y */
/* */
/******************************************************************************/
 
// Date Version Description
//------------------------------------------------------------------------
// 090101 1.0 First version jb
 
/*$$DEFINES*/
/******************************************************************************/
/* */
/* D E F I N E S */
/* */
/******************************************************************************/
 
/******************************************************************************/
/* S Y S T E M C L O C K F R E Q . */
/******************************************************************************/
#define IN_CLK 25000000 // 25MHz
 
/******************************************************************************/
/* S D R A M */
/******************************************************************************/
 
//#define SDRAM_BASE 0x00000000
//#define SDRAM_SIZE 0x02000000 // 32-MByte
//#define SDRAM_END SDRAM_BASE + SDRAM_SIZE - 1
 
/******************************************************************************/
/* G P I O */
/******************************************************************************/
// Not present in the current design
/*
#define GPIO_BASE 0x9A000000 // General purpose IO base address
#define RGPIO_IN 0x0 // GPIO input data
#define RGPIO_OUT 0x4 // GPIO output data
#define RGPIO_OE 0x8 // GPIO output enable
#define RGPIO_INTE 0xC // GPIO interrupt enable
#define RGPIO_PTRIG 0x10 // Type of event that triggers an IRQ
#define RGPIO_AUX 0x14 //
#define RGPIO_CTRL 0x18 // GPIO control register
#define RGPIO_INTS 0x1C // Interupt status
#define RGPIO_ECLK 0x20 // Enable gpio_eclk to latch RGPIO_IN
#define RGPIO_NEC 0x24 // Select active edge of gpio_eclk
*/
/******************************************************************************/
/* U A R T */
/******************************************************************************/
//#define UART_BAUD_RATE 19200
#define UART_BAUD_RATE 115200
#define UART_BASE 0x90000000
#define UART_IRQ 19
 
/******************************************************************************/
/* SD_CONTROLLER */
/******************************************************************************/
#define SD_CONTROLLER_BASE 0xa0000000
 
 
/*$$TYPEDEFS*/
/******************************************************************************/
/* */
/* T Y P E D E F S */
/* */
/******************************************************************************/
 
#ifdef INCLUDED_FROM_C_FILE
 
#define LOAD_INFO_STR
 
typedef struct load_info
{
unsigned long boardtype; //
unsigned long decompressed_crc; // Filled in by ext. program for generating SRecord file
unsigned long compressed_crc; // Filled in by ext. program for generating SRecord file
unsigned long decompressed_size; // Filled in by ext. program for generating SRecord file
unsigned long compressed_size; // Filled in by ext. program for generating SRecord file
unsigned long extra_pad[23]; // Extra padding
unsigned char boardName[12]; //
unsigned char caaName[20]; //
unsigned char caaRev[8]; //
unsigned char addInfo[16]; //
 
} LOAD_INFO;
 
 
typedef unsigned char BYTE; /* 8 bits */
typedef unsigned short WORD; /* 16 bits */
typedef unsigned long LONG_WORD; /* 32 bits */
#endif
 
#ifndef REG
#define REG register
#endif
 
/sdc_dma/ram.ld
0,0 → 1,68
/* Linker script for OR1200 program */
 
/* Linking for loading into high SDRAM */
 
MEMORY
{
ld_info : ORIGIN = 0x01000000, LENGTH = 0x000000F0
vectors : ORIGIN = 0x01000100, LENGTH = 0x00000D00 - 0x100
flash : ORIGIN = 0x01000D00, LENGTH = 0x00002000 - 0x0A00
ram : ORIGIN = 0x01003000, LENGTH = 0x00fffff0
}
 
 
/* Linking for loading into external SDRAM */
 
/*
MEMORY
{
ld_info : ORIGIN = 0x00000000, LENGTH = 0x000000F0
vectors : ORIGIN = 0x00000100, LENGTH = 0x00000D00 - 0x100
flash : ORIGIN = 0x00000D00, LENGTH = 0x00002000 - 0x0A00
ram : ORIGIN = 0x00003000, LENGTH = 0x00001000
}
*/
/*
The following section defines where to put the different input sections.
.text contains the code.
.data contains the initialized data.
.bss contains uninitialized data.
.sdata contains small constant data.
*/
 
SECTIONS
{
 
/*
.ld_info :
{
revision.o(.data)
} > ld_info
*/
.vectors : { *(.vectors) } > vectors
 
.text : { *(.text) } > ram
.rodata : { *(.rodata)} > ram
.data : { *(.data) } > ram
.bss : { *(.bss) } > ram
.stack :
{
__STACK_TOP = . ;
. = . + 0x00000500;
__STACK_BOTTOM = . ;
} > ram
}
 
/*
Definitions of identifiers that control initialization and memory allocation:
These two symbols must be present.
__BSS_START : Start of uninitialized data
__BSS_END : End of data to be cleared
*/
 
__CODE_START = ADDR( .text );
__CODE_END = ADDR( .text ) + SIZEOF( .text );
 
__DATA_START = ADDR( .bss );
__DATA_END = ADDR( .bss ) + SIZEOF( .bss );

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