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URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

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  • This comparison shows the changes necessary to convert path 
    /sdcard_mass_storage_controller/trunk
    from Rev 114 to Rev 115
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  •

Rev 114 → Rev 115

/rtl/sdc_dma/verilog/SD_Bd.v
8,9 → 8,9
input rst,
//input stb_m,
input we_m,
input re_m,
 
input [`RAM_MEM_WIDTH-1:0] dat_in_m,
output reg [`RAM_MEM_WIDTH-1:0] dat_out_m,
 
output reg [`BD_WIDTH-1 :0] free_bd,
 
input re_s,
32,7 → 32,7
reg write_cnt;
reg read_cnt;
reg [`BD_WIDTH -1 :0] m_wr_pnt;
reg [`BD_WIDTH -1 :0] m_rd_pnt;
 
reg [`BD_WIDTH -1 :0] s_rd_pnt ;
//Main side read/write
42,7 → 42,7
if (rst) begin
m_wr_pnt<=0;
m_rd_pnt<=1;
write_cnt<=0;
new_bw =0;
 
61,10 → 61,9
end
end
end
else if (re_m) begin
dat_out_m <=bd_mem[m_rd_pnt];
m_rd_pnt <=m_rd_pnt+2;
end
 
114,7 → 113,7
reg read_cnt;
 
reg [`BD_WIDTH -1 :0] m_wr_pnt;
reg [`BD_WIDTH -1 :0] m_rd_pnt;
 
reg [`BD_WIDTH -1 :0] s_rd_pnt ;
//Main side read/write
124,7 → 123,7
if (rst) begin
m_wr_pnt<=0;
m_rd_pnt<=2 ;
write_cnt<=0;
new_bw =0;
read_cnt<=0;
143,18 → 142,8
end
end
end
else if (re_m) begin //2 Reads to get a 32 bit Word
read_cnt <=~ read_cnt;
if (!read_cnt) begin
dat_out_m <=bd_mem[m_rd_pnt];
m_rd_pnt <=m_rd_pnt+1;
end
else begin
dat_out_m <=bd_mem[m_rd_pnt];
m_rd_pnt <=m_rd_pnt+3;
end
end
 
end
 
/rtl/sdc_dma/verilog/SD_controller_top.v
121,7 → 121,7
wire [15:0] status_reg_w;
wire [31:0] cmd_resp_1_w;
wire [15:0]normal_int_status_reg_w;
wire [15:0]error_int_status_reg_w;
wire [4:0]error_int_status_reg_w;
 
wire[31:0] argument_reg;
143,7 → 143,7
//Rx Buffer Descriptor internal signals
 
 
wire [`RAM_MEM_WIDTH-1:0] dat_out_m_rx_bd; //Data out from Rx_bd to Master
 
wire [`BD_WIDTH-1 :0] free_bd_rx_bd; //NO free Rx_bd
wire new_rx_bd; // New Bd writen
 
152,7 → 152,7
//Tx Buffer Descriptor internal signals
wire [`RAM_MEM_WIDTH-1:0] dat_in_m_rx_bd; //Data in to Rx_bd from Master
wire [`RAM_MEM_WIDTH-1:0] dat_in_m_tx_bd;
wire [`RAM_MEM_WIDTH-1:0] dat_out_m_tx_bd;
 
wire [`BD_WIDTH-1 :0] free_bd_tx_bd;
wire new_tx_bd;
 
214,7 → 214,7
`endif
assign sd_clk_o_pad = sd_clk_o ;
wire [15:0] settings;
wire [15:0] serial_status;
wire [7:0] serial_status;
wire [39:0] cmd_out_master;
wire [39:0] cmd_in_host;
 
333,9 → 333,9
.clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg[0]),
.we_m (we_m_rx_bd),
.re_m (re_m_rx_bd),
 
.dat_in_m (dat_in_m_rx_bd),
.dat_out_m (dat_out_m_rx_bd),
 
.free_bd (free_bd_rx_bd),
 
.re_s (re_s_rx_bd_w),
350,9 → 350,9
.clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg[0]),
.we_m (we_m_tx_bd),
.re_m (re_m_tx_bd),
 
.dat_in_m (dat_in_m_tx_bd),
.dat_out_m (dat_out_m_tx_bd),
 
.free_bd (free_bd_tx_bd),
 
.ack_o_s (ack_o_s_tx),
416,11 → 416,11
.wb_ack_o(wb_ack_o),
 
.we_m_tx_bd( we_m_tx_bd ),
.re_m_tx_bd( re_m_tx_bd ),
 
.new_cmd( new_cmd ),
.we_m_rx_bd( we_m_rx_bd ) ,
.re_m_rx_bd( re_m_rx_bd ) ,
.we_ack( we_ack ) ,
.int_ack( int_ack ) ,
.cmd_int_busy( cmd_int_busy ) ,
467,10 → 467,10
assign int_c = Bd_isr_reg & Bd_isr_enable_reg;
`endif
 
assign m_wb_sel_o = 4'b1111;
 
 
//Set Bd_Status_reg
always @ (wb_clk_i ) begin
always @ (posedge wb_clk_i ) begin
Bd_Status_reg[15:8]=free_bd_rx_bd;
Bd_Status_reg[7:0]=free_bd_tx_bd;
cmd_resp_1<= cmd_resp_1_w;
492,4 → 492,4
 
 
 
endmodule
endmodule
/rtl/sdc_dma/verilog/SD_data_host.v
1,9 → 1,5
//-------------------------
//-------------------------
 
 
 
 
`include "SD_defines.v"
 
 
49,6 → 45,7
parameter READ_DAT = 6'b100000;
reg [2:0] crc_status;
reg busy_int;
 
genvar i;
generate
for(i=0; i<`SD_BUS_W; i=i+1) begin:CRC_16_gen
160,6 → 157,8
always @ (negedge sd_clk or posedge rst )
begin : FSM_OUT
if (rst) begin
write_buf_0<=0;
write_buf_1<=0;
DAT_oe_o<=0;
crc_en<=0;
crc_rst<=1;
409,3 → 408,4
 
 
 
 
/rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
1,5 → 1,5
`include "SD_defines.v"
`include "timescale.v"
 
module SD_FIFO_RX_FILLER
(
input clk,
/rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
1,5 → 1,5
`include "SD_defines.v"
`include "timescale.v"
 
module SD_FIFO_TX_FILLER
(
input clk,
50,8 → 50,7
.rst (rst | reset_tx_fifo)
);
 
reg [3:0] t_c_buffer_0;
reg [3:0] t_c_buffer_1;
 
assign m_wb_adr_o = adr+offset;
 
 
/rtl/sdc_dma/verilog/SD_controller_wb.v
8,8 → 8,8
// WISHBONE master
 
we_m_tx_bd, re_m_tx_bd, new_cmd,
we_m_rx_bd, re_m_rx_bd,
we_m_tx_bd, new_cmd,
we_m_rx_bd,
we_ack, int_ack, cmd_int_busy,
Bd_isr_reset,
normal_isr_reset,
55,7 → 55,7
 
output reg we_m_tx_bd;
output reg re_m_tx_bd;
 
output reg new_cmd;
output reg we_ack; //CMD acces granted
output reg int_ack; //Internal Delayed Ack;
62,7 → 62,7
output reg cmd_int_busy;
 
output reg we_m_rx_bd; //Write enable Master side Rx_bd
output reg re_m_rx_bd; //Read enable Master side Rx_bd
//Read enable Master side Rx_bd
output reg int_busy;
input write_req_s;
input wire [15:0] cmd_set_s;
96,7 → 96,7
`define bd_tx 8'h80
 
 
assign m_wb_sel_o = 4'b1111;
 
`ifdef SUPPLY_VOLTAGE_3_3
parameter power_controll_reg = 8'b0000_111_1;
`elsif SUPPLY_VOLTAGE_3_0
308,4 → 308,4
 
endmodule
endmodule
/rtl/sdc_dma/verilog/SD_defines.v
6,7 → 6,7
//`define SIM
`define SYN
 
//`define IRQ_ENABLE
`define IRQ_ENABLE
`define ACTEL
 
`define CUSTOM
28,8 → 28,8
 
`ifdef CUSTOM
`define NR_O_BD_4
`define BD_WIDTH 4
`define BD_SIZE 16
`define BD_WIDTH 5
`define BD_SIZE 32
`define RAM_MEM_WIDTH_16
`define RAM_MEM_WIDTH 16
`endif
37,7 → 37,7
`define RESEND_MAX_CNT 3
 
`ifdef SYN
`define RESET_CLK_DIV 0
`define RESET_CLK_DIV 1
`define MEM_OFFSET 4
`endif
 
70,11 → 70,11
 
 
//FIFO defines---------------
`define FIFO_RX_MEM_DEPTH 16
`define FIFO_RX_MEM_ADR_SIZE 5
`define FIFO_RX_MEM_DEPTH 4
`define FIFO_RX_MEM_ADR_SIZE 3
 
`define FIFO_TX_MEM_DEPTH 16
`define FIFO_TX_MEM_ADR_SIZE 5
`define FIFO_TX_MEM_DEPTH 4
`define FIFO_TX_MEM_ADR_SIZE 3
//---------------------------
 
 
84,3 → 84,4
 
 
 
 
/rtl/sdc_dma/verilog/SD_cmd_master.v
15,7 → 15,7
output reg [15:0] STATUS_REG,
output reg [31:0] RESP_1_REG,
 
output reg [15:0] ERR_INT_REG,
output reg [4:0] ERR_INT_REG,
output reg [15:0] NORMAL_INT_REG,
input ERR_INT_RST,
input NORMAL_INT_RST,
294,4 → 294,4
end
end
 
endmodule
endmodule
/rtl/sdc_dma/verilog/SD_cmd_serial_host.v
16,7 → 16,7
output [39:0] CMD_OUT;
output ACK_OUT;
output REQ_OUT;
output [15:0] STATUS;
output [7:0] STATUS;
output reg cmd_oe_o;
output reg cmd_out_o;
output reg [1:0] st_dat_t;
31,7 → 31,7
//---------------Output ports Data Type------
reg [39:0] CMD_OUT;
wire ACK_OUT ;
reg [15:0] STATUS;
reg [7:0] STATUS;
reg REQ_OUT;
 
//-------------Internal Constant-------------

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