Subversion Repositories sdhc-sc-core

/unitIcs307Configurator/src/tbIcs307Configurator-e.vhdl

unitIcs307Configurator/src/tbIcs307Configurator-e.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: unitIcs307Configurator/src/Ics307Configurator-Rtl-a.vhdl =================================================================== --- unitIcs307Configurator/src/Ics307Configurator-Rtl-a.vhdl (nonexistent) +++ unitIcs307Configurator/src/Ics307Configurator-Rtl-a.vhdl (revision 79) @@ -0,0 +1,156 @@ +------------------------------------------------------------------------------- +-- Title: +-- Project: FH-Hagenberg/HSSE: Sandbox X general use IP +-- Author: Copyright 2006 by Markus Pfaff, Linz/Austria/Europe +------------------------------------------------------------------------------- +-- $LastChangedDate: 2007-01-09 08:40:02 +0100 (Di, 09 Jän 2007) $ +-- $LastChangedRevision: 415 $ +-- $LastChangedBy: pfaff $ +-- $HeadURL: file:///C:/pfaff/rpySvn/rpySvnSet5/trunk/Uebung/W06Jg04/Uebung03/unitIcs307Configurator/src/Ics307Configurator-Rtl-a.vhd $ +-- LoginNames: pfaff - Markus Pfaff, Linz/Austria/Europe +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +architecture Rtl of Ics307Configurator is + + ----------------------------------------------------------------------------- + -- register definition + ----------------------------------------------------------------------------- + type aActivity is (Transmitting, LatchingIn, Completed); + type aRegion is (RegionC, RegionTTL, RegionF, RegionS, RegionV, RegionR); + subtype aBitIdx is integer range 0 to 8; + subtype aCycleCtr is integer range 0 to 7; + + type aRegSet is record + Activity : aActivity; + Region : aRegion; + BitIdx : aBitIdx; + CycleCtr : aCycleCtr; + Sclk : std_ulogic; + Data : std_ulogic; + end record aRegSet; + + signal R, NxR : aRegSet; + + constant cRinitVal : aRegSet := ( + Activity => Transmitting, + Region => RegionC, + BitIdx => aBitIdx'low, + CycleCtr => aCycleCtr'low, + Sclk => '0', + Data => '0' + ); + +begin + + ------------ + -- Registers + ------------ + Registers : process(iClk, inResetAsync) + begin + if (inResetAsync = cnActivated) then + R <= cRinitVal; + elsif ((iClk'event) and (iClk = '1')) then + R <= NxR; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Nx State and Output Logic: Combinatorial + ----------------------------------------------------------------------------- + NxStateAndOutput : process ( + R + ) + + begin + + --------------------------------------------------------------------------- + -- Set Nx State Defaults + --------------------------------------------------------------------------- + NxR <= R; + + --------------------------------------------------------------------------- + -- Set Output Defaults + --------------------------------------------------------------------------- + oStrobe <= cInactivated; + + --------------------------------------------------------------------------- + -- Consider Actual States and Inputs + --------------------------------------------------------------------------- + case R.Activity is + + when Transmitting => + -- Generating Sclk + if R.CycleCtr /= aCycleCtr'high then + NxR.CycleCtr <= R.CycleCtr + 1; + else + NxR.CycleCtr <= 0; + if R.Sclk = '0' then + -- rising edge of Sclk + NxR.Sclk <= '1'; + else + -- falling edge of Sclk + NxR.Sclk <= '0'; + -- Adjust Region and BitIdx + if R.BitIdx = 0 then + -- The order of regions is given in the data sheet on page 5. + case R.Region is + when RegionC => + NxR.Region <= RegionTTL; + when RegionTTL => + NxR.BitIdx <= gClkFunctionSelect_R'left; + NxR.Region <= RegionF; + when RegionF => + NxR.BitIdx <= gOutputDivide_S'left; + NxR.Region <= RegionS; + when RegionS => + NxR.BitIdx <= gVcoDividerWord_VDW'left; + NxR.Region <= RegionV; + when RegionV => + NxR.BitIdx <= gReferenceDivider_RDW'left; + NxR.Region <= RegionR; + when RegionR => + NxR.Activity <= LatchingIn; + end case; + else + NxR.BitIdx <= R.BitIdx - 1; + end if; + end if; + end if; + + when LatchingIn => + oStrobe <= cActivated; + if R.CycleCtr /= aCycleCtr'high then + NxR.CycleCtr <= R.CycleCtr +1; + else + NxR.Activity <= Completed; + end if; + + when Completed => + null; + + end case; + + -- Determine data output + case R.Region is + -- The order of regions is given in the data sheet on page 5. + when RegionC => + oData <= gCrystalLoadCapacitance_C (R.BitIdx); + when RegionTTL => + oData <= gOutputDutyCycleVoltage_TTL; + when RegionF => + oData <= gClkFunctionSelect_R(R.BitIdx); + when RegionS => + oData <= gOutputDivide_S (R.BitIdx); + when RegionV => + oData <= gVcoDividerWord_VDW (R.BitIdx); + when RegionR => + oData <= gReferenceDivider_RDW (R.BitIdx); + end case; + + end process NxStateAndOutput; + + oSclk <= R.Sclk; + +end Rtl;

unitIcs307Configurator/src/Ics307Configurator-Rtl-a.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: unitIcs307Configurator/src/tbIcs307Configurator-Bhv-a.vhdl =================================================================== --- unitIcs307Configurator/src/tbIcs307Configurator-Bhv-a.vhdl (nonexistent) +++ unitIcs307Configurator/src/tbIcs307Configurator-Bhv-a.vhdl (revision 79) @@ -0,0 +1,76 @@ +------------------------------------------------------------------------------- +-- Project: FH-Hagenberg/HSSE: Sandbox X general use IP +-- Author: Copyright 2006 by Markus Pfaff, Linz/Austria/Europe +------------------------------------------------------------------------------- +-- $LastChangedDate: 2007-01-09 08:40:02 +0100 (Di, 09 Jän 2007) $ +-- $LastChangedRevision: 415 $ +-- $LastChangedBy: pfaff $ +-- $HeadURL: file:///C:/pfaff/rpySvn/rpySvnSet5/trunk/Uebung/W06Jg04/Uebung03/unitIcs307Configurator/src/tbIcs307Configurator-Bhv-a.vhd $ +-- LoginNames: pfaff - Markus Pfaff, Linz/Austria/Europe +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.Global.all; + +-------------------------------------------------------------------------------- + +architecture Bhv of tbIcs307Configurator is + + -- component generics + constant cClkFrequency : natural := 25E6; + constant cIsLowPercentageOfDutyCycle : natural := 65; + constant cInResetDuration : time := 140 ns; + constant cStrobeFrequency : natural := 12E6; + + -- component ports + signal Clk : std_ulogic; + signal nResetAsync : std_ulogic; + signal Strobe : std_ulogic; + signal Sclk : std_ulogic; + signal Data : std_ulogic; + + +begin -- architecture Behavioral + + Ics307Configurator_1 : entity work.Ics307Configurator + --generic map ( + -- gCrystalLoadCapacitance_C => gCrystalLoadCapacitance_C, + -- gReferenceDivider_RDW => gReferenceDivider_RDW, + -- gVcoDividerWord_VDW => gVcoDividerWord_VDW, + -- gOutputDivide_S => gOutputDivide_S, + -- gClkFunctionSelect_R => gClkFunctionSelect_R, + -- gOutputDutyCycleVoltage_TTL => gOutputDutyCycleVoltage_TTL) + port map ( + iClk => Clk, + inResetAsync => nResetAsync, + oSclk => Sclk, + oData => Data, + oStrobe => Strobe); + + -- reset generation + PwrOnResetSource : entity work.PwrOnReset + generic map ( + gInResetDuration => cInResetDuration) + port map ( + onResetAsync => nResetAsync); + + ICS307_1: entity work.ICS307 + port map ( + iSclk => Sclk, + iData => Data, + iStrobe => Strobe, + oClk1 => Clk); + + StopSim : process is + begin + wait for 6 ms; + assert false + report "MP: Simulation stopped intenionally!" + severity failure; + wait; + end process StopSim; + +end architecture Bhv;

unitIcs307Configurator/src/tbIcs307Configurator-Bhv-a.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: unitIcs307Configurator/src/Ics307Configurator-e.vhdl =================================================================== --- unitIcs307Configurator/src/Ics307Configurator-e.vhdl (nonexistent) +++ unitIcs307Configurator/src/Ics307Configurator-e.vhdl (revision 79) @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- Title : Programmer for ICS307 +-- Project : General IP +------------------------------------------------------------------------------- +-- Author : Copyright 2006: Markus Pfaff, Linz +-- Standard : Using VHDL'93 +------------------------------------------------------------------------------- +-- Description: Configures an ICS Serially Programmable Clock +-- Synthesizer immediately after FPGA configuration. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.global.all; + +entity Ics307Configurator is + generic( + -- Default settings for 25 MHz input clk and 48 MHz on clk1 + -- Parameters in the order implied by the block diagramm on title + -- page of data sheet. The data word given by online calculator + -- (see data sheet page 3) is "001001000000100000000011". This + -- data word contains the following parameters: + -- Set for lowest crystal load capacitance, + gCrystalLoadCapacitance_C : std_ulogic_vector(1 downto 0) := "00"; + -- divide by (3+2), + gReferenceDivider_RDW : std_ulogic_vector(6 downto 0) := "0000011"; + -- multiply by (16+8), + gVcoDividerWord_VDW : std_ulogic_vector(8 downto 0) := "000010000"; + -- divide by 5, + gOutputDivide_S : std_ulogic_vector(2 downto 0) := "100"; + -- set source of Clk2 to REF clk (i.e. input clk), + gClkFunctionSelect_R : std_ulogic_vector(1 downto 0) := "00"; + -- CMOS voltage levels for 3.3V. + gOutputDutyCycleVoltage_TTL : std_ulogic := '1' + ); + + port( + iClk : in std_ulogic; + inResetAsync : in std_ulogic; + + -- 3 wire SPI interface for configuration + oSclk : out std_ulogic; + oData : out std_ulogic; + oStrobe : out std_ulogic + ); +end entity Ics307Configurator;

unitIcs307Configurator/src/Ics307Configurator-e.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property